Lines Matching +full:fifo +full:- +full:width
40 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf
42 * This is a from-scratch driver under the BSD license using the Intel data
61 * Register width is 32-bits
87 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */
88 #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */
102 #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */
103 #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */
117 #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
118 /* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
135 * CTL - Control Register 22.2.1
138 * RESTARTEN - RW Restart Enable
139 * 10BIT - RW Controller operates in 10-bit mode, else 7-bit
145 * Performing any high-speed mode op
147 * Performing a read operation with a 10-bit address
154 #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */
163 * TAR_ADD - Target Address Register 22.2.2
166 * 10BIT - RW controller starts its transfers in 10-bit
167 * address mode, else 7-bit.
169 * SPECIAL - RW Indicates whether software performs a General Call
176 * GC_OR_START - RW (only if SPECIAL is set)
187 * IC_TAR - RW when transmitting a general call, these bits are
193 #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */
199 * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3
201 * RESTART - RW This bit controls whether a forced RESTART is
211 * STOP - RW This bit controls whether a STOP is issued after
215 * of whether or not the Tx FIFO is empty.
218 * whether or not the Tx FIFO is empty. If the
219 * Tx FIFO is not empty the master immediately tries
226 * COMMAND - RW Control whether a read or write is performed.
232 * DATA (7:0) - RW Contains the data to be transmitted or received
241 * receive FIFO.
250 * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4
251 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5
252 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6
253 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7
255 * COUNT (15:0) - Set the period count to a value between 6 and
261 * INTR_STAT - (RO) Interrupt Status Register 22.2.8
262 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9
263 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10
280 * the controller will hold the TX FIFO in a reset
282 * clear the condition. Once cleared, the TX FIFO
291 * to the TX FIFO while the TX FIFO was full. Cleared
294 * RX_FULL Indicates that the receive FIFO has reached or
296 * by HW when the cpu drains the FIFO to below the
299 * RX_OVER Indicates that the receive FIFO was unable to
304 * from the receive buffer while the RX FIFO was
314 * Code should test FIFO conditions using the I2C_STA (status) register,
333 * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11
334 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12
336 * Specify the receive and transmit FIFO threshold register. The
337 * FIFOs have 16 elements. The valid range is 0-15. Setting a
339 * depth of the FIFO.
342 * mid-level setting for both parameters and (e.g.) fully drain the
343 * receive FIFO on the STOP_DET condition to handle loose ends.
349 * CLR_INTR - (RO) Clear Interrupt Register 22.2.13
350 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14
351 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15
352 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16
353 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17
354 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18
355 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19
356 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20
357 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21
366 * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware
371 * the TX FIFO from its flushed/reset state, allowing more writes
372 * to the TX FIFO.
381 * I2C_EN - (RW) I2C Enable Register 22.2.22
385 * condition over the I2C bus, followed by TX FIFO flush.
398 * I2C_STA - (RO) I2C Status Register 22.2.23
401 #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */
402 #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */
403 #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */
404 #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */
408 * TXFLR - (RO) Transmit FIFO Level Register 22.2.24
409 * RXFLR - (RO) Receive FIFO Level Register 22.2.25
418 * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26
425 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27
428 * software programming error or a device expected address width
449 * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28
462 * DMA_CTRL - (RW) DMA Control Register 22.2.29
470 * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30
471 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31
480 * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32
489 * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33
500 * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34
502 * DATA_LOST - Indicates that a slave receiver operation has
505 * disabled (IG4_I2C_ENABLE -> 0)
507 * ENABLED - Intel documentation is lacking but I assume this
516 * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35
519 * VALID - Intel documentation is unclear but I believe this
523 * HASDMA - Indicates that the chip is DMA-capable. Presumably
525 * set to not be DMA-capable.
527 * INTR_IO - Indicates that all interrupts are combined to
531 * HCCNT_RO - Indicates that the clock timing registers are
535 * MAXSPEED - Indicates the maximum speed supported.
537 * DATAW - Indicates the internal bus width in bits.
559 * COMP_VER - (RO) Component Version Register 22.2.36
566 * COMP_TYPE - (RO) (linux) Endian and bus width probe
569 * to determine the bus width. e.g. 01404457 = endian-reversed,
570 * and 00000140 or 00004457 means internal 16-bit bus (?).
573 * from the linux driver i2c-designware-core.c.
578 * RESETS - (RW) Resets Register 22.2.37
581 * requirement, software can assert and de-assert in back-to-back
592 /* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */
608 * GENERAL - (RW) General Reigster 22.2.38
627 * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39
628 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40
635 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it