Lines Matching +full:0 +full:x00000064
63 * 22.2 Default Values on device reset are 0 except as specified here:
64 * TAR_ADD 0x00000055
65 * SS_SCL_HCNT 0x00000264
66 * SS_SCL_LCNT 0x000002C2
67 * FS_SCL_HCNT 0x0000006E
68 * FS_SCL_LCNT 0x000000CF
69 * INTR_MASK 0x000008FF
70 * I2C_STA 0x00000006
71 * SDA_HOLD 0x00000001
72 * SDA_SETUP 0x00000064
73 * COMP_PARAM1 0x00FFFF6E
76 #define IG4_REG_CTL 0x0000 /* RW Control Register */
77 #define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */
78 #define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/
79 #define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */
80 #define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */
81 #define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */
82 #define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */
83 #define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */
84 #define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */
85 #define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */
86 #define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */
87 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */
88 #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */
89 #define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */
90 #define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */
91 #define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */
92 #define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */
93 #define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */
94 #define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */
95 #define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */
96 #define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */
97 #define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */
98 #define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */
99 #define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */
100 #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */
101 #define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */
102 #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */
103 #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */
104 #define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */
105 #define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */
106 #define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */
107 #define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */
108 #define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */
109 #define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */
110 #define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */
111 #define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */
112 #define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */
114 #define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */
115 #define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */
117 #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
118 /* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */
119 #define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */
120 #define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */
121 #define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */
122 #define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */
123 #define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */
124 #define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */
126 #define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */
128 #define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */
129 #define IG4_REG_GENERAL 0x0808 /* RW General Register */
131 #define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */
132 #define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */
136 * Default Value: 0x0000007F.
152 #define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */
153 #define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */
154 #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */
155 #define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */
156 #define IG4_CTL_MASTER 0x0001 /* snarfed from linux */
158 #define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */
159 #define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */
160 #define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */
164 * Default Value: 0x00000055F
172 * 0 Ignore GC_OR_START and use TAR address.
178 * 0 General Call Address. After issuing a General Call,
191 * This register should only be updated when the IIC is disabled (I2C_ENABLE=0)
193 #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */
194 #define IG4_TAR_SPECIAL 0x0800 /* Perform special command */
195 #define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */
196 #define IG4_TAR_ADDR_MASK 0x03FF /* Target address */
204 * 0 If not set a RESTART is only issued if the transfer
214 * 0 STOP is not issued after this byte, regardless
228 * 0 WRITE
232 * DATA (7:0) - RW Contains the data to be transmitted or received
244 #define IG4_DATA_RESTART 0x0400 /* Force RESTART */
245 #define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */
246 #define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */
247 #define IG4_DATA_MASK 0x00FF
255 * COUNT (15:0) - Set the period count to a value between 6 and
258 #define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */
318 #define IG4_INTR_GEN_CALL 0x0800
319 #define IG4_INTR_START_DET 0x0400
320 #define IG4_INTR_STOP_DET 0x0200
321 #define IG4_INTR_ACTIVITY 0x0100
322 #define IG4_INTR_TX_ABRT 0x0040
323 #define IG4_INTR_TX_EMPTY 0x0010
324 #define IG4_INTR_TX_OVER 0x0008
325 #define IG4_INTR_RX_FULL 0x0004
326 #define IG4_INTR_RX_OVER 0x0002
327 #define IG4_INTR_RX_UNDER 0x0001
337 * FIFOs have 16 elements. The valid range is 0-15. Setting a
345 #define IG4_FIFO_MASK 0x00FF
378 #define IG4_CLR_BIT 0x0001 /* Reflects source */
394 #define IG4_I2C_ABORT 0x0002
395 #define IG4_I2C_ENABLE 0x0001
400 #define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */
401 #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */
402 #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */
403 #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */
404 #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */
405 #define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */
415 #define IG4_FIFOLVL_MASK 0x01FF
422 #define IG4_SDA_TX_HOLD_MASK 0x0000FFFF
436 #define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */
437 #define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */
438 #define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */
439 #define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */
440 #define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */
441 #define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */
442 #define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */
443 #define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */
444 #define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */
445 #define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */
446 #define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */
454 * NACK_GENERATE Set to 0 for normal NACK/ACK generation.
459 #define IG4_NACK_GENERATE 0x0001
466 #define IG4_TX_DMA_ENABLE 0x0002
467 #define IG4_RX_DMA_ENABLE 0x0001
484 * (Defaults to 0x64).
486 #define IG4_SDA_SETUP_MASK 0x00FF
494 * If set to 0 a NACK is generated and a General Call interrupt is
497 #define IG4_ACKGC_ACK 0x0001
505 * disabled (IG4_I2C_ENABLE -> 0)
512 #define IG4_ENASTAT_DATA_LOST 0x0004
513 #define IG4_ENASTAT_ENABLED 0x0001
517 * Default Value 0x00FFFF6E
539 #define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1)
540 #define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1)
541 #define IG4_PARAM1_CONFIG_VALID 0x00000080
542 #define IG4_PARAM1_CONFIG_HASDMA 0x00000040
543 #define IG4_PARAM1_CONFIG_INTR_IO 0x00000020
544 #define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010
545 #define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C
546 #define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003
548 #define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000
549 #define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004
550 #define IG4_CONFIG_MAXSPEED_FAST 0x00000008
551 #define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C
553 #define IG4_CONFIG_DATAW_8 0x00000000
554 #define IG4_CONFIG_DATAW_16 0x00000001
555 #define IG4_CONFIG_DATAW_32 0x00000002
556 #define IG4_CONFIG_DATAW_RESERVED11 0x00000003
563 #define IG4_COMP_MIN_VER 0x3131352A
575 #define IG4_COMP_TYPE 0x44570140
589 #define IG4_RESETS_ASSERT_HSW 0x0003
590 #define IG4_RESETS_DEASSERT_HSW 0x0000
593 #define IG4_RESETS_DEASSERT_SKL 0x0003
594 #define IG4_RESETS_ASSERT_SKL 0x0000
604 #define IG4_RESTORE_REQUIRED 0x0008
605 #define IG4_DEVICE_IDLE 0x0004
610 * IOVOLT 0=1.8V 1=3.3V
612 * LTR 0=Auto 1=SW
615 * AUTO LTR Value register (offset 0x0814) with the active
617 * (offset 0x0810) with the idle state LTR value.
620 * value (offset 0x0810). It is the SW responsibility to update
623 #define IG4_GENERAL_IOVOLT3_3 0x0008
624 #define IG4_GENERAL_SWMODE 0x0004
630 * Default value is 0x00000800 which means the best possible
635 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it
640 * delay (0) probably runs the controller polling at a high, power hungry
643 #define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */
644 #define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */
645 #define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */
646 #define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */
647 #define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F)
648 #define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16)
650 #define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */
651 #define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */
652 #define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */
653 #define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */
654 #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F)
655 #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F)