910 	for (i = 0; i < vsi->num_rx_queues; i++)  in ice_free_irqvs()
1167 	vsi->num_rx_queues = nrxqsets;  in ice_if_rx_queues_alloc()
1228 		vsi->num_rx_queues = 0;  in ice_if_queues_free()
1604 	if (vsi->num_rx_queues != vsi->num_tx_queues) {  in ice_if_msix_intr_assign()
1607 			      vsi->num_tx_queues, vsi->num_rx_queues);  in ice_if_msix_intr_assign()
1611 	if (msix < (vsi->num_rx_queues + 1)) {  in ice_if_msix_intr_assign()
1618 	sc->num_irq_vectors = vsi->num_rx_queues + 1;  in ice_if_msix_intr_assign()
1645 	for (i = 0, vector = 1; i < vsi->num_rx_queues; i++, vector++) {  in ice_if_msix_intr_assign()
1744 	for (int i = 0; i < vsi->num_rx_queues; i++)  in ice_if_intr_enable()
2459 				    sc->pf_vsi.num_rx_queues);  in ice_prepare_for_reset()
2501 					    vsi->num_rx_queues);  in ice_rebuild_pf_vsi_qmap()
2515 	for (i = 0, rxq = vsi->rx_queues; i < vsi->num_rx_queues; i++, rxq++)  in ice_rebuild_pf_vsi_qmap()
2767 				    sc->pf_vsi.num_rx_queues);  in ice_rebuild()
3592 	vsi->num_tx_queues = vsi->num_rx_queues = ICE_DEFAULT_VF_QUEUES;  in ice_setup_mirror_vsi()
3604 	    vsi->num_rx_queues);  in ice_setup_mirror_vsi()
3786 	for (i = 0; i < vsi->num_rx_queues; i++, rid++) {  in ice_wire_mirror_intrs()
3926 	for (i = 0, rxq = vsi->rx_queues; i < vsi->num_rx_queues; i++, rxq++)  in ice_subif_rebuild_vsi_qmap()
4048 	MPASS(vsi->num_rx_queues == nrxqsets);  in ice_subif_if_rx_queues_alloc()
4098 	if (vsi->num_rx_queues != vsi->num_tx_queues) {  in ice_subif_if_msix_intr_assign()
4101 			      vsi->num_tx_queues, vsi->num_rx_queues);  in ice_subif_if_msix_intr_assign()
4115 	mif->num_irq_vectors = vsi->num_rx_queues;  in ice_subif_if_msix_intr_assign()
4186 	for (int i = 0; i < vsi->num_rx_queues; i++)  in ice_subif_if_intr_enable()
4385 	for (i = 0; i < vsi->num_rx_queues; i++)  in ice_free_irqvs_subif()
4393 	sc->last_rid -= vsi->num_rx_queues;  in ice_free_irqvs_subif()
4396 	for (i = 0; i < vsi->num_rx_queues; i++)  in ice_free_irqvs_subif()