Lines Matching +full:max +full:- +full:memory +full:- +full:bandwidth
1 /* SPDX-License-Identifier: BSD-3-Clause */
35 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB
52 hw = pi->hw;
58 root->children = (struct ice_sched_node **)
59 ice_calloc(hw, hw->max_children[0], sizeof(*root->children));
60 if (!root->children) {
65 ice_memcpy(&root->info, info, sizeof(*info), ICE_NONDMA_TO_NONDMA);
66 pi->root = root;
71 * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB
72 * @start_node: pointer to the starting ice_sched_node struct in a sub-tree
77 * layers it has searched through; stopping at the max supported layer.
79 * This function needs to be called when holding the port_info->sched_lock
93 /* The node has no children or is at the max layer */
94 if (!start_node->num_children ||
95 start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM ||
96 start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF)
100 for (i = 0; i < start_node->num_children; i++)
101 if (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid)
102 return start_node->children[i];
104 /* Search within each child's sub-tree */
105 for (i = 0; i < start_node->num_children; i++) {
108 tmp = ice_sched_find_node_by_teid(start_node->children[i],
118 * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd
140 cmd->num_elem_req = CPU_TO_LE16(elems_req);
144 *elems_resp = LE16_TO_CPU(cmd->num_elem_resp);
150 * ice_aq_query_sched_elems - query scheduler elements
171 * ice_sched_add_node - Insert the Tx scheduler node in SW DB
193 hw = pi->hw;
196 parent = ice_sched_find_node_by_teid(pi->root,
197 LE32_TO_CPU(info->parent_teid));
200 LE32_TO_CPU(info->parent_teid));
207 status = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem);
217 if (hw->max_children[layer]) {
218 node->children = (struct ice_sched_node **)
219 ice_calloc(hw, hw->max_children[layer],
220 sizeof(*node->children));
221 if (!node->children) {
227 node->in_use = true;
228 node->parent = parent;
229 node->tx_sched_layer = layer;
230 parent->children[parent->num_children++] = node;
231 node->info = elem;
236 * ice_aq_delete_sched_elems - delete scheduler elements
257 * ice_sched_remove_elems - remove nodes from HW
279 buf->hdr.parent_teid = parent->info.node_teid;
280 buf->hdr.num_elems = CPU_TO_LE16(num_nodes);
282 buf->teid[i] = CPU_TO_LE32(node_teids[i]);
288 hw->adminq.sq_last_status);
295 * ice_sched_get_first_node - get the first node of the given layer
306 return pi->sib_head[parent->tc_num][layer];
310 * ice_sched_get_tc_node - get pointer to TC node
320 if (!pi || !pi->root)
322 for (i = 0; i < pi->root->num_children; i++)
323 if (pi->root->children[i]->tc_num == tc)
324 return pi->root->children[i];
329 * ice_free_sched_node - Free a Tx scheduler node from SW DB
335 * This function needs to be called with the port_info->sched_lock held
340 struct ice_hw *hw = pi->hw;
347 while (node->num_children)
348 ice_free_sched_node(pi, node->children[0]);
351 if (node->tx_sched_layer >= hw->sw_entry_point_layer &&
352 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&
353 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT &&
354 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) {
355 u32 teid = LE32_TO_CPU(node->info.node_teid);
357 ice_sched_remove_elems(hw, node->parent, 1, &teid);
359 parent = node->parent;
365 for (i = 0; i < parent->num_children; i++)
366 if (parent->children[i] == node) {
367 for (j = i + 1; j < parent->num_children; j++)
368 parent->children[j - 1] =
369 parent->children[j];
370 parent->num_children--;
374 p = ice_sched_get_first_node(pi, node, node->tx_sched_layer);
376 if (p->sibling == node) {
377 p->sibling = node->sibling;
380 p = p->sibling;
384 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node)
385 pi->sib_head[node->tc_num][node->tx_sched_layer] =
386 node->sibling;
390 if (node->children)
391 ice_free(hw, node->children);
396 * ice_aq_get_dflt_topo - gets default scheduler topology
417 cmd->port_num = lport;
420 *num_branches = cmd->num_branches;
426 * ice_aq_add_sched_elems - adds scheduling element
447 * ice_aq_cfg_sched_elems - configures scheduler elements
468 * ice_aq_move_sched_elems - move scheduler elements
489 * ice_aq_suspend_sched_elems - suspend scheduler elements
509 * ice_aq_resume_sched_elems - resume scheduler elements
529 * ice_aq_query_sched_res - query scheduler resource
549 * ice_sched_suspend_resume_elems - suspend or resume HW nodes
589 * ice_alloc_lan_q_ctx - allocate LAN queue contexts for the given VSI and TC
605 if (!vsi_ctx->lan_q_ctx[tc]) {
606 vsi_ctx->lan_q_ctx[tc] = (struct ice_q_ctx *)
608 if (!vsi_ctx->lan_q_ctx[tc])
610 vsi_ctx->num_lan_q_entries[tc] = new_numqs;
614 if (new_numqs > vsi_ctx->num_lan_q_entries[tc]) {
615 u16 prev_num = vsi_ctx->num_lan_q_entries[tc];
621 ice_memcpy(q_ctx, vsi_ctx->lan_q_ctx[tc],
623 ice_free(hw, vsi_ctx->lan_q_ctx[tc]);
624 vsi_ctx->lan_q_ctx[tc] = q_ctx;
625 vsi_ctx->num_lan_q_entries[tc] = new_numqs;
631 * ice_alloc_rdma_q_ctx - allocate RDMA queue contexts for the given VSI and TC
647 if (!vsi_ctx->rdma_q_ctx[tc]) {
648 vsi_ctx->rdma_q_ctx[tc] = (struct ice_q_ctx *)
650 if (!vsi_ctx->rdma_q_ctx[tc])
652 vsi_ctx->num_rdma_q_entries[tc] = new_numqs;
656 if (new_numqs > vsi_ctx->num_rdma_q_entries[tc]) {
657 u16 prev_num = vsi_ctx->num_rdma_q_entries[tc];
663 ice_memcpy(q_ctx, vsi_ctx->rdma_q_ctx[tc],
665 ice_free(hw, vsi_ctx->rdma_q_ctx[tc]);
666 vsi_ctx->rdma_q_ctx[tc] = q_ctx;
667 vsi_ctx->num_rdma_q_entries[tc] = new_numqs;
673 * ice_aq_rl_profile - performs a rate limiting task
697 cmd->num_profiles = CPU_TO_LE16(num_profiles);
700 *num_processed = LE16_TO_CPU(cmd->num_processed);
705 * ice_aq_add_rl_profile - adds rate limiting profile(s)
725 * ice_aq_query_rl_profile - query rate limiting profile(s)
744 * ice_aq_remove_rl_profile - removes RL profile(s)
765 * ice_sched_del_rl_profile - remove RL profile
782 if (rl_info->prof_id_ref != 0)
786 buf = &rl_info->profile;
793 LIST_DEL(&rl_info->list_entry);
799 * ice_sched_clear_rl_prof - clears RL prof entries
807 struct ice_hw *hw = pi->hw;
809 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) {
814 &hw->rl_prof_list[ln],
818 rl_prof_elem->prof_id_ref = 0;
823 LIST_DEL(&rl_prof_elem->list_entry);
831 * ice_sched_clear_agg - clears the aggregator related information
834 * This function removes aggregator list and free up aggregator related memory
842 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &hw->agg_list,
849 &agg_info->agg_vsi_list,
851 LIST_DEL(&agg_vsi_info->list_entry);
854 LIST_DEL(&agg_info->list_entry);
860 * ice_sched_clear_tx_topo - clears the scheduler tree nodes
871 if (pi->root) {
872 ice_free_sched_node(pi, pi->root);
873 pi->root = NULL;
878 * ice_sched_clear_port - clear the scheduler elements from SW DB for a port
885 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
888 pi->port_state = ICE_SCHED_PORT_STATE_INIT;
889 ice_acquire_lock(&pi->sched_lock);
891 ice_release_lock(&pi->sched_lock);
892 ice_destroy_lock(&pi->sched_lock);
896 * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports
906 if (hw->layer_info) {
907 ice_free(hw, hw->layer_info);
908 hw->layer_info = NULL;
911 ice_sched_clear_port(hw->port_info);
913 hw->num_tx_sched_layers = 0;
914 hw->num_tx_sched_phys_layers = 0;
915 hw->flattened_layers = 0;
916 hw->max_cgds = 0;
920 * ice_aq_cfg_node_attr - configure nodes' per-cone flattening attributes
942 cmd->num_entries = CPU_TO_LE16(num_nodes);
947 * ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping
968 cmd->num_l2_nodes = CPU_TO_LE16(num_l2_nodes);
973 * ice_sched_add_elems - add nodes to HW and SW DB
994 struct ice_hw *hw = pi->hw;
1004 buf->hdr.parent_teid = parent->info.node_teid;
1005 buf->hdr.num_elems = CPU_TO_LE16(num_nodes);
1007 buf->generic[i].parent_teid = parent->info.node_teid;
1008 buf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC;
1009 buf->generic[i].data.valid_sections =
1012 buf->generic[i].data.generic = 0;
1013 buf->generic[i].data.cir_bw.bw_profile_idx =
1015 buf->generic[i].data.cir_bw.bw_alloc =
1017 buf->generic[i].data.eir_bw.bw_profile_idx =
1019 buf->generic[i].data.eir_bw.bw_alloc =
1027 hw->adminq.sq_last_status);
1036 status = ice_sched_add_node(pi, layer, &buf->generic[i], prealloc_nodes[i]);
1038 status = ice_sched_add_node(pi, layer, &buf->generic[i], NULL);
1046 teid = LE32_TO_CPU(buf->generic[i].node_teid);
1053 new_node->sibling = NULL;
1054 new_node->tc_num = tc_node->tc_num;
1060 while (prev->sibling)
1061 prev = prev->sibling;
1062 prev->sibling = new_node;
1066 if (!pi->sib_head[tc_node->tc_num][layer])
1067 pi->sib_head[tc_node->tc_num][layer] = new_node;
1078 * ice_sched_add_nodes_to_hw_layer - Add nodes to hw layer
1103 if (!parent || layer < pi->hw->sw_entry_point_layer)
1106 /* max children per node per layer */
1107 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer];
1109 /* current number of children + required nodes exceed max children */
1110 if ((parent->num_children + num_nodes) > max_child_nodes) {
1122 * ice_sched_add_nodes_to_layer - Add nodes to a given layer
1157 ice_debug(pi->hw, ICE_DBG_SCHED, "added extra nodes %d %d\n", num_nodes,
1165 /* break if the error is not max limit */
1168 /* Exceeded the max children */
1169 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer];
1171 if (parent->num_children < max_child_nodes) {
1172 new_num_nodes = max_child_nodes - parent->num_children;
1175 parent = parent->sibling;
1176 /* Don't modify the first node TEID memory if the
1178 * Instead send some temp memory for all other
1184 new_num_nodes = num_nodes - *num_nodes_added;
1191 * ice_sched_get_qgrp_layer - get the current queue group layer number
1198 /* It's always total layers - 1, the array is 0 relative so -2 */
1199 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;
1203 * ice_sched_get_vsi_layer - get the current VSI layer number
1216 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)
1217 return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;
1218 else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS)
1220 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;
1221 return hw->sw_entry_point_layer;
1225 * ice_sched_get_agg_layer - get the current aggregator layer number
1237 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)
1238 return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;
1239 return hw->sw_entry_point_layer;
1243 * ice_rm_dflt_leaf_node - remove the default leaf node in the tree
1253 node = pi->root;
1255 if (!node->num_children)
1257 node = node->children[0];
1259 if (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) {
1260 u32 teid = LE32_TO_CPU(node->info.node_teid);
1264 status = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid);
1271 * ice_sched_rm_dflt_nodes - free the default nodes in the tree
1284 node = pi->root;
1286 if (node->tx_sched_layer >= pi->hw->sw_entry_point_layer &&
1287 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&
1288 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) {
1293 if (!node->num_children)
1295 node = node->children[0];
1300 * ice_sched_init_port - Initialize scheduler by querying information from FW
1318 hw = pi->hw;
1327 status = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN,
1332 /* num_branches should be between 1-8 */
1343 /* num_elems should always be between 1-9 */
1354 if (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type ==
1356 pi->last_node_teid =
1357 LE32_TO_CPU(buf[0].generic[num_elems - 2].node_teid);
1359 pi->last_node_teid =
1360 LE32_TO_CPU(buf[0].generic[num_elems - 1].node_teid);
1376 hw->sw_entry_point_layer = j;
1385 if (pi->root)
1389 pi->port_state = ICE_SCHED_PORT_STATE_READY;
1390 ice_init_lock(&pi->sched_lock);
1392 INIT_LIST_HEAD(&hw->rl_prof_list[i]);
1395 if (status && pi->root) {
1396 ice_free_sched_node(pi, pi->root);
1397 pi->root = NULL;
1405 * ice_sched_get_node - Get the struct ice_sched_node for given TEID
1420 ice_acquire_lock(&pi->sched_lock);
1421 node = ice_sched_find_node_by_teid(pi->root, teid);
1422 ice_release_lock(&pi->sched_lock);
1425 ice_debug(pi->hw, ICE_DBG_SCHED, "Node not found for teid=0x%x\n", teid);
1431 * ice_sched_query_res_alloc - query the FW for num of logical sched layers
1443 if (hw->layer_info)
1455 hw->num_tx_sched_layers =
1456 (u8)LE16_TO_CPU(buf->sched_props.logical_levels);
1457 hw->num_tx_sched_phys_layers =
1458 (u8)LE16_TO_CPU(buf->sched_props.phys_levels);
1459 hw->flattened_layers = buf->sched_props.flattening_bitmap;
1460 hw->max_cgds = buf->sched_props.max_pf_cgds;
1462 /* max sibling group size of current layer refers to the max children
1464 * layer 1 node max children will be layer 2 max sibling group size
1465 * layer 2 node max children will be layer 3 max sibling group size
1469 for (i = 0; i < hw->num_tx_sched_layers - 1; i++) {
1470 max_sibl = buf->layer_props[i + 1].max_sibl_grp_sz;
1471 hw->max_children[i] = LE16_TO_CPU(max_sibl);
1474 hw->layer_info = (struct ice_aqc_layer_props *)
1475 ice_memdup(hw, buf->layer_props,
1476 (hw->num_tx_sched_layers *
1477 sizeof(*hw->layer_info)),
1479 if (!hw->layer_info) {
1490 * ice_sched_get_psm_clk_freq - determine the PSM clock frequency
1505 hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ;
1508 hw->psm_clk_freq = ICE_PSM_CLK_416MHZ_IN_HZ;
1511 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ;
1514 hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ;
1518 * to a 2-bit value from GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M mask.
1526 * ice_sched_find_node_in_subtree - Find node in part of base node subtree
1540 for (i = 0; i < base->num_children; i++) {
1541 struct ice_sched_node *child = base->children[i];
1546 if (child->tx_sched_layer > node->tx_sched_layer)
1559 * ice_sched_get_free_qgrp - Scan all queue group siblings and find a free node
1579 min_children = qgrp_node->num_children;
1585 * equal number of shares and active. The bandwidth will be equally
1590 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))
1591 if (qgrp_node->num_children < min_children &&
1592 qgrp_node->owner == owner) {
1595 min_children = min_qgrp->num_children;
1600 qgrp_node = qgrp_node->sibling;
1606 * ice_sched_get_free_qparent - Get a free LAN or RDMA queue group node
1623 qgrp_layer = ice_sched_get_qgrp_layer(pi->hw);
1624 vsi_layer = ice_sched_get_vsi_layer(pi->hw);
1625 max_children = pi->hw->max_children[qgrp_layer];
1627 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
1630 vsi_node = vsi_ctx->sched.vsi_node[tc];
1641 /* get the first queue group node from VSI sub-tree */
1645 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))
1646 if (qgrp_node->num_children < max_children &&
1647 qgrp_node->owner == owner)
1649 qgrp_node = qgrp_node->sibling;
1657 * ice_sched_get_vsi_node - Get a VSI node based on VSI ID
1672 vsi_layer = ice_sched_get_vsi_layer(pi->hw);
1677 if (node->vsi_handle == vsi_handle)
1679 node = node->sibling;
1686 * ice_sched_get_agg_node - Get an aggregator node based on aggregator ID
1699 struct ice_hw *hw = pi->hw;
1709 if (node->agg_id == agg_id)
1711 node = node->sibling;
1718 * ice_sched_check_node - Compare node parameters between SW DB and HW DB
1730 node_teid = LE32_TO_CPU(node->info.node_teid);
1735 if (memcmp(&buf, &node->info, sizeof(buf))) {
1745 * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes
1763 for (i = qgl; i > vsil; i--) {
1765 num = DIVIDE_AND_ROUND_UP(num, hw->max_children[i]);
1773 * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree
1789 struct ice_hw *hw = pi->hw;
1818 node->owner = owner;
1819 node = node->sibling;
1822 parent = parent->children[0];
1830 * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes
1847 vsil = ice_sched_get_vsi_layer(pi->hw);
1848 for (i = vsil; i >= pi->hw->sw_entry_point_layer; i--)
1852 if (!tc_node->num_children || i == vsil) {
1855 /* If intermediate nodes are reached max children
1861 if (node->num_children <
1862 pi->hw->max_children[i])
1864 node = node->sibling;
1879 * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree
1900 vsil = ice_sched_get_vsi_layer(pi->hw);
1901 for (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) {
1918 parent = parent->children[0];
1924 parent->vsi_handle = vsi_handle;
1931 * ice_sched_add_vsi_to_topo - add a new VSI into tree
1957 * ice_sched_update_vsi_child_nodes - update VSI child nodes
1961 * @new_numqs: new number of max queues
1974 struct ice_hw *hw = pi->hw;
1991 prev_numqs = vsi_ctx->sched.max_lanq[tc];
1993 prev_numqs = vsi_ctx->sched.max_rdmaq[tc];
2009 /* Keep the max number of queue configuration all the time. Update the
2021 vsi_ctx->sched.max_lanq[tc] = new_numqs;
2023 vsi_ctx->sched.max_rdmaq[tc] = new_numqs;
2029 * ice_sched_cfg_vsi - configure the new/existing VSI
2033 * @maxqs: max number of queues
2047 struct ice_hw *hw = pi->hw;
2050 ice_debug(pi->hw, ICE_DBG_SCHED, "add/config VSI %d\n", vsi_handle);
2061 if (vsi_node && vsi_node->in_use) {
2062 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid);
2067 vsi_node->in_use = false;
2082 vsi_ctx->sched.vsi_node[tc] = vsi_node;
2083 vsi_node->in_use = true;
2084 /* invalidate the max queues whenever VSI gets added first time
2088 vsi_ctx->sched.max_lanq[tc] = 0;
2089 vsi_ctx->sched.max_rdmaq[tc] = 0;
2099 if (!vsi_node->in_use) {
2100 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid);
2104 vsi_node->in_use = true;
2111 * ice_sched_rm_agg_vsi_info - remove aggregator related VSI info entry
2123 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &pi->hw->agg_list,
2130 &agg_info->agg_vsi_list,
2132 if (agg_vsi_info->vsi_handle == vsi_handle) {
2133 LIST_DEL(&agg_vsi_info->list_entry);
2134 ice_free(pi->hw, agg_vsi_info);
2141 * ice_sched_is_leaf_node_present - check for a leaf node in the sub-tree
2142 * @node: pointer to the sub-tree node
2144 * This function checks for a leaf node presence in a given sub-tree node.
2150 for (i = 0; i < node->num_children; i++)
2151 if (ice_sched_is_leaf_node_present(node->children[i]))
2154 return (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF);
2158 * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes
2173 ice_debug(pi->hw, ICE_DBG_SCHED, "removing VSI %d\n", vsi_handle);
2174 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
2176 ice_acquire_lock(&pi->sched_lock);
2177 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
2194 ice_debug(pi->hw, ICE_DBG_SCHED, "VSI has leaf nodes in TC %d\n", i);
2198 while (j < vsi_node->num_children) {
2199 if (vsi_node->children[j]->owner == owner) {
2200 ice_free_sched_node(pi, vsi_node->children[j]);
2211 if (!vsi_node->num_children) {
2213 vsi_ctx->sched.vsi_node[i] = NULL;
2219 vsi_ctx->sched.max_lanq[i] = 0;
2221 vsi_ctx->sched.max_rdmaq[i] = 0;
2226 ice_release_lock(&pi->sched_lock);
2231 * ice_rm_vsi_lan_cfg - remove VSI and its LAN children nodes
2244 * ice_rm_vsi_rdma_cfg - remove VSI and its RDMA children nodes
2257 * ice_sched_is_tree_balanced - Check tree nodes are identical or not
2262 * This function needs to be called with the port_info->sched_lock held
2269 for (i = 0; i < node->num_children; i++)
2274 if (!ice_sched_is_tree_balanced(hw, node->children[i]))
2281 * ice_aq_query_node_to_root - retrieve the tree topology for a given node TEID
2301 cmd->teid = CPU_TO_LE32(node_teid);
2306 * ice_get_agg_info - get the aggregator ID
2318 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
2320 if (agg_info->agg_id == agg_id)
2327 * ice_sched_get_free_vsi_parent - Find a free parent node in aggregator subtree
2339 u8 l = node->tx_sched_layer;
2345 if (l == vsil - 1)
2346 return (node->num_children < hw->max_children[l]) ? node : NULL;
2351 if (node->num_children < hw->max_children[l])
2357 for (i = 0; i < node->num_children; i++) {
2360 parent = ice_sched_get_free_vsi_parent(hw, node->children[i],
2370 * ice_sched_update_parent - update the new parent in SW DB
2384 old_parent = node->parent;
2387 for (i = 0; i < old_parent->num_children; i++)
2388 if (old_parent->children[i] == node) {
2389 for (j = i + 1; j < old_parent->num_children; j++)
2390 old_parent->children[j - 1] =
2391 old_parent->children[j];
2392 old_parent->num_children--;
2397 new_parent->children[new_parent->num_children++] = node;
2398 node->parent = new_parent;
2399 node->info.parent_teid = new_parent->info.node_teid;
2403 * ice_sched_move_nodes - move child nodes to a given parent
2422 hw = pi->hw;
2428 if (parent->num_children + num_items >
2429 hw->max_children[parent->tx_sched_layer])
2438 node = ice_sched_find_node_by_teid(pi->root, list[i]);
2444 buf->hdr.src_parent_teid = node->info.parent_teid;
2445 buf->hdr.dest_parent_teid = parent->info.node_teid;
2446 buf->teid[0] = node->info.node_teid;
2447 buf->hdr.num_elems = CPU_TO_LE16(1);
2465 * ice_sched_move_vsi_to_agg - move VSI to aggregator node
2498 if (ice_sched_find_node_in_subtree(pi->hw, agg_node, vsi_node))
2501 aggl = ice_sched_get_agg_layer(pi->hw);
2502 vsil = ice_sched_get_vsi_layer(pi->hw);
2509 for (i = 0; i < agg_node->num_children; i++) {
2510 parent = ice_sched_get_free_vsi_parent(pi->hw,
2511 agg_node->children[i],
2534 parent = parent->children[0];
2541 vsi_teid = LE32_TO_CPU(vsi_node->info.node_teid);
2546 * ice_move_all_vsi_to_dflt_agg - move all VSI(s) to default aggregator
2565 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, tmp, &agg_info->agg_vsi_list,
2567 u16 vsi_handle = agg_vsi_info->vsi_handle;
2570 if (!ice_is_tc_ena(agg_vsi_info->tc_bitmap[0], tc))
2578 ice_clear_bit(tc, agg_vsi_info->tc_bitmap);
2579 if (rm_vsi_info && !agg_vsi_info->tc_bitmap[0]) {
2580 LIST_DEL(&agg_vsi_info->list_entry);
2581 ice_free(pi->hw, agg_vsi_info);
2589 * ice_sched_is_agg_inuse - check whether the aggregator is in use or not
2600 vsil = ice_sched_get_vsi_layer(pi->hw);
2601 if (node->tx_sched_layer < vsil - 1) {
2602 for (i = 0; i < node->num_children; i++)
2603 if (ice_sched_is_agg_inuse(pi, node->children[i]))
2607 return node->num_children ? true : false;
2612 * ice_sched_rm_agg_cfg - remove the aggregator node
2624 struct ice_hw *hw = pi->hw;
2641 while (agg_node->tx_sched_layer > hw->sw_entry_point_layer) {
2642 struct ice_sched_node *parent = agg_node->parent;
2647 if (parent->num_children > 1)
2658 * ice_rm_agg_cfg_tc - remove aggregator configuration for TC
2674 /* If nothing to remove - return success */
2675 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc))
2683 status = ice_sched_rm_agg_cfg(pi, agg_info->agg_id, tc);
2687 ice_clear_bit(tc, agg_info->tc_bitmap);
2693 * ice_save_agg_tc_bitmap - save aggregator TC bitmap
2707 agg_info = ice_get_agg_info(pi->hw, agg_id);
2710 ice_cp_bitmap(agg_info->replay_tc_bitmap, tc_bitmap,
2716 * ice_sched_add_agg_cfg - create an aggregator node
2729 struct ice_hw *hw = pi->hw;
2753 for (i = hw->sw_entry_point_layer; i < aggl; i++) {
2758 if (parent->num_children < hw->max_children[i])
2760 parent = parent->sibling;
2770 for (i = hw->sw_entry_point_layer; i <= aggl; i++) {
2789 parent->agg_id = agg_id;
2791 parent = parent->children[0];
2799 * ice_sched_cfg_agg - configure aggregator node
2819 struct ice_hw *hw = pi->hw;
2831 agg_info->agg_id = agg_id;
2832 agg_info->agg_type = agg_type;
2833 agg_info->tc_bitmap[0] = 0;
2836 INIT_LIST_HEAD(&agg_info->agg_vsi_list);
2839 LIST_ADD(&agg_info->list_entry, &hw->agg_list);
2852 if (ice_is_tc_ena(agg_info->tc_bitmap[0], tc))
2861 ice_set_bit(tc, agg_info->tc_bitmap);
2868 * ice_cfg_agg - config aggregator node
2883 ice_acquire_lock(&pi->sched_lock);
2889 ice_release_lock(&pi->sched_lock);
2894 * ice_get_agg_vsi_info - get the aggregator ID
2906 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list,
2908 if (agg_vsi_info->vsi_handle == vsi_handle)
2915 * ice_get_vsi_agg_info - get the aggregator info of VSI
2928 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
2940 * ice_save_agg_vsi_tc_bitmap - save aggregator VSI TC bitmap
2956 agg_info = ice_get_agg_info(pi->hw, agg_id);
2963 ice_cp_bitmap(agg_vsi_info->replay_tc_bitmap, tc_bitmap,
2969 * ice_sched_assoc_vsi_to_agg - associate/move VSI to new/default aggregator
2985 struct ice_hw *hw = pi->hw;
2989 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3002 &old_agg_info->agg_vsi_list,
3004 if (old_agg_vsi_info->vsi_handle == vsi_handle)
3018 agg_vsi_info->vsi_handle = vsi_handle;
3019 LIST_ADD(&agg_vsi_info->list_entry, &agg_info->agg_vsi_list);
3031 ice_set_bit(tc, agg_vsi_info->tc_bitmap);
3033 ice_clear_bit(tc, old_agg_vsi_info->tc_bitmap);
3035 if (old_agg_vsi_info && !old_agg_vsi_info->tc_bitmap[0]) {
3036 LIST_DEL(&old_agg_vsi_info->list_entry);
3037 ice_free(pi->hw, old_agg_vsi_info);
3043 * ice_sched_rm_unused_rl_prof - remove unused RL profile
3053 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) {
3058 &hw->rl_prof_list[ln],
3067 * ice_sched_update_elem - update element
3073 * parameters of node from argument info data buffer (Info->data buf) and
3088 if (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_TC)
3109 node->info.data = info->data;
3114 * ice_sched_cfg_node_bw_alloc - configure node BW weight/alloc params
3130 buf = node->info;
3133 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR;
3134 data->cir_bw.bw_alloc = CPU_TO_LE16(bw_alloc);
3136 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR;
3137 data->eir_bw.bw_alloc = CPU_TO_LE16(bw_alloc);
3148 * ice_move_vsi_to_agg - moves VSI to new or default aggregator
3163 ice_acquire_lock(&pi->sched_lock);
3169 ice_release_lock(&pi->sched_lock);
3174 * ice_rm_agg_cfg - remove aggregator configuration
3187 ice_acquire_lock(&pi->sched_lock);
3188 agg_info = ice_get_agg_info(pi->hw, agg_id);
3200 if (ice_is_any_bit_set(agg_info->tc_bitmap, ICE_MAX_TRAFFIC_CLASS)) {
3206 LIST_DEL(&agg_info->list_entry);
3207 ice_free(pi->hw, agg_info);
3210 ice_sched_rm_unused_rl_prof(pi->hw);
3213 ice_release_lock(&pi->sched_lock);
3218 * ice_set_clear_cir_bw_alloc - set or clear CIR BW alloc information
3219 * @bw_t_info: bandwidth type information structure
3220 * @bw_alloc: Bandwidth allocation information
3228 bw_t_info->cir_bw.bw_alloc = bw_alloc;
3229 if (bw_t_info->cir_bw.bw_alloc)
3230 ice_set_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap);
3232 ice_clear_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap);
3236 * ice_set_clear_eir_bw_alloc - set or clear EIR BW alloc information
3237 * @bw_t_info: bandwidth type information structure
3238 * @bw_alloc: Bandwidth allocation information
3246 bw_t_info->eir_bw.bw_alloc = bw_alloc;
3247 if (bw_t_info->eir_bw.bw_alloc)
3248 ice_set_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap);
3250 ice_clear_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap);
3254 * ice_sched_save_vsi_bw_alloc - save VSI node's BW alloc information
3258 * @rl_type: rate limit type min or max
3259 * @bw_alloc: Bandwidth allocation information
3269 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3271 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
3276 ice_set_clear_cir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc],
3280 ice_set_clear_eir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc],
3290 * ice_set_clear_cir_bw - set or clear CIR BW
3291 * @bw_t_info: bandwidth type information structure
3292 * @bw: bandwidth in Kbps - Kilo bits per sec
3294 * Save or clear CIR bandwidth (BW) in the passed param bw_t_info.
3299 ice_clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap);
3300 bw_t_info->cir_bw.bw = 0;
3303 ice_set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap);
3304 bw_t_info->cir_bw.bw = bw;
3309 * ice_set_clear_eir_bw - set or clear EIR BW
3310 * @bw_t_info: bandwidth type information structure
3311 * @bw: bandwidth in Kbps - Kilo bits per sec
3313 * Save or clear EIR bandwidth (BW) in the passed param bw_t_info.
3318 ice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);
3319 bw_t_info->eir_bw.bw = 0;
3322 ice_set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap);
3323 bw_t_info->eir_bw.bw = bw;
3328 * ice_set_clear_shared_bw - set or clear shared BW
3329 * @bw_t_info: bandwidth type information structure
3330 * @bw: bandwidth in Kbps - Kilo bits per sec
3332 * Save or clear shared bandwidth (BW) in the passed param bw_t_info.
3337 ice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);
3338 bw_t_info->shared_bw = 0;
3341 ice_set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap);
3342 bw_t_info->shared_bw = bw;
3347 * ice_sched_save_vsi_bw - save VSI node's BW information
3351 * @rl_type: rate limit type min, max, or shared
3352 * @bw: bandwidth in Kbps - Kilo bits per sec
3362 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3364 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
3369 ice_set_clear_cir_bw(&vsi_ctx->sched.bw_t_info[tc], bw);
3372 ice_set_clear_eir_bw(&vsi_ctx->sched.bw_t_info[tc], bw);
3375 ice_set_clear_shared_bw(&vsi_ctx->sched.bw_t_info[tc], bw);
3384 * ice_set_clear_prio - set or clear priority information
3385 * @bw_t_info: bandwidth type information structure
3392 bw_t_info->generic = prio;
3393 if (bw_t_info->generic)
3394 ice_set_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap);
3396 ice_clear_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap);
3400 * ice_sched_save_vsi_prio - save VSI node's priority information
3414 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3416 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
3421 ice_set_clear_prio(&vsi_ctx->sched.bw_t_info[tc], prio);
3426 * ice_sched_save_agg_bw_alloc - save aggregator node's BW alloc information
3430 * @rl_type: rate limit type min or max
3431 * @bw_alloc: bandwidth alloc information
3441 agg_info = ice_get_agg_info(pi->hw, agg_id);
3444 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc))
3448 ice_set_clear_cir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc);
3451 ice_set_clear_eir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc);
3460 * ice_sched_save_agg_bw - save aggregator node's BW information
3464 * @rl_type: rate limit type min, max, or shared
3465 * @bw: bandwidth in Kbps - Kilo bits per sec
3475 agg_info = ice_get_agg_info(pi->hw, agg_id);
3478 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc))
3482 ice_set_clear_cir_bw(&agg_info->bw_t_info[tc], bw);
3485 ice_set_clear_eir_bw(&agg_info->bw_t_info[tc], bw);
3488 ice_set_clear_shared_bw(&agg_info->bw_t_info[tc], bw);
3497 * ice_cfg_vsi_bw_lmt_per_tc - configure VSI BW limit per TC
3501 * @rl_type: min or max
3502 * @bw: bandwidth in Kbps
3517 ice_acquire_lock(&pi->sched_lock);
3519 ice_release_lock(&pi->sched_lock);
3525 * ice_cfg_vsi_bw_dflt_lmt_per_tc - configure default VSI BW limit per TC
3529 * @rl_type: min or max
3545 ice_acquire_lock(&pi->sched_lock);
3548 ice_release_lock(&pi->sched_lock);
3554 * ice_cfg_agg_bw_lmt_per_tc - configure aggregator BW limit per TC
3558 * @rl_type: min or max
3559 * @bw: bandwidth in Kbps
3573 ice_acquire_lock(&pi->sched_lock);
3575 ice_release_lock(&pi->sched_lock);
3581 * ice_cfg_agg_bw_dflt_lmt_per_tc - configure aggregator BW default limit per TC
3585 * @rl_type: min or max
3600 ice_acquire_lock(&pi->sched_lock);
3603 ice_release_lock(&pi->sched_lock);
3609 * ice_cfg_vsi_bw_shared_lmt - configure VSI BW shared limit
3612 * @min_bw: minimum bandwidth in Kbps
3613 * @max_bw: maximum bandwidth in Kbps
3614 * @shared_bw: shared bandwidth in Kbps
3628 * ice_cfg_vsi_bw_no_shared_lmt - configure VSI BW for no shared limiter
3645 * ice_cfg_agg_bw_shared_lmt - configure aggregator BW shared limit
3648 * @min_bw: minimum bandwidth in Kbps
3649 * @max_bw: maximum bandwidth in Kbps
3650 * @shared_bw: shared bandwidth in Kbps
3664 * ice_cfg_agg_bw_no_shared_lmt - configure aggregator BW for no shared limiter
3680 * ice_cfg_agg_bw_shared_lmt_per_tc - config aggregator BW shared limit per tc
3684 * @min_bw: minimum bandwidth in Kbps
3685 * @max_bw: maximum bandwidth in Kbps
3686 * @shared_bw: shared bandwidth in Kbps
3700 * ice_cfg_agg_bw_no_shared_lmt_per_tc - cfg aggregator BW shared limit per tc
3718 * ice_cfg_vsi_q_priority - config VSI queue priority of node
3734 ice_acquire_lock(&pi->sched_lock);
3739 node = ice_sched_find_node_by_teid(pi->root, q_ids[i]);
3740 if (!node || node->info.data.elem_type !=
3751 ice_release_lock(&pi->sched_lock);
3756 * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC
3776 struct ice_hw *hw = pi->hw;
3780 ice_acquire_lock(&pi->sched_lock);
3781 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
3783 if (agg_info->agg_id == agg_id) {
3798 if (num_vsis > hw->max_children[agg_node->tx_sched_layer])
3811 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list,
3813 if (agg_vsi_info->vsi_handle == vsi_handle) {
3839 ice_release_lock(&pi->sched_lock);
3844 * ice_cfg_vsi_bw_alloc - config VSI BW alloc per TC
3861 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3864 ice_acquire_lock(&pi->sched_lock);
3881 status = ice_sched_cfg_node_bw_alloc(pi->hw, vsi_node, rl_type,
3891 ice_release_lock(&pi->sched_lock);
3896 * ice_cfg_agg_bw_alloc - config aggregator BW alloc
3912 struct ice_hw *hw = pi->hw;
3916 ice_acquire_lock(&pi->sched_lock);
3917 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
3919 if (agg_info->agg_id == agg_id) {
3954 ice_release_lock(&pi->sched_lock);
3959 * ice_sched_calc_wakeup - calculate RL profile wakeup parameter
3961 * @bw: bandwidth in Kbps
3973 wakeup_int = DIV_S64(hw->psm_clk_freq, bytes_per_sec);
3982 hw->psm_clk_freq, bytes_per_sec);
3985 wakeup_f = wakeup_a - wakeup_b;
4001 * ice_sched_bw_to_rl_profile - convert BW to profile parameters
4003 * @bw: bandwidth in Kbps
4030 ts_rate = DIV_S64((s64)hw->psm_clk_freq,
4055 profile->rl_multiply = CPU_TO_LE16(mv);
4056 profile->wake_up_calc = CPU_TO_LE16(wm);
4057 profile->rl_encode = CPU_TO_LE16(encode);
4067 * ice_sched_add_rl_profile - add RL profile
4069 * @rl_type: type of rate limit BW - min, max, or shared
4070 * @bw: bandwidth in Kbps - Kilo bits per sec
4089 if (!hw || layer_num >= hw->num_tx_sched_layers)
4105 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],
4107 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==
4108 profile_type && rl_prof_elem->bw == bw)
4119 status = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile);
4123 rl_prof_elem->bw = bw;
4125 rl_prof_elem->profile.level = layer_num + 1;
4126 rl_prof_elem->profile.flags = profile_type;
4127 rl_prof_elem->profile.max_burst_size = CPU_TO_LE16(hw->max_burst_size);
4130 buf = &rl_prof_elem->profile;
4136 /* Good entry - add in the list */
4137 rl_prof_elem->prof_id_ref = 0;
4138 LIST_ADD(&rl_prof_elem->list_entry, &hw->rl_prof_list[layer_num]);
4147 * ice_sched_cfg_node_bw_lmt - configure node sched params
4162 buf = node->info;
4166 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR;
4167 data->cir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id);
4170 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR;
4171 data->eir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id);
4174 data->valid_sections |= ICE_AQC_ELEM_VALID_SHARED;
4175 data->srl_id = CPU_TO_LE16(rl_prof_id);
4187 * ice_sched_get_node_rl_prof_id - get node's rate limit profile ID
4201 data = &node->info.data;
4204 if (data->valid_sections & ICE_AQC_ELEM_VALID_CIR)
4205 rl_prof_id = LE16_TO_CPU(data->cir_bw.bw_profile_idx);
4208 if (data->valid_sections & ICE_AQC_ELEM_VALID_EIR)
4209 rl_prof_id = LE16_TO_CPU(data->eir_bw.bw_profile_idx);
4212 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED)
4213 rl_prof_id = LE16_TO_CPU(data->srl_id);
4223 * ice_sched_get_rl_prof_layer - selects rate limit profile creation layer
4225 * @rl_type: type of rate limit BW - min, max, or shared
4234 struct ice_hw *hw = pi->hw;
4236 if (layer_index >= hw->num_tx_sched_layers)
4240 if (hw->layer_info[layer_index].max_cir_rl_profiles)
4244 if (hw->layer_info[layer_index].max_eir_rl_profiles)
4251 if (hw->layer_info[layer_index].max_srl_profiles)
4253 else if (layer_index < hw->num_tx_sched_layers - 1 &&
4254 hw->layer_info[layer_index + 1].max_srl_profiles)
4257 hw->layer_info[layer_index - 1].max_srl_profiles)
4258 return layer_index - 1;
4267 * ice_sched_get_srl_node - get shared rate limit node
4277 if (srl_layer > node->tx_sched_layer)
4278 return node->children[0];
4279 else if (srl_layer < node->tx_sched_layer)
4283 return node->parent;
4289 * ice_sched_rm_rl_profile - remove RL profile ID
4306 if (!hw || layer_num >= hw->num_tx_sched_layers)
4309 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],
4311 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==
4313 LE16_TO_CPU(rl_prof_elem->profile.profile_id) ==
4315 if (rl_prof_elem->prof_id_ref)
4316 rl_prof_elem->prof_id_ref--;
4330 * ice_sched_set_node_bw_dflt - set node's bandwidth limit to default
4333 * @rl_type: rate limit type min, max, or shared
4351 hw = pi->hw;
4385 * ice_sched_set_node_bw - set node's bandwidth
4388 * @rl_type: rate limit type min, max, or shared
4389 * @bw: bandwidth in Kbps - Kilo bits per sec
4401 struct ice_hw *hw = pi->hw;
4409 rl_prof_id = LE16_TO_CPU(rl_prof_info->profile.profile_id);
4420 rl_prof_info->prof_id_ref++;
4428 rl_prof_info->profile.flags &
4433 * ice_sched_set_node_priority - set node's priority
4436 * @priority: number 0-7 representing priority among siblings
4447 buf = node->info;
4450 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;
4451 data->generic |= ICE_AQC_ELEM_GENERIC_PRIO_M &
4454 return ice_sched_update_elem(pi->hw, node, &buf);
4458 * ice_sched_set_node_weight - set node's weight
4461 * @weight: number 1-200 representing weight for WFQ
4471 buf = node->info;
4474 data->valid_sections = ICE_AQC_ELEM_VALID_CIR | ICE_AQC_ELEM_VALID_EIR |
4476 data->cir_bw.bw_alloc = CPU_TO_LE16(weight);
4477 data->eir_bw.bw_alloc = CPU_TO_LE16(weight);
4478 data->generic |= ICE_AQC_ELEM_GENERIC_SP_M &
4481 return ice_sched_update_elem(pi->hw, node, &buf);
4485 * ice_sched_set_node_bw_lmt - set node's BW limit
4488 * @rl_type: rate limit type min, max, or shared
4489 * @bw: bandwidth in Kbps - Kilo bits per sec
4506 hw = pi->hw;
4511 node->tx_sched_layer);
4512 if (layer_num >= hw->num_tx_sched_layers)
4521 * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default
4524 * @rl_type: rate limit type min, max, or shared
4540 * ice_sched_validate_srl_node - Check node for SRL applicability
4556 if (sel_layer == node->tx_sched_layer ||
4557 ((sel_layer == node->tx_sched_layer + 1) &&
4558 node->num_children == 1) ||
4559 ((sel_layer == node->tx_sched_layer - 1) &&
4560 (node->parent && node->parent->num_children == 1)))
4567 * ice_sched_save_q_bw - save queue node's BW information
4569 * @rl_type: rate limit type min, max, or shared
4570 * @bw: bandwidth in Kbps - Kilo bits per sec
4579 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw);
4582 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw);
4585 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw);
4594 * ice_sched_set_q_bw_lmt - sets queue BW limit
4599 * @rl_type: min, max, or shared
4600 * @bw: bandwidth in Kbps
4612 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4614 ice_acquire_lock(&pi->sched_lock);
4615 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle);
4618 node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid);
4620 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n");
4625 if (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF)
4628 /* SRL bandwidth layer selection */
4633 node->tx_sched_layer);
4634 if (sel_layer >= pi->hw->num_tx_sched_layers) {
4652 ice_release_lock(&pi->sched_lock);
4657 * ice_cfg_q_bw_lmt - configure queue BW limit
4662 * @rl_type: min, max, or shared
4663 * @bw: bandwidth in Kbps
4676 * ice_cfg_q_bw_dflt_lmt - configure queue BW default limit
4681 * @rl_type: min, max, or shared
4694 * ice_sched_save_tc_node_bw - save TC node BW limit
4697 * @rl_type: min or max
4698 * @bw: bandwidth in Kbps
4700 * This function saves the modified values of bandwidth settings for later
4711 ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw);
4714 ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw);
4717 ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw);
4729 * ice_sched_set_tc_node_bw_lmt - sets TC node BW limit
4732 * @rl_type: min or max
4733 * @bw: bandwidth in Kbps
4735 * This function configures bandwidth limit of TC node.
4748 ice_acquire_lock(&pi->sched_lock);
4754 buf = tc_node->info;
4756 data->valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
4757 data->generic = (tc << ICE_SCHED_GENERIC_PRIO_S) |
4759 status = ice_sched_update_elem(pi->hw, tc_node, &buf);
4771 ice_release_lock(&pi->sched_lock);
4776 * ice_cfg_tc_node_bw_lmt - configure TC node BW limit
4779 * @rl_type: min or max
4780 * @bw: bandwidth in Kbps
4793 * ice_cfg_tc_node_bw_dflt_lmt - configure TC node BW default limit
4796 * @rl_type: min or max
4808 * ice_sched_save_tc_node_bw_alloc - save TC node's BW alloc information
4811 * @rl_type: rate limit type min or max
4812 * @bw_alloc: Bandwidth allocation information
4824 ice_set_clear_cir_bw_alloc(&pi->tc_node_bw_t_info[tc],
4828 ice_set_clear_eir_bw_alloc(&pi->tc_node_bw_t_info[tc],
4838 * ice_sched_set_tc_node_bw_alloc - set TC node BW alloc
4841 * @rl_type: min or max
4842 * @bw_alloc: bandwidth alloc
4844 * This function configures bandwidth alloc of TC node, also saves the
4846 * in modifying bandwidth alloc setting.
4857 ice_acquire_lock(&pi->sched_lock);
4861 status = ice_sched_cfg_node_bw_alloc(pi->hw, tc_node, rl_type,
4868 ice_release_lock(&pi->sched_lock);
4873 * ice_cfg_tc_node_bw_alloc - configure TC node BW alloc
4876 * @rl_type: min or max
4877 * @bw_alloc: bandwidth alloc
4890 * ice_sched_set_agg_bw_dflt_lmt - set aggregator node's BW limit to default
4905 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4907 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
4914 node = vsi_ctx->sched.ag_node[tc];
4923 /* Set max profile to default */
4939 * ice_sched_get_node_by_id_type - get node from ID type
4960 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4963 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
4966 node = vsi_ctx->sched.vsi_node[tc];
4981 node = ice_sched_find_node_by_teid(pi->root, id);
4988 child_node = ice_sched_find_node_by_teid(pi->root, id);
4991 node = child_node->parent;
5003 * ice_sched_set_node_bw_lmt_per_tc - set node BW limit per TC
5008 * @rl_type: min or max
5009 * @bw: bandwidth in Kbps
5028 ice_acquire_lock(&pi->sched_lock);
5031 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong id, agg type, or tc\n");
5040 ice_release_lock(&pi->sched_lock);
5045 * ice_sched_validate_vsi_srl_node - validate VSI SRL node
5059 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5076 /* SRL bandwidth layer selection */
5078 u8 node_layer = vsi_node->tx_sched_layer;
5083 if (layer_num >= pi->hw->num_tx_sched_layers)
5096 * ice_sched_set_save_vsi_srl_node_bw - set VSI shared limit values
5102 * @bw: minimum, maximum, or shared bandwidth in Kbps
5127 * ice_sched_set_vsi_node_srl_per_tc - set VSI node BW shared limit for tc
5131 * @min_bw: minimum bandwidth in Kbps
5132 * @max_bw: maximum bandwidth in Kbps
5133 * @shared_bw: shared bandwidth in Kbps
5157 vsi_node->tx_sched_layer);
5158 if (layer_num >= pi->hw->num_tx_sched_layers)
5183 * ice_sched_set_vsi_bw_shared_lmt - set VSI BW shared limit
5186 * @min_bw: minimum bandwidth in Kbps
5187 * @max_bw: maximum bandwidth in Kbps
5188 * @shared_bw: shared bandwidth in Kbps
5204 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5207 ice_acquire_lock(&pi->sched_lock);
5231 ice_release_lock(&pi->sched_lock);
5236 * ice_sched_validate_agg_srl_node - validate AGG SRL node
5253 LIST_FOR_EACH_ENTRY(agg_info, &pi->hw->agg_list, ice_sched_agg_info,
5255 if (agg_info->agg_id == agg_id) {
5273 /* SRL bandwidth layer selection */
5275 u8 node_layer = agg_node->tx_sched_layer;
5280 if (layer_num >= pi->hw->num_tx_sched_layers)
5293 * ice_sched_validate_agg_id - Validate aggregator id
5311 LIST_FOR_EACH_ENTRY_SAFE(agg_info, tmp, &pi->hw->agg_list,
5313 if (agg_info->agg_id == agg_id) {
5325 * ice_sched_set_save_agg_srl_node_bw - set aggregator shared limit values
5331 * @bw: minimum, maximum, or shared bandwidth in Kbps
5356 * ice_sched_set_agg_node_srl_per_tc - set aggregator SRL per tc
5360 * @min_bw: minimum bandwidth in Kbps
5361 * @max_bw: maximum bandwidth in Kbps
5362 * @shared_bw: shared bandwidth in Kbps
5387 agg_node->tx_sched_layer);
5388 if (layer_num >= pi->hw->num_tx_sched_layers)
5412 * ice_sched_set_agg_bw_shared_lmt - set aggregator BW shared limit
5415 * @min_bw: minimum bandwidth in Kbps
5416 * @max_bw: maximum bandwidth in Kbps
5417 * @shared_bw: shared bandwidth in Kbps
5434 ice_acquire_lock(&pi->sched_lock);
5459 ice_release_lock(&pi->sched_lock);
5464 * ice_sched_set_agg_bw_shared_lmt_per_tc - set aggregator BW shared lmt per tc
5468 * @min_bw: minimum bandwidth in Kbps
5469 * @max_bw: maximum bandwidth in Kbps
5470 * @shared_bw: shared bandwidth in Kbps
5485 ice_acquire_lock(&pi->sched_lock);
5494 ice_release_lock(&pi->sched_lock);
5499 * ice_sched_cfg_sibl_node_prio - configure node sibling priority
5513 struct ice_hw *hw = pi->hw;
5518 buf = node->info;
5520 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;
5523 data->generic &= ~ICE_AQC_ELEM_GENERIC_PRIO_M;
5524 data->generic |= priority;
5532 * ice_cfg_rl_burst_size - Set burst size value
5568 hw->max_burst_size = burst_size_to_prog;
5573 * ice_sched_replay_node_prio - re-configure node priority
5589 buf = node->info;
5591 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;
5592 data->generic = priority;
5600 * ice_sched_replay_node_bw - replay node(s) BW
5612 struct ice_port_info *pi = hw->port_info;
5618 if (!ice_is_any_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT))
5620 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_PRIO)) {
5622 bw_t_info->generic);
5626 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR)) {
5628 bw_t_info->cir_bw.bw);
5632 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR_WT)) {
5633 bw_alloc = bw_t_info->cir_bw.bw_alloc;
5639 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR)) {
5641 bw_t_info->eir_bw.bw);
5645 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR_WT)) {
5646 bw_alloc = bw_t_info->eir_bw.bw_alloc;
5652 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_SHARED))
5654 bw_t_info->shared_bw);
5659 * ice_sched_replay_agg_bw - replay aggregator node(s) BW
5663 * This function re-creates aggregator type nodes. The caller needs to hold
5676 if (!ice_is_any_bit_set(agg_info->bw_t_info[tc].bw_t_bitmap,
5679 tc_node = ice_sched_get_tc_node(hw->port_info, tc);
5684 agg_node = ice_sched_get_agg_node(hw->port_info, tc_node,
5685 agg_info->agg_id);
5691 &agg_info->bw_t_info[tc]);
5699 * ice_sched_get_ena_tc_bitmap - get enabled TC bitmap
5722 * ice_sched_replay_agg - recreate aggregator node(s)
5731 struct ice_port_info *pi = hw->port_info;
5734 ice_acquire_lock(&pi->sched_lock);
5735 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
5737 /* replay aggregator (re-create aggregator node) */
5738 if (!ice_cmp_bitmap(agg_info->tc_bitmap,
5739 agg_info->replay_tc_bitmap,
5747 agg_info->replay_tc_bitmap,
5749 status = ice_sched_cfg_agg(hw->port_info,
5750 agg_info->agg_id,
5755 agg_info->agg_id);
5763 agg_info->agg_id);
5765 ice_release_lock(&pi->sched_lock);
5769 * ice_sched_replay_agg_vsi_preinit - Agg/VSI replay pre initialization
5777 struct ice_port_info *pi = hw->port_info;
5780 ice_acquire_lock(&pi->sched_lock);
5781 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info,
5785 agg_info->tc_bitmap[0] = 0;
5786 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list,
5788 agg_vsi_info->tc_bitmap[0] = 0;
5790 ice_release_lock(&pi->sched_lock);
5794 * ice_sched_replay_root_node_bw - replay root node BW
5803 if (!pi->hw)
5805 ice_acquire_lock(&pi->sched_lock);
5807 status = ice_sched_replay_node_bw(pi->hw, pi->root,
5808 &pi->root_node_bw_t_info);
5809 ice_release_lock(&pi->sched_lock);
5814 * ice_sched_replay_tc_node_bw - replay TC node(s) BW
5824 if (!pi->hw)
5826 ice_acquire_lock(&pi->sched_lock);
5833 status = ice_sched_replay_node_bw(pi->hw, tc_node,
5834 &pi->tc_node_bw_t_info[tc]);
5838 ice_release_lock(&pi->sched_lock);
5843 * ice_sched_replay_vsi_bw - replay VSI type node(s) BW
5848 * This function replays VSI type nodes bandwidth. This function needs to be
5856 struct ice_port_info *pi = hw->port_info;
5862 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
5874 bw_t_info = &vsi_ctx->sched.bw_t_info[tc];
5883 * ice_sched_replay_vsi_agg - replay aggregator & VSI to aggregator node(s)
5888 * their node bandwidth information. This function needs to be called with
5896 struct ice_port_info *pi = hw->port_info;
5905 return 0; /* Not present in list - default Agg case */
5908 return 0; /* Not present in list - default Agg case */
5909 ice_sched_get_ena_tc_bitmap(pi, agg_info->replay_tc_bitmap,
5912 status = ice_sched_cfg_agg(hw->port_info, agg_info->agg_id,
5922 ice_sched_get_ena_tc_bitmap(pi, agg_vsi_info->replay_tc_bitmap,
5925 status = ice_sched_assoc_vsi_to_agg(pi, agg_info->agg_id, vsi_handle,
5931 agg_vsi_info->tc_bitmap);
5935 * ice_replay_vsi_agg - replay VSI to aggregator node
5940 * node bandwidth information.
5944 struct ice_port_info *pi = hw->port_info;
5947 ice_acquire_lock(&pi->sched_lock);
5949 ice_release_lock(&pi->sched_lock);
5954 * ice_sched_replay_q_bw - replay queue type node BW
5958 * This function replays queue type node bandwidth. This function needs to be
5967 q_node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid);
5970 return ice_sched_replay_node_bw(pi->hw, q_node, &q_ctx->bw_t_info);