Lines Matching +full:no +full:- +full:hw +full:- +full:checksum
1 /* SPDX-License-Identifier: BSD-3-Clause */
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
38 * @hw: pointer to the HW struct
50 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
57 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
67 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
71 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
72 cmd->module_typeid = CPU_TO_LE16(module_typeid);
73 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
74 cmd->offset_high = (offset >> 16) & 0xFF;
75 cmd->length = CPU_TO_LE16(length);
77 return ice_aq_send_cmd(hw, &desc, data, length, cd);
81 * ice_read_flat_nvm - Read portion of NVM by flat offset
82 * @hw: pointer to the HW struct
89 * breaks read requests across Shadow RAM sectors and ensures that no single
96 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
104 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
109 if (read_shadow_ram && ((offset + inlen) > (hw->flash.sr_words * 2u))) {
110 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n");
123 read_size = MIN_T(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
124 inlen - bytes_read);
132 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
149 * @hw: pointer to the HW struct
161 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
168 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
178 cmd->cmd_flags |= command_flags;
182 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
183 cmd->module_typeid = CPU_TO_LE16(module_typeid);
184 cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
185 cmd->offset_high = (offset >> 16) & 0xFF;
186 cmd->length = CPU_TO_LE16(length);
190 return ice_aq_send_cmd(hw, &desc, data, length, cd);
195 * @hw: pointer to the HW struct
201 int ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
208 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
213 status = ice_aq_read_nvm(hw, 0, 2 * module_typeid + 2, 2, &len, true,
222 cmd->module_typeid = CPU_TO_LE16(module_typeid);
223 cmd->length = len;
224 cmd->offset_low = 0;
225 cmd->offset_high = 0;
227 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
231 * ice_aq_read_nvm_cfg - read an NVM config block
232 * @hw: pointer to the HW struct
243 ice_aq_read_nvm_cfg(struct ice_hw *hw, u8 cmd_flags, u16 field_id, void *data,
250 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
256 cmd->cmd_flags = cmd_flags;
257 cmd->id = CPU_TO_LE16(field_id);
259 status = ice_aq_send_cmd(hw, &desc, data, buf_size, cd);
261 *elem_count = LE16_TO_CPU(cmd->count);
267 * ice_aq_write_nvm_cfg - write an NVM config block
268 * @hw: pointer to the HW struct
278 ice_aq_write_nvm_cfg(struct ice_hw *hw, u8 cmd_flags, void *data, u16 buf_size,
284 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
291 cmd->count = CPU_TO_LE16(elem_count);
292 cmd->cmd_flags = cmd_flags;
294 return ice_aq_send_cmd(hw, &desc, data, buf_size, cd);
298 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations
299 * @hw: pointer to the HW structure
304 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
306 if ((offset + words) > hw->flash.sr_words) {
307 ice_debug(hw, ICE_DBG_NVM, "NVM error: offset beyond SR lmt.\n");
313 ice_debug(hw, ICE_DBG_NVM, "NVM error: tried to access %d words, limit is %d.\n",
318 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
321 ice_debug(hw, ICE_DBG_NVM, "NVM error: cannot spread over two sectors.\n");
329 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
330 * @hw: pointer to the HW structure
331 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
336 int ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
342 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
348 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
358 * ice_write_sr_aq - Writes Shadow RAM
359 * @hw: pointer to the HW structure
368 ice_write_sr_aq(struct ice_hw *hw, u32 offset, u16 words, __le16 *data,
373 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
375 status = ice_check_sr_access_params(hw, offset, words);
377 status = ice_aq_update_nvm(hw, 0, 2 * offset, 2 * words, data,
384 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
385 * @hw: pointer to the HW structure
386 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
394 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
399 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
404 status = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);
417 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
418 * @hw: pointer to the HW structure
423 int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
425 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
426 if (hw->flash.blank_nvm_mode)
429 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
433 * ice_release_nvm - Generic request for releasing the NVM ownership
434 * @hw: pointer to the HW structure
438 void ice_release_nvm(struct ice_hw *hw)
440 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
442 if (hw->flash.blank_nvm_mode)
445 ice_release_res(hw, ICE_NVM_RES_ID);
449 * ice_get_flash_bank_offset - Get offset into requested flash bank
450 * @hw: pointer to the HW structure
460 static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
462 struct ice_bank_info *banks = &hw->flash.banks;
469 offset = banks->nvm_ptr;
470 size = banks->nvm_size;
471 active_bank = banks->nvm_bank;
474 offset = banks->orom_ptr;
475 size = banks->orom_size;
476 active_bank = banks->orom_bank;
479 offset = banks->netlist_ptr;
480 size = banks->netlist_size;
481 active_bank = banks->netlist_bank;
484 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
496 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
512 ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
517 * ice_read_flash_module - Read a word from one of the main NVM modules
518 * @hw: pointer to the HW structure
530 * hw->flash.banks data being setup by ice_determine_active_flash_banks()
534 ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
540 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
542 start = ice_get_flash_bank_offset(hw, bank, module);
544 ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
549 status = ice_acquire_nvm(hw, ICE_RES_READ);
553 status = ice_read_flat_nvm(hw, start + offset, &length, data, false);
555 ice_release_nvm(hw);
561 * ice_read_nvm_module - Read from the active main NVM module
562 * @hw: pointer to the HW structure
571 ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
576 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_NVM_BANK_PTR, offset * sizeof(u16),
585 * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header
586 * @hw: pointer to the HW struct
594 ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,
601 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,
606 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,
621 * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
622 * @hw: pointer to the HW structure
631 ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
636 status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
642 return ice_read_nvm_module(hw, bank, hdr_len + offset, data);
646 * ice_read_orom_module - Read from the active Option ROM module
647 * @hw: pointer to the HW structure
657 ice_read_orom_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
662 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, offset * sizeof(u16),
671 * ice_read_netlist_module - Read data from the netlist module area
672 * @hw: pointer to the HW structure
680 ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
685 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR, offset * sizeof(u16),
694 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
695 * @hw: pointer to the HW structure
696 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
701 int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
705 status = ice_acquire_nvm(hw, ICE_RES_READ);
707 status = ice_read_sr_word_aq(hw, offset, data);
708 ice_release_nvm(hw);
717 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
718 * @hw: pointer to hardware structure
728 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
734 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
736 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
739 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
741 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
745 if (check_add_overflow(pfa_ptr, (u16)(pfa_len - 1), &max_tlv)) {
746 ice_debug(hw, ICE_DBG_INIT, "PFA starts at offset %u. PFA length of %u caused 16-bit arithmetic overflow.\n",
765 status = ice_read_sr_word(hw, (u16)next_tlv,
768 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
772 status = ice_read_sr_word(hw, (u16)(next_tlv + 1), &tlv_len);
774 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
788 ice_debug(hw, ICE_DBG_INIT, "TLV of type %u and length 0x%04x caused 16-bit arithmetic overflow. The PFA starts at 0x%04x and has length of 0x%04x\n",
798 * ice_read_pba_string - Reads part number string from NVM
799 * @hw: pointer to hardware structure
805 int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
812 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
815 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
820 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
822 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
827 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
834 pba_size--;
836 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
841 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
843 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
856 * ice_get_nvm_srev - Read the security revision from the NVM CSS header
857 * @hw: pointer to the HW struct
864 static int ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
869 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_L, &srev_l);
873 status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_SREV_H, &srev_h);
883 * ice_get_nvm_ver_info - Read NVM version information
884 * @hw: pointer to the HW struct
892 ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
897 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
899 ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
903 nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
904 nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
906 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
908 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
911 status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
913 ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
917 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
919 status = ice_get_nvm_srev(hw, bank, &nvm->srev);
921 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
927 * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
928 * @hw: pointer to the HW structure
935 int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
937 return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
941 * ice_get_orom_srev - Read the security revision from the OROM CSS header
942 * @hw: pointer to the HW struct
949 static int ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)
951 u32 orom_size_word = hw->flash.banks.orom_size / 2;
957 status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
962 ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
963 hw->flash.banks.orom_size);
970 css_start = orom_size_word - hdr_len;
971 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
975 status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
985 * ice_get_orom_civd_data - Get the combo version information from Option ROM
986 * @hw: pointer to the HW struct
994 ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank,
1014 for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) {
1017 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR,
1020 ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n");
1028 ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n",
1031 status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR,
1035 ice_debug(hw, ICE_DBG_NVM, "Unable to read CIVD data\n");
1039 /* Verify that the simple checksum is zero */
1044 ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n",
1056 ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n");
1063 * ice_get_orom_ver_info - Read Option ROM version information
1064 * @hw: pointer to the HW struct
1072 ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom)
1078 status = ice_get_orom_civd_data(hw, bank, &civd);
1080 ice_debug(hw, ICE_DBG_NVM, "Failed to locate valid Option ROM CIVD data\n");
1086 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >> ICE_OROM_VER_SHIFT);
1087 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
1088 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >> ICE_OROM_VER_BUILD_SHIFT);
1090 status = ice_get_orom_srev(hw, bank, &orom->srev);
1092 ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
1100 * ice_get_inactive_orom_ver - Read Option ROM version from the inactive bank
1101 * @hw: pointer to the HW structure
1108 int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom)
1110 return ice_get_orom_ver_info(hw, ICE_INACTIVE_FLASH_BANK, orom);
1115 * @hw: pointer to the HW struct
1124 ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank,
1131 status = ice_read_netlist_module(hw, bank, ICE_NETLIST_TYPE_OFFSET, &module_id);
1136 ice_debug(hw, ICE_DBG_NVM, "Expected netlist module_id ID of 0x%04x, but got 0x%04x\n",
1141 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_MODULE_LEN, &length);
1147 ice_debug(hw, ICE_DBG_NVM, "Netlist Link Topology module too small. Expected at least %u words, but got %u words.\n",
1152 status = ice_read_netlist_module(hw, bank, ICE_LINK_TOPO_NODE_COUNT, &node_count);
1157 id_blk = (u16 *)ice_calloc(hw, ICE_NETLIST_ID_BLK_SIZE, sizeof(*id_blk));
1162 status = ice_read_flash_module(hw, bank, ICE_SR_NETLIST_BANK_PTR,
1171 netlist->major = id_blk[ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16 |
1173 netlist->minor = id_blk[ICE_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16 |
1175 netlist->type = id_blk[ICE_NETLIST_ID_BLK_TYPE_HIGH] << 16 |
1177 netlist->rev = id_blk[ICE_NETLIST_ID_BLK_REV_HIGH] << 16 |
1179 netlist->cust_ver = id_blk[ICE_NETLIST_ID_BLK_CUST_VER];
1181 netlist->hash = id_blk[ICE_NETLIST_ID_BLK_SHA_HASH_WORD(15)] << 16 |
1185 ice_free(hw, id_blk);
1192 * @hw: pointer to the HW struct
1197 int ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *netlist)
1199 return ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, netlist);
1204 * @hw: pointer to the HW struct
1211 int ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist)
1213 return ice_get_netlist_info(hw, ICE_INACTIVE_FLASH_BANK, netlist);
1217 * ice_discover_flash_size - Discover the available flash size
1218 * @hw: pointer to the HW struct
1224 static int ice_discover_flash_size(struct ice_hw *hw)
1229 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1231 status = ice_acquire_nvm(hw, ICE_RES_READ);
1235 while ((max_size - min_size) > 1) {
1240 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
1242 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
1243 ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",
1248 ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",
1257 ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);
1259 hw->flash.flash_size = max_size;
1262 ice_release_nvm(hw);
1268 * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
1269 * @hw: pointer to the HW structure
1281 static int ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
1286 status = ice_read_sr_word(hw, offset, &value);
1300 * ice_read_sr_area_size - Read an area size from a Shadow RAM word
1301 * @hw: pointer to the HW structure
1312 static int ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
1317 status = ice_read_sr_word(hw, offset, &value);
1328 * ice_determine_active_flash_banks - Discover active bank for each module
1329 * @hw: pointer to the HW struct
1337 static int ice_determine_active_flash_banks(struct ice_hw *hw)
1339 struct ice_bank_info *banks = &hw->flash.banks;
1343 status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
1345 ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
1351 ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
1356 banks->nvm_bank = ICE_1ST_FLASH_BANK;
1358 banks->nvm_bank = ICE_2ND_FLASH_BANK;
1361 banks->orom_bank = ICE_1ST_FLASH_BANK;
1363 banks->orom_bank = ICE_2ND_FLASH_BANK;
1366 banks->netlist_bank = ICE_1ST_FLASH_BANK;
1368 banks->netlist_bank = ICE_2ND_FLASH_BANK;
1370 status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
1372 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
1376 status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
1378 ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
1382 status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
1384 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
1388 status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
1390 ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
1394 status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
1396 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
1400 status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
1402 ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
1410 * ice_init_nvm - initializes NVM setting
1411 * @hw: pointer to the HW struct
1416 int ice_init_nvm(struct ice_hw *hw)
1418 struct ice_flash_info *flash = &hw->flash;
1423 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1428 gens_stat = rd32(hw, GLNVM_GENS);
1432 flash->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
1435 fla = rd32(hw, GLNVM_FLA);
1437 flash->blank_nvm_mode = false;
1440 flash->blank_nvm_mode = true;
1441 ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");
1445 status = ice_discover_flash_size(hw);
1447 ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");
1451 status = ice_determine_active_flash_banks(hw);
1453 ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
1457 status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
1459 ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
1463 status = ice_get_orom_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->orom);
1465 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
1468 status = ice_get_netlist_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->netlist);
1470 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
1476 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
1477 * @hw: pointer to the HW structure
1478 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
1487 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
1491 status = ice_acquire_nvm(hw, ICE_RES_READ);
1493 status = ice_read_sr_buf_aq(hw, offset, words, data);
1494 ice_release_nvm(hw);
1501 * __ice_write_sr_word - Writes Shadow RAM word
1502 * @hw: pointer to the HW structure
1508 * reception) by caller. To commit SR to NVM update checksum function
1512 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data)
1516 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1519 return ice_write_sr_aq(hw, offset, 1, &data_local, false);
1523 * __ice_write_sr_buf - Writes Shadow RAM buf
1524 * @hw: pointer to the HW structure
1532 * checksum function should be called.
1535 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data)
1542 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1544 vmem = ice_calloc(hw, words, sizeof(u16));
1555 status = ice_write_sr_aq(hw, offset, words, data_local, false);
1557 ice_free(hw, vmem);
1563 * ice_calc_sr_checksum - Calculates and returns Shadow RAM SW checksum
1564 * @hw: pointer to hardware structure
1565 * @checksum: pointer to the checksum
1567 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
1568 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
1572 static int ice_calc_sr_checksum(struct ice_hw *hw, u16 *checksum)
1582 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1584 vmem = ice_calloc(hw, ICE_SR_SECTOR_SIZE_IN_WORDS, sizeof(u16));
1590 status = ice_read_sr_word_aq(hw, ICE_SR_VPD_PTR, &vpd_module);
1594 /* read pointer to PCIe Alt Auto-load module */
1595 status = ice_read_sr_word_aq(hw, ICE_SR_PCIE_ALT_AUTO_LOAD_PTR,
1600 /* Calculate SW checksum that covers the whole 64kB shadow RAM
1601 * except the VPD and PCIe ALT Auto-load modules
1603 for (i = 0; i < hw->flash.sr_words; i++) {
1608 status = ice_read_sr_buf_aq(hw, i, &words, data);
1613 /* Skip Checksum word */
1628 *checksum = (u16)ICE_SR_SW_CHECKSUM_BASE - checksum_local;
1631 ice_free(hw, vmem);
1636 * ice_update_sr_checksum - Updates the Shadow RAM SW checksum
1637 * @hw: pointer to hardware structure
1643 int ice_update_sr_checksum(struct ice_hw *hw)
1646 u16 checksum;
1649 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1651 status = ice_calc_sr_checksum(hw, &checksum);
1653 le_sum = CPU_TO_LE16(checksum);
1654 status = ice_write_sr_aq(hw, ICE_SR_SW_CHECKSUM_WORD, 1,
1661 * ice_validate_sr_checksum - Validate Shadow RAM SW checksum
1662 * @hw: pointer to hardware structure
1663 * @checksum: calculated checksum
1665 * Performs checksum calculation and validates the Shadow RAM SW checksum.
1666 * If the caller does not need checksum, the value can be NULL.
1668 int ice_validate_sr_checksum(struct ice_hw *hw, u16 *checksum)
1674 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1676 status = ice_acquire_nvm(hw, ICE_RES_READ);
1678 status = ice_calc_sr_checksum(hw, &checksum_local);
1679 ice_release_nvm(hw);
1686 ice_read_sr_word(hw, ICE_SR_SW_CHECKSUM_WORD, &checksum_sr);
1688 /* Verify read checksum from EEPROM is the same as
1689 * calculated checksum
1694 /* If the user cares, return the calculated checksum */
1695 if (checksum)
1696 *checksum = checksum_local;
1703 * @hw: pointer to the HW struct
1705 * Verify NVM PFA checksum validity (0x0706)
1707 int ice_nvm_validate_checksum(struct ice_hw *hw)
1713 status = ice_acquire_nvm(hw, ICE_RES_READ);
1720 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
1722 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1723 ice_release_nvm(hw);
1726 if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
1734 * @hw: pointer to the HW struct
1736 * Recalculate NVM PFA checksum (0x0706)
1738 int ice_nvm_recalculate_checksum(struct ice_hw *hw)
1744 status = ice_acquire_nvm(hw, ICE_RES_READ);
1751 cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC;
1753 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1755 ice_release_nvm(hw);
1762 * @hw: pointer to the HW struct
1780 int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags)
1789 cmd->cmd_flags = (u8)(cmd_flags & 0xFF);
1790 cmd->offset_high = (u8)((cmd_flags >> 8) & 0xFF);
1792 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1794 *response_flags = cmd->cmd_flags;
1800 * ice_get_nvm_minsrevs - Get the Minimum Security Revision values from flash
1801 * @hw: pointer to the HW struct
1808 ice_get_nvm_minsrevs(struct ice_hw *hw, struct ice_minsrev_info *minsrevs)
1814 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1816 status = ice_acquire_nvm(hw, ICE_RES_READ);
1820 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_MINSREV_MOD_ID, 0, sizeof(data),
1823 ice_release_nvm(hw);
1837 minsrevs->nvm = minsrev_h << 16 | minsrev_l;
1838 minsrevs->nvm_valid = true;
1848 minsrevs->orom = minsrev_h << 16 | minsrev_l;
1849 minsrevs->orom_valid = true;
1856 * ice_update_nvm_minsrevs - Update minimum security revision TLV data in flash
1857 * @hw: pointer to the HW struct
1861 * area of the flash. Reads the minsrevs->nvm_valid and minsrevs->orom_valid
1866 ice_update_nvm_minsrevs(struct ice_hw *hw, struct ice_minsrev_info *minsrevs)
1871 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1873 if (!minsrevs->nvm_valid && !minsrevs->orom_valid) {
1874 ice_debug(hw, ICE_DBG_NVM, "At least one of NVM and OROM MinSrev must be valid");
1878 status = ice_acquire_nvm(hw, ICE_RES_WRITE);
1883 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_MINSREV_MOD_ID, 0, sizeof(data),
1888 if (minsrevs->nvm_valid) {
1889 data.nvm_minsrev_l = CPU_TO_LE16(minsrevs->nvm & 0xFFFF);
1890 data.nvm_minsrev_h = CPU_TO_LE16(minsrevs->nvm >> 16);
1894 if (minsrevs->orom_valid) {
1895 data.orom_minsrev_l = CPU_TO_LE16(minsrevs->orom & 0xFFFF);
1896 data.orom_minsrev_h = CPU_TO_LE16(minsrevs->orom >> 16);
1901 status = ice_aq_update_nvm(hw, ICE_AQC_NVM_MINSREV_MOD_ID, 0, sizeof(data), &data,
1907 status = ice_nvm_write_activate(hw, 0, NULL);
1910 ice_release_nvm(hw);
1916 * ice_nvm_access_get_features - Return the NVM access features structure
1932 if (cmd->data_size < sizeof(struct ice_nvm_features))
1936 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
1939 data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
1940 data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
1941 data->drv_features.size = sizeof(struct ice_nvm_features);
1942 data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
1948 * ice_nvm_access_get_module - Helper function to read module value
1955 return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
1959 * ice_nvm_access_get_flags - Helper function to read flags value
1966 return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
1970 * ice_nvm_access_get_adapter - Helper function to read adapter info
1977 return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
1982 * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
1997 offset = cmd->offset;
2002 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
2035 * ice_nvm_access_read - Handle an NVM read request
2036 * @hw: pointer to the HW struct
2043 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
2048 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2051 ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
2058 ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
2059 cmd->offset);
2062 data->regval = rd32(hw, cmd->offset);
2068 * ice_nvm_access_write - Handle an NVM write request
2069 * @hw: pointer to the HW struct
2076 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
2081 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2088 /* Reject requests to write to read-only registers */
2089 if (hw->mac_type == ICE_MAC_E830) {
2090 if (cmd->offset == E830_GL_HICR_EN)
2093 if (cmd->offset == GL_HICR_EN)
2097 if (cmd->offset == GLGEN_RSTAT)
2100 ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n",
2101 cmd->offset, data->regval);
2104 wr32(hw, cmd->offset, data->regval);
2110 * ice_handle_nvm_access - Handle an NVM access request
2111 * @hw: pointer to the HW struct
2123 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
2128 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
2131 if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
2134 /* Adapter info must match the HW device ID */
2136 if (adapter_info != hw->device_id)
2139 switch (cmd->command) {
2150 cmd->offset == 0)
2153 return ice_nvm_access_read(hw, cmd, data);
2155 return ice_nvm_access_write(hw, cmd, data);
2162 * ice_nvm_sanitize_operate - Clear the user data
2163 * @hw: pointer to the HW struct
2169 s32 ice_nvm_sanitize_operate(struct ice_hw *hw)
2177 status = ice_nvm_sanitize(hw, cmd_flags, &values);
2192 * ice_nvm_sanitize - Sanitize NVM
2193 * @hw: pointer to the HW struct
2201 s32 ice_nvm_sanitize(struct ice_hw *hw, u8 cmd_flags, u8 *values)
2209 cmd->cmd_flags = cmd_flags;
2211 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2213 *values = cmd->values;