Lines Matching +full:0 +full:x00120000
43 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE(_i) (0x000FD000 + ((_i) * 64)) /* _i=0...7 */ /* Reset Source: CORER */
45 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_S 0
46 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_M MAKEMASK(0x3F, 0)
48 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_M MAKEMASK(0x3F, 6)
50 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_M MAKEMASK(0x3, 12)
52 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_M MAKEMASK(0x3FF, 14)
54 #define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_M MAKEMASK(0x7, 24)
57 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
58 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
59 #define GL_HICR 0x00082040
60 #define GL_HICR_EN 0x00082044
61 #define GLGEN_CSR_DEBUG_C 0x00075750
62 #define GLNVM_GENS 0x000B6100
63 #define GLNVM_FLA 0x000B6108
67 #define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
68 #define GL_RDPU_CNTRL_RX_PAD_EN_S 0
69 #define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
77 #define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 4)
79 #define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_M MAKEMASK(0x3F, 10)
82 #define E800_GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x1F, 16)
83 #define E830_GL_RDPU_CNTRL_REQ_WB_PM_TH_M MAKEMASK(0x3F, 16)
88 #define E800_GL_RDPU_CNTRL_ECO_M MAKEMASK(0x7FF, 21)
89 #define E830_GL_RDPU_CNTRL_ECO_M MAKEMASK(0x1FF, 23)
90 #define MSIX_PBA(_i) (0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */
92 #define MSIX_PBA_PENBIT_S 0
93 #define MSIX_PBA_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
94 #define MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
96 #define MSIX_TADD_MSIXTADD10_S 0
97 #define MSIX_TADD_MSIXTADD10_M MAKEMASK(0x3, 0)
99 #define MSIX_TADD_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
100 #define MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
102 #define MSIX_TUADD_MSIXTUADD_S 0
103 #define MSIX_TUADD_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
104 #define MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
106 #define MSIX_TVCTRL_MASK_S 0
107 #define MSIX_TVCTRL_MASK_M BIT(0)
108 #define PF0_FW_HLP_ARQBAH_PAGE 0x02D00180 /* Reset Source: EMPR */
109 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_S 0
110 #define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
111 #define PF0_FW_HLP_ARQBAL_PAGE 0x02D00080 /* Reset Source: EMPR */
112 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
113 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
115 #define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
116 #define PF0_FW_HLP_ARQH_PAGE 0x02D00380 /* Reset Source: EMPR */
117 #define PF0_FW_HLP_ARQH_PAGE_ARQH_S 0
118 #define PF0_FW_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
119 #define PF0_FW_HLP_ARQLEN_PAGE 0x02D00280 /* Reset Source: EMPR */
120 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_S 0
121 #define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
130 #define PF0_FW_HLP_ARQT_PAGE 0x02D00480 /* Reset Source: EMPR */
131 #define PF0_FW_HLP_ARQT_PAGE_ARQT_S 0
132 #define PF0_FW_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
133 #define PF0_FW_HLP_ATQBAH_PAGE 0x02D00100 /* Reset Source: EMPR */
134 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_S 0
135 #define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
136 #define PF0_FW_HLP_ATQBAL_PAGE 0x02D00000 /* Reset Source: EMPR */
137 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_S 0
138 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
140 #define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
141 #define PF0_FW_HLP_ATQH_PAGE 0x02D00300 /* Reset Source: EMPR */
142 #define PF0_FW_HLP_ATQH_PAGE_ATQH_S 0
143 #define PF0_FW_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
144 #define PF0_FW_HLP_ATQLEN_PAGE 0x02D00200 /* Reset Source: EMPR */
145 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_S 0
146 #define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
155 #define PF0_FW_HLP_ATQT_PAGE 0x02D00400 /* Reset Source: EMPR */
156 #define PF0_FW_HLP_ATQT_PAGE_ATQT_S 0
157 #define PF0_FW_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
158 #define PF0_FW_PSM_ARQBAH_PAGE 0x02D40180 /* Reset Source: EMPR */
159 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_S 0
160 #define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
161 #define PF0_FW_PSM_ARQBAL_PAGE 0x02D40080 /* Reset Source: EMPR */
162 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0
163 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
165 #define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
166 #define PF0_FW_PSM_ARQH_PAGE 0x02D40380 /* Reset Source: EMPR */
167 #define PF0_FW_PSM_ARQH_PAGE_ARQH_S 0
168 #define PF0_FW_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
169 #define PF0_FW_PSM_ARQLEN_PAGE 0x02D40280 /* Reset Source: EMPR */
170 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_S 0
171 #define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
180 #define PF0_FW_PSM_ARQT_PAGE 0x02D40480 /* Reset Source: EMPR */
181 #define PF0_FW_PSM_ARQT_PAGE_ARQT_S 0
182 #define PF0_FW_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
183 #define PF0_FW_PSM_ATQBAH_PAGE 0x02D40100 /* Reset Source: EMPR */
184 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_S 0
185 #define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
186 #define PF0_FW_PSM_ATQBAL_PAGE 0x02D40000 /* Reset Source: EMPR */
187 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_S 0
188 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
190 #define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
191 #define PF0_FW_PSM_ATQH_PAGE 0x02D40300 /* Reset Source: EMPR */
192 #define PF0_FW_PSM_ATQH_PAGE_ATQH_S 0
193 #define PF0_FW_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
194 #define PF0_FW_PSM_ATQLEN_PAGE 0x02D40200 /* Reset Source: EMPR */
195 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_S 0
196 #define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
205 #define PF0_FW_PSM_ATQT_PAGE 0x02D40400 /* Reset Source: EMPR */
206 #define PF0_FW_PSM_ATQT_PAGE_ATQT_S 0
207 #define PF0_FW_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
208 #define PF0_MBX_CPM_ARQBAH_PAGE 0x02D80190 /* Reset Source: CORER */
209 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_S 0
210 #define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
211 #define PF0_MBX_CPM_ARQBAL_PAGE 0x02D80090 /* Reset Source: CORER */
212 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0
213 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
215 #define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
216 #define PF0_MBX_CPM_ARQH_PAGE 0x02D80390 /* Reset Source: CORER */
217 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_S 0
218 #define PF0_MBX_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
219 #define PF0_MBX_CPM_ARQLEN_PAGE 0x02D80290 /* Reset Source: PFR */
220 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_S 0
221 #define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
230 #define PF0_MBX_CPM_ARQT_PAGE 0x02D80490 /* Reset Source: CORER */
231 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_S 0
232 #define PF0_MBX_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
233 #define PF0_MBX_CPM_ATQBAH_PAGE 0x02D80110 /* Reset Source: CORER */
234 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_S 0
235 #define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
236 #define PF0_MBX_CPM_ATQBAL_PAGE 0x02D80010 /* Reset Source: CORER */
238 #define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
239 #define PF0_MBX_CPM_ATQH_PAGE 0x02D80310 /* Reset Source: CORER */
240 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_S 0
241 #define PF0_MBX_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
242 #define PF0_MBX_CPM_ATQLEN_PAGE 0x02D80210 /* Reset Source: PFR */
243 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_S 0
244 #define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
253 #define PF0_MBX_CPM_ATQT_PAGE 0x02D80410 /* Reset Source: CORER */
254 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_S 0
255 #define PF0_MBX_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
256 #define PF0_MBX_HLP_ARQBAH_PAGE 0x02D00190 /* Reset Source: CORER */
257 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_S 0
258 #define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
259 #define PF0_MBX_HLP_ARQBAL_PAGE 0x02D00090 /* Reset Source: CORER */
260 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
261 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
263 #define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
264 #define PF0_MBX_HLP_ARQH_PAGE 0x02D00390 /* Reset Source: CORER */
265 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_S 0
266 #define PF0_MBX_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
267 #define PF0_MBX_HLP_ARQLEN_PAGE 0x02D00290 /* Reset Source: PFR */
268 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_S 0
269 #define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
278 #define PF0_MBX_HLP_ARQT_PAGE 0x02D00490 /* Reset Source: CORER */
279 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_S 0
280 #define PF0_MBX_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
281 #define PF0_MBX_HLP_ATQBAH_PAGE 0x02D00110 /* Reset Source: CORER */
282 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_S 0
283 #define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
284 #define PF0_MBX_HLP_ATQBAL_PAGE 0x02D00010 /* Reset Source: CORER */
286 #define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
287 #define PF0_MBX_HLP_ATQH_PAGE 0x02D00310 /* Reset Source: CORER */
288 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_S 0
289 #define PF0_MBX_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
290 #define PF0_MBX_HLP_ATQLEN_PAGE 0x02D00210 /* Reset Source: PFR */
291 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_S 0
292 #define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
301 #define PF0_MBX_HLP_ATQT_PAGE 0x02D00410 /* Reset Source: CORER */
302 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_S 0
303 #define PF0_MBX_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
304 #define PF0_MBX_PSM_ARQBAH_PAGE 0x02D40190 /* Reset Source: CORER */
305 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_S 0
306 #define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
307 #define PF0_MBX_PSM_ARQBAL_PAGE 0x02D40090 /* Reset Source: CORER */
308 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_S 0
309 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
311 #define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
312 #define PF0_MBX_PSM_ARQH_PAGE 0x02D40390 /* Reset Source: CORER */
313 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_S 0
314 #define PF0_MBX_PSM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
315 #define PF0_MBX_PSM_ARQLEN_PAGE 0x02D40290 /* Reset Source: PFR */
316 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_S 0
317 #define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
326 #define PF0_MBX_PSM_ARQT_PAGE 0x02D40490 /* Reset Source: CORER */
327 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_S 0
328 #define PF0_MBX_PSM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
329 #define PF0_MBX_PSM_ATQBAH_PAGE 0x02D40110 /* Reset Source: CORER */
330 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_S 0
331 #define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
332 #define PF0_MBX_PSM_ATQBAL_PAGE 0x02D40010 /* Reset Source: CORER */
334 #define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
335 #define PF0_MBX_PSM_ATQH_PAGE 0x02D40310 /* Reset Source: CORER */
336 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_S 0
337 #define PF0_MBX_PSM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
338 #define PF0_MBX_PSM_ATQLEN_PAGE 0x02D40210 /* Reset Source: PFR */
339 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_S 0
340 #define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
349 #define PF0_MBX_PSM_ATQT_PAGE 0x02D40410 /* Reset Source: CORER */
350 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_S 0
351 #define PF0_MBX_PSM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
352 #define PF0_SB_CPM_ARQBAH_PAGE 0x02D801A0 /* Reset Source: CORER */
353 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_S 0
354 #define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
355 #define PF0_SB_CPM_ARQBAL_PAGE 0x02D800A0 /* Reset Source: CORER */
356 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_S 0
357 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
359 #define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
360 #define PF0_SB_CPM_ARQH_PAGE 0x02D803A0 /* Reset Source: CORER */
361 #define PF0_SB_CPM_ARQH_PAGE_ARQH_S 0
362 #define PF0_SB_CPM_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
363 #define PF0_SB_CPM_ARQLEN_PAGE 0x02D802A0 /* Reset Source: PFR */
364 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_S 0
365 #define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
374 #define PF0_SB_CPM_ARQT_PAGE 0x02D804A0 /* Reset Source: CORER */
375 #define PF0_SB_CPM_ARQT_PAGE_ARQT_S 0
376 #define PF0_SB_CPM_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
377 #define PF0_SB_CPM_ATQBAH_PAGE 0x02D80120 /* Reset Source: CORER */
378 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_S 0
379 #define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
380 #define PF0_SB_CPM_ATQBAL_PAGE 0x02D80020 /* Reset Source: CORER */
382 #define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
383 #define PF0_SB_CPM_ATQH_PAGE 0x02D80320 /* Reset Source: CORER */
384 #define PF0_SB_CPM_ATQH_PAGE_ATQH_S 0
385 #define PF0_SB_CPM_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
386 #define PF0_SB_CPM_ATQLEN_PAGE 0x02D80220 /* Reset Source: PFR */
387 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_S 0
388 #define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
397 #define PF0_SB_CPM_ATQT_PAGE 0x02D80420 /* Reset Source: CORER */
398 #define PF0_SB_CPM_ATQT_PAGE_ATQT_S 0
399 #define PF0_SB_CPM_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
400 #define PF0_SB_HLP_ARQBAH_PAGE 0x02D001A0 /* Reset Source: CORER */
401 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_S 0
402 #define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
403 #define PF0_SB_HLP_ARQBAL_PAGE 0x02D000A0 /* Reset Source: CORER */
404 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_S 0
405 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
407 #define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
408 #define PF0_SB_HLP_ARQH_PAGE 0x02D003A0 /* Reset Source: CORER */
409 #define PF0_SB_HLP_ARQH_PAGE_ARQH_S 0
410 #define PF0_SB_HLP_ARQH_PAGE_ARQH_M MAKEMASK(0x3FF, 0)
411 #define PF0_SB_HLP_ARQLEN_PAGE 0x02D002A0 /* Reset Source: PFR */
412 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_S 0
413 #define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_M MAKEMASK(0x3FF, 0)
422 #define PF0_SB_HLP_ARQT_PAGE 0x02D004A0 /* Reset Source: CORER */
423 #define PF0_SB_HLP_ARQT_PAGE_ARQT_S 0
424 #define PF0_SB_HLP_ARQT_PAGE_ARQT_M MAKEMASK(0x3FF, 0)
425 #define PF0_SB_HLP_ATQBAH_PAGE 0x02D00120 /* Reset Source: CORER */
426 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_S 0
427 #define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
428 #define PF0_SB_HLP_ATQBAL_PAGE 0x02D00020 /* Reset Source: CORER */
430 #define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
431 #define PF0_SB_HLP_ATQH_PAGE 0x02D00320 /* Reset Source: CORER */
432 #define PF0_SB_HLP_ATQH_PAGE_ATQH_S 0
433 #define PF0_SB_HLP_ATQH_PAGE_ATQH_M MAKEMASK(0x3FF, 0)
434 #define PF0_SB_HLP_ATQLEN_PAGE 0x02D00220 /* Reset Source: PFR */
435 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_S 0
436 #define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_M MAKEMASK(0x3FF, 0)
445 #define PF0_SB_HLP_ATQT_PAGE 0x02D00420 /* Reset Source: CORER */
446 #define PF0_SB_HLP_ATQT_PAGE_ATQT_S 0
447 #define PF0_SB_HLP_ATQT_PAGE_ATQT_M MAKEMASK(0x3FF, 0)
448 #define PF0INT_DYN_CTL(_i) (0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
450 #define PF0INT_DYN_CTL_INTENA_S 0
451 #define PF0INT_DYN_CTL_INTENA_M BIT(0)
457 #define PF0INT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
459 #define PF0INT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
463 #define PF0INT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
468 #define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
470 #define PF0INT_ITR_0_INTERVAL_S 0
471 #define PF0INT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0)
472 #define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
474 #define PF0INT_ITR_1_INTERVAL_S 0
475 #define PF0INT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0)
476 #define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
478 #define PF0INT_ITR_2_INTERVAL_S 0
479 #define PF0INT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0)
480 #define PF0INT_OICR_CPM_PAGE 0x02D03000 /* Reset Source: CORER */
481 #define PF0INT_OICR_CPM_PAGE_INTEVENT_S 0
482 #define PF0INT_OICR_CPM_PAGE_INTEVENT_M BIT(0)
487 #define E800_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
488 #define E830_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0x3F, 2)
504 #define PF0INT_OICR_CPM_PAGE_RSV2_M MAKEMASK(0x3, 17)
531 #define PF0INT_OICR_ENA_CPM_PAGE 0x02D03100 /* Reset Source: CORER */
532 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_S 0
533 #define PF0INT_OICR_ENA_CPM_PAGE_RSV0_M BIT(0)
535 #define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
536 #define PF0INT_OICR_ENA_HLP_PAGE 0x02D01100 /* Reset Source: CORER */
537 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_S 0
538 #define PF0INT_OICR_ENA_HLP_PAGE_RSV0_M BIT(0)
540 #define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
541 #define PF0INT_OICR_ENA_PSM_PAGE 0x02D02100 /* Reset Source: CORER */
542 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_S 0
543 #define PF0INT_OICR_ENA_PSM_PAGE_RSV0_M BIT(0)
545 #define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
546 #define PF0INT_OICR_HLP_PAGE 0x02D01000 /* Reset Source: CORER */
547 #define PF0INT_OICR_HLP_PAGE_INTEVENT_S 0
548 #define PF0INT_OICR_HLP_PAGE_INTEVENT_M BIT(0)
553 #define E800_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2)
554 #define E830_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0x3F, 2)
570 #define PF0INT_OICR_HLP_PAGE_RSV2_M MAKEMASK(0x3, 17)
597 #define PF0INT_OICR_PSM_PAGE 0x02D02000 /* Reset Source: CORER */
598 #define PF0INT_OICR_PSM_PAGE_INTEVENT_S 0
599 #define PF0INT_OICR_PSM_PAGE_INTEVENT_M BIT(0)
604 #define E800_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2)
605 #define E830_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0x3F, 2)
621 #define PF0INT_OICR_PSM_PAGE_RSV2_M MAKEMASK(0x3, 17)
648 #define QRX_TAIL_PAGE(_QRX) (0x03800000 + ((_QRX) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */
650 #define QRX_TAIL_PAGE_TAIL_S 0
651 #define QRX_TAIL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
652 #define QTX_COMM_DBELL_PAGE(_DBQM) (0x04000000 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
654 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S 0
655 #define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
656 #define E800_QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ) (0x02F00000 + ((_DBLQ) * 4096)) /* _i=0...255 */ /* Reset Source: CORER */
658 #define E800_QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S 0
659 #define E800_QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M MAKEMASK(0x1FFF, 0)
660 #define VSI_MBX_ARQBAH(_VSI) (0x02000018 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
662 #define VSI_MBX_ARQBAH_ARQBAH_S 0
663 #define VSI_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
664 #define VSI_MBX_ARQBAL(_VSI) (0x02000014 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
666 #define VSI_MBX_ARQBAL_ARQBAL_LSB_S 0
667 #define VSI_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
669 #define VSI_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
670 #define VSI_MBX_ARQH(_VSI) (0x02000020 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
672 #define VSI_MBX_ARQH_ARQH_S 0
673 #define VSI_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
674 #define VSI_MBX_ARQLEN(_VSI) (0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
676 #define VSI_MBX_ARQLEN_ARQLEN_S 0
677 #define VSI_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
686 #define VSI_MBX_ARQT(_VSI) (0x02000024 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
688 #define VSI_MBX_ARQT_ARQT_S 0
689 #define VSI_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
690 #define VSI_MBX_ATQBAH(_VSI) (0x02000004 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
692 #define VSI_MBX_ATQBAH_ATQBAH_S 0
693 #define VSI_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
694 #define VSI_MBX_ATQBAL(_VSI) (0x02000000 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
697 #define VSI_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
698 #define VSI_MBX_ATQH(_VSI) (0x0200000C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
700 #define VSI_MBX_ATQH_ATQH_S 0
701 #define VSI_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
702 #define VSI_MBX_ATQLEN(_VSI) (0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: PFR */
704 #define VSI_MBX_ATQLEN_ATQLEN_S 0
705 #define VSI_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
714 #define VSI_MBX_ATQT(_VSI) (0x02000010 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */
716 #define VSI_MBX_ATQT_ATQT_S 0
717 #define VSI_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
718 #define GL_ACL_ACCESS_CMD 0x00391000 /* Reset Source: CORER */
719 #define GL_ACL_ACCESS_CMD_TABLE_ID_S 0
720 #define GL_ACL_ACCESS_CMD_TABLE_ID_M MAKEMASK(0xFF, 0)
722 #define GL_ACL_ACCESS_CMD_ENTRY_INDEX_M MAKEMASK(0xFFF, 8)
726 #define GL_ACL_ACCESS_CMD_OBJ_TYPE_M MAKEMASK(0xF, 24)
729 #define GL_ACL_ACCESS_STATUS 0x00391004 /* Reset Source: CORER */
730 #define GL_ACL_ACCESS_STATUS_BUSY_S 0
731 #define GL_ACL_ACCESS_STATUS_BUSY_M BIT(0)
739 #define GL_ACL_ACCESS_STATUS_ERROR_CODE_M MAKEMASK(0xF, 4)
741 #define GL_ACL_ACCESS_STATUS_TABLE_ID_M MAKEMASK(0xFF, 8)
743 #define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_M MAKEMASK(0xFFF, 16)
745 #define GL_ACL_ACCESS_STATUS_OBJ_TYPE_M MAKEMASK(0xF, 28)
746 #define GL_ACL_ACTMEM_ACT(_i) (0x00393824 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
748 #define GL_ACL_ACTMEM_ACT_VALUE_S 0
749 #define GL_ACL_ACTMEM_ACT_VALUE_M MAKEMASK(0xFFFF, 0)
751 #define GL_ACL_ACTMEM_ACT_MDID_M MAKEMASK(0x3F, 20)
753 #define GL_ACL_ACTMEM_ACT_PRIORITY_M MAKEMASK(0x7, 28)
754 #define GL_ACL_CHICKEN_REGISTER 0x00393810 /* Reset Source: CORER */
755 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_S 0
756 #define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_M BIT(0)
759 #define GL_ACL_DEFAULT_ACT(_i) (0x00391168 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
761 #define GL_ACL_DEFAULT_ACT_VALUE_S 0
762 #define GL_ACL_DEFAULT_ACT_VALUE_M MAKEMASK(0xFFFF, 0)
764 #define GL_ACL_DEFAULT_ACT_MDID_M MAKEMASK(0x3F, 20)
766 #define GL_ACL_DEFAULT_ACT_PRIORITY_M MAKEMASK(0x7, 28)
767 #define GL_ACL_PROFILE_BWSB_SEL(_i) (0x00391008 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
769 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S 0
770 #define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M MAKEMASK(0x3F, 0)
772 #define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8)
773 #define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
775 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
776 #define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
777 #define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
779 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0
780 #define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M MAKEMASK(0x3F, 0)
781 #define GL_ACL_PROFILE_RC_CFG(_i) (0x003910E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
783 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S 0
784 #define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M MAKEMASK(0xFFFF, 0)
786 #define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_M MAKEMASK(0xFFFF, 16)
787 #define GL_ACL_PROFILE_RCF_MASK(_i) (0x00391108 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
789 #define GL_ACL_PROFILE_RCF_MASK_MASK_S 0
790 #define GL_ACL_PROFILE_RCF_MASK_MASK_M MAKEMASK(0xFFFF, 0)
791 #define GL_ACL_SCENARIO_ACT_CFG(_i) (0x003938AC + ((_i) * 4)) /* _i=0...19 */ /* Reset Source: CORER */
793 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_S 0
794 #define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_M MAKEMASK(0xF, 0)
797 #define GL_ACL_SCENARIO_CFG_H(_i) (0x0039386C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
799 #define GL_ACL_SCENARIO_CFG_H_SELECT4_S 0
800 #define GL_ACL_SCENARIO_CFG_H_SELECT4_M MAKEMASK(0x1F, 0)
802 #define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_M MAKEMASK(0xFF, 8)
807 #define GL_ACL_SCENARIO_CFG_L(_i) (0x0039382C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
809 #define GL_ACL_SCENARIO_CFG_L_SELECT0_S 0
810 #define GL_ACL_SCENARIO_CFG_L_SELECT0_M MAKEMASK(0x7F, 0)
812 #define GL_ACL_SCENARIO_CFG_L_SELECT1_M MAKEMASK(0x7F, 8)
814 #define GL_ACL_SCENARIO_CFG_L_SELECT2_M MAKEMASK(0x7F, 16)
816 #define GL_ACL_SCENARIO_CFG_L_SELECT3_M MAKEMASK(0x7F, 24)
817 #define GL_ACL_TCAM_KEY_H 0x00393818 /* Reset Source: CORER */
818 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_S 0
819 #define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_M MAKEMASK(0xFF, 0)
820 #define GL_ACL_TCAM_KEY_INV_H 0x00393820 /* Reset Source: CORER */
821 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_S 0
822 #define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_M MAKEMASK(0xFF, 0)
823 #define GL_ACL_TCAM_KEY_INV_L 0x0039381C /* Reset Source: CORER */
824 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_S 0
825 #define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_M MAKEMASK(0xFFFFFFFF, 0)
826 #define GL_ACL_TCAM_KEY_L 0x00393814 /* Reset Source: CORER */
827 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_S 0
828 #define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_M MAKEMASK(0xFFFFFFFF, 0)
829 #define VSI_ACL_DEF_SEL(_VSI) (0x00391800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
831 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_S 0
832 #define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 0)
834 #define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_M MAKEMASK(0x3, 4)
836 #define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_M MAKEMASK(0x3, 8)
838 #define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_M MAKEMASK(0x3, 12)
839 #define GL_SWT_L2TAG0(_i) (0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
841 #define GL_SWT_L2TAG0_DATA_S 0
842 #define GL_SWT_L2TAG0_DATA_M MAKEMASK(0xFFFFFFFF, 0)
843 #define GL_SWT_L2TAG1(_i) (0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
845 #define GL_SWT_L2TAG1_DATA_S 0
846 #define GL_SWT_L2TAG1_DATA_M MAKEMASK(0xFFFFFFFF, 0)
847 #define GL_SWT_L2TAGCTRL(_i) (0x001D2660 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
849 #define GL_SWT_L2TAGCTRL_LENGTH_S 0
850 #define GL_SWT_L2TAGCTRL_LENGTH_M MAKEMASK(0x7F, 0)
866 #define GL_SWT_L2TAGCTRL_ETHERTYPE_M MAKEMASK(0xFFFF, 16)
867 #define GL_SWT_L2TAGRXEB(_i) (0x00052000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
869 #define GL_SWT_L2TAGRXEB_OFFSET_S 0
870 #define GL_SWT_L2TAGRXEB_OFFSET_M MAKEMASK(0xFF, 0)
872 #define GL_SWT_L2TAGRXEB_LENGTH_M MAKEMASK(0x3, 8)
873 #define GL_SWT_L2TAGTXIB(_i) (0x000492E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
875 #define GL_SWT_L2TAGTXIB_OFFSET_S 0
876 #define GL_SWT_L2TAGTXIB_OFFSET_M MAKEMASK(0xFF, 0)
878 #define GL_SWT_L2TAGTXIB_LENGTH_M MAKEMASK(0x3, 8)
879 #define GLCM_PE_CACHESIZE 0x005046B4 /* Reset Source: CORER */
880 #define GLCM_PE_CACHESIZE_WORD_SIZE_S 0
881 #define GLCM_PE_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFFF, 0)
883 #define GLCM_PE_CACHESIZE_SETS_M MAKEMASK(0xF, 12)
885 #define GLCM_PE_CACHESIZE_WAYS_M MAKEMASK(0x1FF, 16)
886 #define GLCOMM_CQ_CTL(_CQ) (0x000F0000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
888 #define GLCOMM_CQ_CTL_COMP_TYPE_S 0
889 #define GLCOMM_CQ_CTL_COMP_TYPE_M MAKEMASK(0x7, 0)
891 #define GLCOMM_CQ_CTL_CMD_M MAKEMASK(0x7, 4)
893 #define GLCOMM_CQ_CTL_ID_M MAKEMASK(0x3FFF, 16)
894 #define GLCOMM_MIN_MAX_PKT 0x000FC064 /* Reset Source: CORER */
895 #define GLCOMM_MIN_MAX_PKT_MAHDL_S 0
896 #define GLCOMM_MIN_MAX_PKT_MAHDL_M MAKEMASK(0x3FFF, 0)
898 #define GLCOMM_MIN_MAX_PKT_MIHDL_M MAKEMASK(0x3F, 16)
900 #define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_M MAKEMASK(0x3FF, 22)
901 #define GLCOMM_PKT_SHAPER_PROF(_i) (0x002D2DA8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
903 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_S 0
904 #define GLCOMM_PKT_SHAPER_PROF_PKTCNT_M MAKEMASK(0x3F, 0)
905 #define GLCOMM_QTX_CNTX_CTL 0x002D2DC8 /* Reset Source: CORER */
906 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_S 0
907 #define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x3FFF, 0)
909 #define GLCOMM_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16)
912 #define GLCOMM_QTX_CNTX_DATA(_i) (0x002D2D40 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: CORER */
914 #define GLCOMM_QTX_CNTX_DATA_DATA_S 0
915 #define GLCOMM_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
916 #define GLCOMM_QTX_CNTX_STAT 0x002D2DCC /* Reset Source: CORER */
917 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_S 0
918 #define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)
919 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
921 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S 0
922 #define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M MAKEMASK(0x3FFF, 0)
924 #define GLCOMM_QUANTA_PROF_MAX_CMD_M MAKEMASK(0xFF, 16)
926 #define GLCOMM_QUANTA_PROF_MAX_DESC_M MAKEMASK(0x3F, 24)
927 #define GLLAN_TCLAN_CACHE_CTL 0x000FC0B8 /* Reset Source: CORER */
928 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0
929 #define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0)
933 #define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)
935 #define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
937 #define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22)
938 #define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
940 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S 0
941 #define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M MAKEMASK(0xFFFFFFFF, 0)
942 #define GLTCLAN_CQ_CNTX1(_CQ) (0x000F1000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
944 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_S 0
945 #define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_M MAKEMASK(0x1FFFFFF, 0)
946 #define GLTCLAN_CQ_CNTX10(_CQ) (0x000F5800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
948 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_S 0
949 #define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
950 #define GLTCLAN_CQ_CNTX11(_CQ) (0x000F6000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
952 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_S 0
953 #define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
954 #define GLTCLAN_CQ_CNTX12(_CQ) (0x000F6800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
956 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_S 0
957 #define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
958 #define GLTCLAN_CQ_CNTX13(_CQ) (0x000F7000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
960 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_S 0
961 #define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
962 #define GLTCLAN_CQ_CNTX14(_CQ) (0x000F7800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
964 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_S 0
965 #define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
966 #define GLTCLAN_CQ_CNTX15(_CQ) (0x000F8000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
968 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_S 0
969 #define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
970 #define GLTCLAN_CQ_CNTX16(_CQ) (0x000F8800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
972 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_S 0
973 #define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
974 #define GLTCLAN_CQ_CNTX17(_CQ) (0x000F9000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
976 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_S 0
977 #define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
978 #define GLTCLAN_CQ_CNTX18(_CQ) (0x000F9800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
980 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_S 0
981 #define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
982 #define GLTCLAN_CQ_CNTX19(_CQ) (0x000FA000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
984 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_S 0
985 #define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
986 #define GLTCLAN_CQ_CNTX2(_CQ) (0x000F1800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
988 #define GLTCLAN_CQ_CNTX2_RING_LEN_S 0
989 #define GLTCLAN_CQ_CNTX2_RING_LEN_M MAKEMASK(0x3FFFF, 0)
990 #define GLTCLAN_CQ_CNTX20(_CQ) (0x000FA800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
992 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_S 0
993 #define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
994 #define GLTCLAN_CQ_CNTX21(_CQ) (0x000FB000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
996 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_S 0
997 #define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
998 #define GLTCLAN_CQ_CNTX3(_CQ) (0x000F2000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1000 #define GLTCLAN_CQ_CNTX3_GENERATION_S 0
1001 #define GLTCLAN_CQ_CNTX3_GENERATION_M BIT(0)
1003 #define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_M MAKEMASK(0x3FFFFF, 1)
1004 #define GLTCLAN_CQ_CNTX4(_CQ) (0x000F2800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1006 #define GLTCLAN_CQ_CNTX4_PF_NUM_S 0
1007 #define GLTCLAN_CQ_CNTX4_PF_NUM_M MAKEMASK(0x7, 0)
1009 #define GLTCLAN_CQ_CNTX4_VMVF_NUM_M MAKEMASK(0x3FF, 3)
1011 #define GLTCLAN_CQ_CNTX4_VMVF_TYPE_M MAKEMASK(0x3, 13)
1012 #define GLTCLAN_CQ_CNTX5(_CQ) (0x000F3000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1014 #define GLTCLAN_CQ_CNTX5_TPH_EN_S 0
1015 #define GLTCLAN_CQ_CNTX5_TPH_EN_M BIT(0)
1017 #define GLTCLAN_CQ_CNTX5_CPU_ID_M MAKEMASK(0xFF, 1)
1020 #define GLTCLAN_CQ_CNTX6(_CQ) (0x000F3800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1022 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_S 0
1023 #define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1024 #define GLTCLAN_CQ_CNTX7(_CQ) (0x000F4000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1026 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_S 0
1027 #define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1028 #define GLTCLAN_CQ_CNTX8(_CQ) (0x000F4800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1030 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_S 0
1031 #define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1032 #define GLTCLAN_CQ_CNTX9(_CQ) (0x000F5000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
1034 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_S 0
1035 #define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_M MAKEMASK(0xFFFFFFFF, 0)
1036 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
1038 #define QTX_COMM_DBELL_QTX_COMM_DBELL_S 0
1039 #define QTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
1040 #define QTX_COMM_DBLQ_CNTX(_i, _DBLQ) (0x002D0000 + ((_i) * 1024 + (_DBLQ) * 4)) /* _i=0...4, _DBLQ=0...255 */ /* Reset Source: CORER */
1042 #define QTX_COMM_DBLQ_CNTX_DATA_S 0
1043 #define QTX_COMM_DBLQ_CNTX_DATA_M MAKEMASK(0xFFFFFFFF, 0)
1044 #define QTX_COMM_DBLQ_DBELL(_DBLQ) (0x002D1400 + ((_DBLQ) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1046 #define QTX_COMM_DBLQ_DBELL_TAIL_S 0
1047 #define QTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0)
1048 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
1050 #define QTX_COMM_HEAD_HEAD_S 0
1051 #define QTX_COMM_HEAD_HEAD_M MAKEMASK(0x1FFF, 0)
1054 #define GL_FW_TOOL_ARQBAH 0x000801C0 /* Reset Source: EMPR */
1055 #define GL_FW_TOOL_ARQBAH_ARQBAH_S 0
1056 #define GL_FW_TOOL_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1057 #define GL_FW_TOOL_ARQBAL 0x000800C0 /* Reset Source: EMPR */
1058 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_S 0
1059 #define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1061 #define GL_FW_TOOL_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1062 #define GL_FW_TOOL_ARQH 0x000803C0 /* Reset Source: EMPR */
1063 #define GL_FW_TOOL_ARQH_ARQH_S 0
1064 #define GL_FW_TOOL_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1065 #define GL_FW_TOOL_ARQLEN 0x000802C0 /* Reset Source: EMPR */
1066 #define GL_FW_TOOL_ARQLEN_ARQLEN_S 0
1067 #define GL_FW_TOOL_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1076 #define GL_FW_TOOL_ARQT 0x000804C0 /* Reset Source: EMPR */
1077 #define GL_FW_TOOL_ARQT_ARQT_S 0
1078 #define GL_FW_TOOL_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1079 #define GL_FW_TOOL_ATQBAH 0x00080140 /* Reset Source: EMPR */
1080 #define GL_FW_TOOL_ATQBAH_ATQBAH_S 0
1081 #define GL_FW_TOOL_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1082 #define GL_FW_TOOL_ATQBAL 0x00080040 /* Reset Source: EMPR */
1083 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_S 0
1084 #define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1086 #define GL_FW_TOOL_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1087 #define GL_FW_TOOL_ATQH 0x00080340 /* Reset Source: EMPR */
1088 #define GL_FW_TOOL_ATQH_ATQH_S 0
1089 #define GL_FW_TOOL_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1090 #define GL_FW_TOOL_ATQLEN 0x00080240 /* Reset Source: EMPR */
1091 #define GL_FW_TOOL_ATQLEN_ATQLEN_S 0
1092 #define GL_FW_TOOL_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1101 #define GL_FW_TOOL_ATQT 0x00080440 /* Reset Source: EMPR */
1102 #define GL_FW_TOOL_ATQT_ATQT_S 0
1103 #define GL_FW_TOOL_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1104 #define GL_MBX_PASID 0x00231EC0 /* Reset Source: CORER */
1105 #define GL_MBX_PASID_PASID_MODE_S 0
1106 #define GL_MBX_PASID_PASID_MODE_M BIT(0)
1109 #define PF_FW_ARQBAH 0x00080180 /* Reset Source: EMPR */
1110 #define PF_FW_ARQBAH_ARQBAH_S 0
1111 #define PF_FW_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1112 #define PF_FW_ARQBAL 0x00080080 /* Reset Source: EMPR */
1113 #define PF_FW_ARQBAL_ARQBAL_LSB_S 0
1114 #define PF_FW_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1116 #define PF_FW_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1117 #define PF_FW_ARQH 0x00080380 /* Reset Source: EMPR */
1118 #define PF_FW_ARQH_ARQH_S 0
1119 #define PF_FW_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1120 #define PF_FW_ARQLEN 0x00080280 /* Reset Source: EMPR */
1121 #define PF_FW_ARQLEN_ARQLEN_S 0
1122 #define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1131 #define PF_FW_ARQT 0x00080480 /* Reset Source: EMPR */
1132 #define PF_FW_ARQT_ARQT_S 0
1133 #define PF_FW_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1134 #define PF_FW_ATQBAH 0x00080100 /* Reset Source: EMPR */
1135 #define PF_FW_ATQBAH_ATQBAH_S 0
1136 #define PF_FW_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1137 #define PF_FW_ATQBAL 0x00080000 /* Reset Source: EMPR */
1138 #define PF_FW_ATQBAL_ATQBAL_LSB_S 0
1139 #define PF_FW_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1141 #define PF_FW_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1142 #define PF_FW_ATQH 0x00080300 /* Reset Source: EMPR */
1143 #define PF_FW_ATQH_ATQH_S 0
1144 #define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1145 #define PF_FW_ATQLEN 0x00080200 /* Reset Source: EMPR */
1146 #define PF_FW_ATQLEN_ATQLEN_S 0
1147 #define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1156 #define PF_FW_ATQT 0x00080400 /* Reset Source: EMPR */
1157 #define PF_FW_ATQT_ATQT_S 0
1158 #define PF_FW_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1159 #define PF_MBX_ARQBAH 0x0022E400 /* Reset Source: CORER */
1160 #define PF_MBX_ARQBAH_ARQBAH_S 0
1161 #define PF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1162 #define PF_MBX_ARQBAL 0x0022E380 /* Reset Source: CORER */
1163 #define PF_MBX_ARQBAL_ARQBAL_LSB_S 0
1164 #define PF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1166 #define PF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1167 #define PF_MBX_ARQH 0x0022E500 /* Reset Source: CORER */
1168 #define PF_MBX_ARQH_ARQH_S 0
1169 #define PF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1170 #define PF_MBX_ARQLEN 0x0022E480 /* Reset Source: PFR */
1171 #define PF_MBX_ARQLEN_ARQLEN_S 0
1172 #define PF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1181 #define PF_MBX_ARQT 0x0022E580 /* Reset Source: CORER */
1182 #define PF_MBX_ARQT_ARQT_S 0
1183 #define PF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1184 #define PF_MBX_ATQBAH 0x0022E180 /* Reset Source: CORER */
1185 #define PF_MBX_ATQBAH_ATQBAH_S 0
1186 #define PF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1187 #define PF_MBX_ATQBAL 0x0022E100 /* Reset Source: CORER */
1189 #define PF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1190 #define PF_MBX_ATQH 0x0022E280 /* Reset Source: CORER */
1191 #define PF_MBX_ATQH_ATQH_S 0
1192 #define PF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1193 #define PF_MBX_ATQLEN 0x0022E200 /* Reset Source: PFR */
1194 #define PF_MBX_ATQLEN_ATQLEN_S 0
1195 #define PF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1204 #define PF_MBX_ATQT 0x0022E300 /* Reset Source: CORER */
1205 #define PF_MBX_ATQT_ATQT_S 0
1206 #define PF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1207 #define PF_SB_ARQBAH 0x0022FF00 /* Reset Source: CORER */
1208 #define PF_SB_ARQBAH_ARQBAH_S 0
1209 #define PF_SB_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1210 #define PF_SB_ARQBAL 0x0022FE80 /* Reset Source: CORER */
1211 #define PF_SB_ARQBAL_ARQBAL_LSB_S 0
1212 #define PF_SB_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1214 #define PF_SB_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1215 #define PF_SB_ARQH 0x00230000 /* Reset Source: CORER */
1216 #define PF_SB_ARQH_ARQH_S 0
1217 #define PF_SB_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1218 #define PF_SB_ARQLEN 0x0022FF80 /* Reset Source: PFR */
1219 #define PF_SB_ARQLEN_ARQLEN_S 0
1220 #define PF_SB_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1229 #define PF_SB_ARQT 0x00230080 /* Reset Source: CORER */
1230 #define PF_SB_ARQT_ARQT_S 0
1231 #define PF_SB_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1232 #define PF_SB_ATQBAH 0x0022FC80 /* Reset Source: CORER */
1233 #define PF_SB_ATQBAH_ATQBAH_S 0
1234 #define PF_SB_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1235 #define PF_SB_ATQBAL 0x0022FC00 /* Reset Source: CORER */
1237 #define PF_SB_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1238 #define PF_SB_ATQH 0x0022FD80 /* Reset Source: CORER */
1239 #define PF_SB_ATQH_ATQH_S 0
1240 #define PF_SB_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1241 #define PF_SB_ATQLEN 0x0022FD00 /* Reset Source: PFR */
1242 #define PF_SB_ATQLEN_ATQLEN_S 0
1243 #define PF_SB_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1252 #define PF_SB_ATQT 0x0022FE00 /* Reset Source: CORER */
1253 #define PF_SB_ATQT_ATQT_S 0
1254 #define PF_SB_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1255 #define PF_SB_REM_DEV_CTL 0x002300F0 /* Reset Source: CORER */
1256 #define PF_SB_REM_DEV_CTL_DEST_EN_S 0
1257 #define PF_SB_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1258 #define PF0_FW_HLP_ARQBAH 0x000801C8 /* Reset Source: EMPR */
1259 #define PF0_FW_HLP_ARQBAH_ARQBAH_S 0
1260 #define PF0_FW_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1261 #define PF0_FW_HLP_ARQBAL 0x000800C8 /* Reset Source: EMPR */
1262 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_S 0
1263 #define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1265 #define PF0_FW_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1266 #define PF0_FW_HLP_ARQH 0x000803C8 /* Reset Source: EMPR */
1267 #define PF0_FW_HLP_ARQH_ARQH_S 0
1268 #define PF0_FW_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1269 #define PF0_FW_HLP_ARQLEN 0x000802C8 /* Reset Source: EMPR */
1270 #define PF0_FW_HLP_ARQLEN_ARQLEN_S 0
1271 #define PF0_FW_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1280 #define PF0_FW_HLP_ARQT 0x000804C8 /* Reset Source: EMPR */
1281 #define PF0_FW_HLP_ARQT_ARQT_S 0
1282 #define PF0_FW_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1283 #define PF0_FW_HLP_ATQBAH 0x00080148 /* Reset Source: EMPR */
1284 #define PF0_FW_HLP_ATQBAH_ATQBAH_S 0
1285 #define PF0_FW_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1286 #define PF0_FW_HLP_ATQBAL 0x00080048 /* Reset Source: EMPR */
1287 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_S 0
1288 #define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1290 #define PF0_FW_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1291 #define PF0_FW_HLP_ATQH 0x00080348 /* Reset Source: EMPR */
1292 #define PF0_FW_HLP_ATQH_ATQH_S 0
1293 #define PF0_FW_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1294 #define PF0_FW_HLP_ATQLEN 0x00080248 /* Reset Source: EMPR */
1295 #define PF0_FW_HLP_ATQLEN_ATQLEN_S 0
1296 #define PF0_FW_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1305 #define PF0_FW_HLP_ATQT 0x00080448 /* Reset Source: EMPR */
1306 #define PF0_FW_HLP_ATQT_ATQT_S 0
1307 #define PF0_FW_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1308 #define PF0_FW_PSM_ARQBAH 0x000801C4 /* Reset Source: EMPR */
1309 #define PF0_FW_PSM_ARQBAH_ARQBAH_S 0
1310 #define PF0_FW_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1311 #define PF0_FW_PSM_ARQBAL 0x000800C4 /* Reset Source: EMPR */
1312 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_S 0
1313 #define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1315 #define PF0_FW_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1316 #define PF0_FW_PSM_ARQH 0x000803C4 /* Reset Source: EMPR */
1317 #define PF0_FW_PSM_ARQH_ARQH_S 0
1318 #define PF0_FW_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1319 #define PF0_FW_PSM_ARQLEN 0x000802C4 /* Reset Source: EMPR */
1320 #define PF0_FW_PSM_ARQLEN_ARQLEN_S 0
1321 #define PF0_FW_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1330 #define PF0_FW_PSM_ARQT 0x000804C4 /* Reset Source: EMPR */
1331 #define PF0_FW_PSM_ARQT_ARQT_S 0
1332 #define PF0_FW_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1333 #define PF0_FW_PSM_ATQBAH 0x00080144 /* Reset Source: EMPR */
1334 #define PF0_FW_PSM_ATQBAH_ATQBAH_S 0
1335 #define PF0_FW_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1336 #define PF0_FW_PSM_ATQBAL 0x00080044 /* Reset Source: EMPR */
1337 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_S 0
1338 #define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_M MAKEMASK(0x3F, 0)
1340 #define PF0_FW_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1341 #define PF0_FW_PSM_ATQH 0x00080344 /* Reset Source: EMPR */
1342 #define PF0_FW_PSM_ATQH_ATQH_S 0
1343 #define PF0_FW_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1344 #define PF0_FW_PSM_ATQLEN 0x00080244 /* Reset Source: EMPR */
1345 #define PF0_FW_PSM_ATQLEN_ATQLEN_S 0
1346 #define PF0_FW_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1355 #define PF0_FW_PSM_ATQT 0x00080444 /* Reset Source: EMPR */
1356 #define PF0_FW_PSM_ATQT_ATQT_S 0
1357 #define PF0_FW_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1358 #define PF0_MBX_CPM_ARQBAH 0x0022E5D8 /* Reset Source: CORER */
1359 #define PF0_MBX_CPM_ARQBAH_ARQBAH_S 0
1360 #define PF0_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1361 #define PF0_MBX_CPM_ARQBAL 0x0022E5D4 /* Reset Source: CORER */
1362 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0
1363 #define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1365 #define PF0_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1366 #define PF0_MBX_CPM_ARQH 0x0022E5E0 /* Reset Source: CORER */
1367 #define PF0_MBX_CPM_ARQH_ARQH_S 0
1368 #define PF0_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1369 #define PF0_MBX_CPM_ARQLEN 0x0022E5DC /* Reset Source: PFR */
1370 #define PF0_MBX_CPM_ARQLEN_ARQLEN_S 0
1371 #define PF0_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1380 #define PF0_MBX_CPM_ARQT 0x0022E5E4 /* Reset Source: CORER */
1381 #define PF0_MBX_CPM_ARQT_ARQT_S 0
1382 #define PF0_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1383 #define PF0_MBX_CPM_ATQBAH 0x0022E5C4 /* Reset Source: CORER */
1384 #define PF0_MBX_CPM_ATQBAH_ATQBAH_S 0
1385 #define PF0_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1386 #define PF0_MBX_CPM_ATQBAL 0x0022E5C0 /* Reset Source: CORER */
1388 #define PF0_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1389 #define PF0_MBX_CPM_ATQH 0x0022E5CC /* Reset Source: CORER */
1390 #define PF0_MBX_CPM_ATQH_ATQH_S 0
1391 #define PF0_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1392 #define PF0_MBX_CPM_ATQLEN 0x0022E5C8 /* Reset Source: PFR */
1393 #define PF0_MBX_CPM_ATQLEN_ATQLEN_S 0
1394 #define PF0_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1403 #define PF0_MBX_CPM_ATQT 0x0022E5D0 /* Reset Source: CORER */
1404 #define PF0_MBX_CPM_ATQT_ATQT_S 0
1405 #define PF0_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1406 #define PF0_MBX_HLP_ARQBAH 0x0022E600 /* Reset Source: CORER */
1407 #define PF0_MBX_HLP_ARQBAH_ARQBAH_S 0
1408 #define PF0_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1409 #define PF0_MBX_HLP_ARQBAL 0x0022E5FC /* Reset Source: CORER */
1410 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0
1411 #define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1413 #define PF0_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1414 #define PF0_MBX_HLP_ARQH 0x0022E608 /* Reset Source: CORER */
1415 #define PF0_MBX_HLP_ARQH_ARQH_S 0
1416 #define PF0_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1417 #define PF0_MBX_HLP_ARQLEN 0x0022E604 /* Reset Source: PFR */
1418 #define PF0_MBX_HLP_ARQLEN_ARQLEN_S 0
1419 #define PF0_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1428 #define PF0_MBX_HLP_ARQT 0x0022E60C /* Reset Source: CORER */
1429 #define PF0_MBX_HLP_ARQT_ARQT_S 0
1430 #define PF0_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1431 #define PF0_MBX_HLP_ATQBAH 0x0022E5EC /* Reset Source: CORER */
1432 #define PF0_MBX_HLP_ATQBAH_ATQBAH_S 0
1433 #define PF0_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1434 #define PF0_MBX_HLP_ATQBAL 0x0022E5E8 /* Reset Source: CORER */
1436 #define PF0_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1437 #define PF0_MBX_HLP_ATQH 0x0022E5F4 /* Reset Source: CORER */
1438 #define PF0_MBX_HLP_ATQH_ATQH_S 0
1439 #define PF0_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1440 #define PF0_MBX_HLP_ATQLEN 0x0022E5F0 /* Reset Source: PFR */
1441 #define PF0_MBX_HLP_ATQLEN_ATQLEN_S 0
1442 #define PF0_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1451 #define PF0_MBX_HLP_ATQT 0x0022E5F8 /* Reset Source: CORER */
1452 #define PF0_MBX_HLP_ATQT_ATQT_S 0
1453 #define PF0_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1454 #define PF0_MBX_PSM_ARQBAH 0x0022E628 /* Reset Source: CORER */
1455 #define PF0_MBX_PSM_ARQBAH_ARQBAH_S 0
1456 #define PF0_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1457 #define PF0_MBX_PSM_ARQBAL 0x0022E624 /* Reset Source: CORER */
1458 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0
1459 #define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1461 #define PF0_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1462 #define PF0_MBX_PSM_ARQH 0x0022E630 /* Reset Source: CORER */
1463 #define PF0_MBX_PSM_ARQH_ARQH_S 0
1464 #define PF0_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1465 #define PF0_MBX_PSM_ARQLEN 0x0022E62C /* Reset Source: PFR */
1466 #define PF0_MBX_PSM_ARQLEN_ARQLEN_S 0
1467 #define PF0_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1476 #define PF0_MBX_PSM_ARQT 0x0022E634 /* Reset Source: CORER */
1477 #define PF0_MBX_PSM_ARQT_ARQT_S 0
1478 #define PF0_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1479 #define PF0_MBX_PSM_ATQBAH 0x0022E614 /* Reset Source: CORER */
1480 #define PF0_MBX_PSM_ATQBAH_ATQBAH_S 0
1481 #define PF0_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1482 #define PF0_MBX_PSM_ATQBAL 0x0022E610 /* Reset Source: CORER */
1484 #define PF0_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1485 #define PF0_MBX_PSM_ATQH 0x0022E61C /* Reset Source: CORER */
1486 #define PF0_MBX_PSM_ATQH_ATQH_S 0
1487 #define PF0_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1488 #define PF0_MBX_PSM_ATQLEN 0x0022E618 /* Reset Source: PFR */
1489 #define PF0_MBX_PSM_ATQLEN_ATQLEN_S 0
1490 #define PF0_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1499 #define PF0_MBX_PSM_ATQT 0x0022E620 /* Reset Source: CORER */
1500 #define PF0_MBX_PSM_ATQT_ATQT_S 0
1501 #define PF0_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1502 #define PF0_SB_CPM_ARQBAH 0x0022E650 /* Reset Source: CORER */
1503 #define PF0_SB_CPM_ARQBAH_ARQBAH_S 0
1504 #define PF0_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1505 #define PF0_SB_CPM_ARQBAL 0x0022E64C /* Reset Source: CORER */
1506 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_S 0
1507 #define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1509 #define PF0_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1510 #define PF0_SB_CPM_ARQH 0x0022E658 /* Reset Source: CORER */
1511 #define PF0_SB_CPM_ARQH_ARQH_S 0
1512 #define PF0_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1513 #define PF0_SB_CPM_ARQLEN 0x0022E654 /* Reset Source: PFR */
1514 #define PF0_SB_CPM_ARQLEN_ARQLEN_S 0
1515 #define PF0_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1524 #define PF0_SB_CPM_ARQT 0x0022E65C /* Reset Source: CORER */
1525 #define PF0_SB_CPM_ARQT_ARQT_S 0
1526 #define PF0_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1527 #define PF0_SB_CPM_ATQBAH 0x0022E63C /* Reset Source: CORER */
1528 #define PF0_SB_CPM_ATQBAH_ATQBAH_S 0
1529 #define PF0_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1530 #define PF0_SB_CPM_ATQBAL 0x0022E638 /* Reset Source: CORER */
1532 #define PF0_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1533 #define PF0_SB_CPM_ATQH 0x0022E644 /* Reset Source: CORER */
1534 #define PF0_SB_CPM_ATQH_ATQH_S 0
1535 #define PF0_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1536 #define PF0_SB_CPM_ATQLEN 0x0022E640 /* Reset Source: PFR */
1537 #define PF0_SB_CPM_ATQLEN_ATQLEN_S 0
1538 #define PF0_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1547 #define PF0_SB_CPM_ATQT 0x0022E648 /* Reset Source: CORER */
1548 #define PF0_SB_CPM_ATQT_ATQT_S 0
1549 #define PF0_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1550 #define PF0_SB_CPM_REM_DEV_CTL 0x002300F4 /* Reset Source: CORER */
1551 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_S 0
1552 #define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1553 #define PF0_SB_HLP_ARQBAH 0x002300D8 /* Reset Source: CORER */
1554 #define PF0_SB_HLP_ARQBAH_ARQBAH_S 0
1555 #define PF0_SB_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1556 #define PF0_SB_HLP_ARQBAL 0x002300D4 /* Reset Source: CORER */
1557 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_S 0
1558 #define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1560 #define PF0_SB_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1561 #define PF0_SB_HLP_ARQH 0x002300E0 /* Reset Source: CORER */
1562 #define PF0_SB_HLP_ARQH_ARQH_S 0
1563 #define PF0_SB_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1564 #define PF0_SB_HLP_ARQLEN 0x002300DC /* Reset Source: PFR */
1565 #define PF0_SB_HLP_ARQLEN_ARQLEN_S 0
1566 #define PF0_SB_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1575 #define PF0_SB_HLP_ARQT 0x002300E4 /* Reset Source: CORER */
1576 #define PF0_SB_HLP_ARQT_ARQT_S 0
1577 #define PF0_SB_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1578 #define PF0_SB_HLP_ATQBAH 0x002300C4 /* Reset Source: CORER */
1579 #define PF0_SB_HLP_ATQBAH_ATQBAH_S 0
1580 #define PF0_SB_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1581 #define PF0_SB_HLP_ATQBAL 0x002300C0 /* Reset Source: CORER */
1583 #define PF0_SB_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1584 #define PF0_SB_HLP_ATQH 0x002300CC /* Reset Source: CORER */
1585 #define PF0_SB_HLP_ATQH_ATQH_S 0
1586 #define PF0_SB_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1587 #define PF0_SB_HLP_ATQLEN 0x002300C8 /* Reset Source: PFR */
1588 #define PF0_SB_HLP_ATQLEN_ATQLEN_S 0
1589 #define PF0_SB_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1598 #define PF0_SB_HLP_ATQT 0x002300D0 /* Reset Source: CORER */
1599 #define PF0_SB_HLP_ATQT_ATQT_S 0
1600 #define PF0_SB_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1601 #define PF0_SB_HLP_REM_DEV_CTL 0x002300E8 /* Reset Source: CORER */
1602 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_S 0
1603 #define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1604 #define SB_REM_DEV_DEST(_i) (0x002300F8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
1606 #define SB_REM_DEV_DEST_DEST_S 0
1607 #define SB_REM_DEV_DEST_DEST_M MAKEMASK(0xF, 0)
1610 #define VF_MBX_ARQBAH(_VF) (0x0022B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1612 #define VF_MBX_ARQBAH_ARQBAH_S 0
1613 #define VF_MBX_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1614 #define VF_MBX_ARQBAL(_VF) (0x0022B400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1616 #define VF_MBX_ARQBAL_ARQBAL_LSB_S 0
1617 #define VF_MBX_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1619 #define VF_MBX_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1620 #define VF_MBX_ARQH(_VF) (0x0022C000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1622 #define VF_MBX_ARQH_ARQH_S 0
1623 #define VF_MBX_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1624 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
1626 #define VF_MBX_ARQLEN_ARQLEN_S 0
1627 #define VF_MBX_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1636 #define VF_MBX_ARQT(_VF) (0x0022C400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1638 #define VF_MBX_ARQT_ARQT_S 0
1639 #define VF_MBX_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1640 #define VF_MBX_ATQBAH(_VF) (0x0022A400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1642 #define VF_MBX_ATQBAH_ATQBAH_S 0
1643 #define VF_MBX_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1644 #define VF_MBX_ATQBAL(_VF) (0x0022A000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1647 #define VF_MBX_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1648 #define VF_MBX_ATQH(_VF) (0x0022AC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1650 #define VF_MBX_ATQH_ATQH_S 0
1651 #define VF_MBX_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1652 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
1654 #define VF_MBX_ATQLEN_ATQLEN_S 0
1655 #define VF_MBX_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1664 #define VF_MBX_ATQT(_VF) (0x0022B000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
1666 #define VF_MBX_ATQT_ATQT_S 0
1667 #define VF_MBX_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1668 #define VF_MBX_CPM_ARQBAH(_VF128) (0x0022D400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1670 #define VF_MBX_CPM_ARQBAH_ARQBAH_S 0
1671 #define VF_MBX_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1672 #define VF_MBX_CPM_ARQBAL(_VF128) (0x0022D200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1674 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_S 0
1675 #define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1677 #define VF_MBX_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1678 #define VF_MBX_CPM_ARQH(_VF128) (0x0022D800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1680 #define VF_MBX_CPM_ARQH_ARQH_S 0
1681 #define VF_MBX_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1682 #define VF_MBX_CPM_ARQLEN(_VF128) (0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1684 #define VF_MBX_CPM_ARQLEN_ARQLEN_S 0
1685 #define VF_MBX_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1694 #define VF_MBX_CPM_ARQT(_VF128) (0x0022DA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1696 #define VF_MBX_CPM_ARQT_ARQT_S 0
1697 #define VF_MBX_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1698 #define VF_MBX_CPM_ATQBAH(_VF128) (0x0022CA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1700 #define VF_MBX_CPM_ATQBAH_ATQBAH_S 0
1701 #define VF_MBX_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1702 #define VF_MBX_CPM_ATQBAL(_VF128) (0x0022C800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1705 #define VF_MBX_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1706 #define VF_MBX_CPM_ATQH(_VF128) (0x0022CE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1708 #define VF_MBX_CPM_ATQH_ATQH_S 0
1709 #define VF_MBX_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1710 #define VF_MBX_CPM_ATQLEN(_VF128) (0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1712 #define VF_MBX_CPM_ATQLEN_ATQLEN_S 0
1713 #define VF_MBX_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1722 #define VF_MBX_CPM_ATQT(_VF128) (0x0022D000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1724 #define VF_MBX_CPM_ATQT_ATQT_S 0
1725 #define VF_MBX_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1726 #define VF_MBX_HLP_ARQBAH(_VF16) (0x0022DD80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1728 #define VF_MBX_HLP_ARQBAH_ARQBAH_S 0
1729 #define VF_MBX_HLP_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1730 #define VF_MBX_HLP_ARQBAL(_VF16) (0x0022DD40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1732 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_S 0
1733 #define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1735 #define VF_MBX_HLP_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1736 #define VF_MBX_HLP_ARQH(_VF16) (0x0022DE00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1738 #define VF_MBX_HLP_ARQH_ARQH_S 0
1739 #define VF_MBX_HLP_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1740 #define VF_MBX_HLP_ARQLEN(_VF16) (0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1742 #define VF_MBX_HLP_ARQLEN_ARQLEN_S 0
1743 #define VF_MBX_HLP_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1752 #define VF_MBX_HLP_ARQT(_VF16) (0x0022DE40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1754 #define VF_MBX_HLP_ARQT_ARQT_S 0
1755 #define VF_MBX_HLP_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1756 #define VF_MBX_HLP_ATQBAH(_VF16) (0x0022DC40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1758 #define VF_MBX_HLP_ATQBAH_ATQBAH_S 0
1759 #define VF_MBX_HLP_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1760 #define VF_MBX_HLP_ATQBAL(_VF16) (0x0022DC00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1763 #define VF_MBX_HLP_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1764 #define VF_MBX_HLP_ATQH(_VF16) (0x0022DCC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1766 #define VF_MBX_HLP_ATQH_ATQH_S 0
1767 #define VF_MBX_HLP_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1768 #define VF_MBX_HLP_ATQLEN(_VF16) (0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1770 #define VF_MBX_HLP_ATQLEN_ATQLEN_S 0
1771 #define VF_MBX_HLP_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1780 #define VF_MBX_HLP_ATQT(_VF16) (0x0022DD00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1782 #define VF_MBX_HLP_ATQT_ATQT_S 0
1783 #define VF_MBX_HLP_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1784 #define VF_MBX_PSM_ARQBAH(_VF16) (0x0022E000 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1786 #define VF_MBX_PSM_ARQBAH_ARQBAH_S 0
1787 #define VF_MBX_PSM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1788 #define VF_MBX_PSM_ARQBAL(_VF16) (0x0022DFC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1790 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_S 0
1791 #define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1793 #define VF_MBX_PSM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1794 #define VF_MBX_PSM_ARQH(_VF16) (0x0022E080 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1796 #define VF_MBX_PSM_ARQH_ARQH_S 0
1797 #define VF_MBX_PSM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1798 #define VF_MBX_PSM_ARQLEN(_VF16) (0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1800 #define VF_MBX_PSM_ARQLEN_ARQLEN_S 0
1801 #define VF_MBX_PSM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1810 #define VF_MBX_PSM_ARQT(_VF16) (0x0022E0C0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1812 #define VF_MBX_PSM_ARQT_ARQT_S 0
1813 #define VF_MBX_PSM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1814 #define VF_MBX_PSM_ATQBAH(_VF16) (0x0022DEC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1816 #define VF_MBX_PSM_ATQBAH_ATQBAH_S 0
1817 #define VF_MBX_PSM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1818 #define VF_MBX_PSM_ATQBAL(_VF16) (0x0022DE80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1821 #define VF_MBX_PSM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1822 #define VF_MBX_PSM_ATQH(_VF16) (0x0022DF40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1824 #define VF_MBX_PSM_ATQH_ATQH_S 0
1825 #define VF_MBX_PSM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1826 #define VF_MBX_PSM_ATQLEN(_VF16) (0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: PFR */
1828 #define VF_MBX_PSM_ATQLEN_ATQLEN_S 0
1829 #define VF_MBX_PSM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1838 #define VF_MBX_PSM_ATQT(_VF16) (0x0022DF80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1840 #define VF_MBX_PSM_ATQT_ATQT_S 0
1841 #define VF_MBX_PSM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1842 #define VF_SB_CPM_ARQBAH(_VF128) (0x0022F400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1844 #define VF_SB_CPM_ARQBAH_ARQBAH_S 0
1845 #define VF_SB_CPM_ARQBAH_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1846 #define VF_SB_CPM_ARQBAL(_VF128) (0x0022F200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1848 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_S 0
1849 #define VF_SB_CPM_ARQBAL_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
1851 #define VF_SB_CPM_ARQBAL_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
1852 #define VF_SB_CPM_ARQH(_VF128) (0x0022F800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1854 #define VF_SB_CPM_ARQH_ARQH_S 0
1855 #define VF_SB_CPM_ARQH_ARQH_M MAKEMASK(0x3FF, 0)
1856 #define VF_SB_CPM_ARQLEN(_VF128) (0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1858 #define VF_SB_CPM_ARQLEN_ARQLEN_S 0
1859 #define VF_SB_CPM_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, 0)
1868 #define VF_SB_CPM_ARQT(_VF128) (0x0022FA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1870 #define VF_SB_CPM_ARQT_ARQT_S 0
1871 #define VF_SB_CPM_ARQT_ARQT_M MAKEMASK(0x3FF, 0)
1872 #define VF_SB_CPM_ATQBAH(_VF128) (0x0022EA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1874 #define VF_SB_CPM_ATQBAH_ATQBAH_S 0
1875 #define VF_SB_CPM_ATQBAH_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
1876 #define VF_SB_CPM_ATQBAL(_VF128) (0x0022E800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1879 #define VF_SB_CPM_ATQBAL_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
1880 #define VF_SB_CPM_ATQH(_VF128) (0x0022EE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1882 #define VF_SB_CPM_ATQH_ATQH_S 0
1883 #define VF_SB_CPM_ATQH_ATQH_M MAKEMASK(0x3FF, 0)
1884 #define VF_SB_CPM_ATQLEN(_VF128) (0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: PFR */
1886 #define VF_SB_CPM_ATQLEN_ATQLEN_S 0
1887 #define VF_SB_CPM_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, 0)
1896 #define VF_SB_CPM_ATQT(_VF128) (0x0022F000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1898 #define VF_SB_CPM_ATQT_ATQT_S 0
1899 #define VF_SB_CPM_ATQT_ATQT_M MAKEMASK(0x3FF, 0)
1900 #define VF_SB_CPM_REM_DEV_CTL 0x002300EC /* Reset Source: CORER */
1901 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_S 0
1902 #define VF_SB_CPM_REM_DEV_CTL_DEST_EN_M MAKEMASK(0xFFFF, 0)
1903 #define VP_MBX_CPM_PF_VF_CTRL(_VP128) (0x00231800 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1905 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_S 0
1906 #define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1907 #define VP_MBX_HLP_PF_VF_CTRL(_VP16) (0x00231A00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1909 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_S 0
1910 #define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1911 #define VP_MBX_PF_VF_CTRL(_VSI) (0x00230800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
1913 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_S 0
1914 #define VP_MBX_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1915 #define VP_MBX_PSM_PF_VF_CTRL(_VP16) (0x00231A40 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
1917 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_S 0
1918 #define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1919 #define VP_SB_CPM_PF_VF_CTRL(_VP128) (0x00231C00 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
1921 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_S 0
1922 #define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_M BIT(0)
1923 #define GL_DCB_TDSCP2TC_BLOCK_DIS 0x00049218 /* Reset Source: CORER */
1924 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_S 0
1925 #define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_M BIT(0)
1926 #define GL_DCB_TDSCP2TC_BLOCK_IPV4(_i) (0x00049018 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
1928 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_S 0
1929 #define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)
1930 #define GL_DCB_TDSCP2TC_BLOCK_IPV6(_i) (0x00049118 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
1932 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_S 0
1933 #define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)
1934 #define GLDCB_GENC 0x00083044 /* Reset Source: CORER */
1935 #define GLDCB_GENC_PCIRTT_S 0
1936 #define GLDCB_GENC_PCIRTT_M MAKEMASK(0xFFFF, 0)
1937 #define GLDCB_PRS_RETSTCC(_i) (0x002000B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1939 #define GLDCB_PRS_RETSTCC_BWSHARE_S 0
1940 #define GLDCB_PRS_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1943 #define GLDCB_PRS_RSPMC 0x00200160 /* Reset Source: CORER */
1944 #define GLDCB_PRS_RSPMC_RSPM_S 0
1945 #define GLDCB_PRS_RSPMC_RSPM_M MAKEMASK(0xFF, 0)
1947 #define GLDCB_PRS_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8)
1949 #define GLDCB_PRS_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10)
1951 #define GLDCB_PRS_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14)
1954 #define GLDCB_RETSTCC(_i) (0x00122140 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1956 #define GLDCB_RETSTCC_BWSHARE_S 0
1957 #define GLDCB_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1960 #define GLDCB_RETSTCS(_i) (0x001221C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1962 #define GLDCB_RETSTCS_CREDITS_S 0
1963 #define GLDCB_RETSTCS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0)
1964 #define GLDCB_RTC2PFC_RCB 0x00122100 /* Reset Source: CORER */
1965 #define GLDCB_RTC2PFC_RCB_TC2PFC_S 0
1966 #define GLDCB_RTC2PFC_RCB_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0)
1967 #define GLDCB_SWT_RETSTCC(_i) (0x0020A040 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
1969 #define GLDCB_SWT_RETSTCC_BWSHARE_S 0
1970 #define GLDCB_SWT_RETSTCC_BWSHARE_M MAKEMASK(0x7F, 0)
1973 #define GLDCB_TC2PFC 0x001D2694 /* Reset Source: CORER */
1974 #define GLDCB_TC2PFC_TC2PFC_S 0
1975 #define GLDCB_TC2PFC_TC2PFC_M MAKEMASK(0xFFFFFFFF, 0)
1976 #define GLDCB_TCB_MNG_SP 0x000AE12C /* Reset Source: CORER */
1977 #define GLDCB_TCB_MNG_SP_MNG_SP_S 0
1978 #define GLDCB_TCB_MNG_SP_MNG_SP_M BIT(0)
1979 #define GLDCB_TCB_TCLL_CFG 0x000AE134 /* Reset Source: CORER */
1980 #define GLDCB_TCB_TCLL_CFG_LLTC_S 0
1981 #define GLDCB_TCB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0)
1982 #define GLDCB_TCB_WB_SP 0x000AE310 /* Reset Source: CORER */
1983 #define GLDCB_TCB_WB_SP_WB_SP_S 0
1984 #define GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
1985 #define GLDCB_TCUPM_IMM_EN 0x000BC824 /* Reset Source: CORER */
1986 #define GLDCB_TCUPM_IMM_EN_IMM_EN_S 0
1987 #define GLDCB_TCUPM_IMM_EN_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
1988 #define GLDCB_TCUPM_LEGACY_TC 0x000BC828 /* Reset Source: CORER */
1989 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_S 0
1990 #define GLDCB_TCUPM_LEGACY_TC_LEGTC_M MAKEMASK(0xFFFFFFFF, 0)
1991 #define GLDCB_TCUPM_NO_EXCEED_DIS 0x000BC830 /* Reset Source: CORER */
1992 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_S 0
1993 #define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_M BIT(0)
1994 #define GLDCB_TCUPM_WB_DIS 0x000BC834 /* Reset Source: CORER */
1995 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_S 0
1996 #define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_M BIT(0)
1999 #define GLDCB_TFPFCI 0x0009949C /* Reset Source: CORER */
2000 #define GLDCB_TFPFCI_GLDCB_TFPFCI_S 0
2001 #define GLDCB_TFPFCI_GLDCB_TFPFCI_M MAKEMASK(0xFFFFFFFF, 0)
2002 #define GLDCB_TLPM_IMM_TCB 0x000A0190 /* Reset Source: CORER */
2003 #define GLDCB_TLPM_IMM_TCB_IMM_EN_S 0
2004 #define GLDCB_TLPM_IMM_TCB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
2005 #define GLDCB_TLPM_IMM_TCUPM 0x000A018C /* Reset Source: CORER */
2006 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_S 0
2007 #define GLDCB_TLPM_IMM_TCUPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
2008 #define GLDCB_TLPM_PCI_DM 0x000A0180 /* Reset Source: CORER */
2009 #define GLDCB_TLPM_PCI_DM_MONITOR_S 0
2010 #define GLDCB_TLPM_PCI_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2011 #define GLDCB_TLPM_PCI_DTHR 0x000A0184 /* Reset Source: CORER */
2012 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_S 0
2013 #define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_M MAKEMASK(0xFFF, 0)
2014 #define GLDCB_TPB_IMM_TLPM 0x00099468 /* Reset Source: CORER */
2015 #define GLDCB_TPB_IMM_TLPM_IMM_EN_S 0
2016 #define GLDCB_TPB_IMM_TLPM_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
2017 #define GLDCB_TPB_IMM_TPB 0x0009946C /* Reset Source: CORER */
2018 #define GLDCB_TPB_IMM_TPB_IMM_EN_S 0
2019 #define GLDCB_TPB_IMM_TPB_IMM_EN_M MAKEMASK(0xFFFFFFFF, 0)
2020 #define GLDCB_TPB_TCLL_CFG 0x00099464 /* Reset Source: CORER */
2021 #define GLDCB_TPB_TCLL_CFG_LLTC_S 0
2022 #define GLDCB_TPB_TCLL_CFG_LLTC_M MAKEMASK(0xFFFFFFFF, 0)
2023 #define GLTCB_BULK_DWRR_REG_QUANTA 0x000AE0E0 /* Reset Source: CORER */
2024 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_S 0
2025 #define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2026 #define GLTCB_BULK_DWRR_REG_SAT 0x000AE0F0 /* Reset Source: CORER */
2027 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_S 0
2028 #define GLTCB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2029 #define GLTCB_BULK_DWRR_WB_QUANTA 0x000AE0E4 /* Reset Source: CORER */
2030 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_S 0
2031 #define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2032 #define GLTCB_BULK_DWRR_WB_SAT 0x000AE0F4 /* Reset Source: CORER */
2033 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_S 0
2034 #define GLTCB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2035 #define GLTCB_CREDIT_EXP_CTL 0x000AE120 /* Reset Source: CORER */
2036 #define GLTCB_CREDIT_EXP_CTL_EN_S 0
2037 #define GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
2039 #define GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1)
2040 #define GLTCB_LL_DWRR_REG_QUANTA 0x000AE0E8 /* Reset Source: CORER */
2041 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_S 0
2042 #define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2043 #define GLTCB_LL_DWRR_REG_SAT 0x000AE0F8 /* Reset Source: CORER */
2044 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_S 0
2045 #define GLTCB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2046 #define GLTCB_LL_DWRR_WB_QUANTA 0x000AE0EC /* Reset Source: CORER */
2047 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_S 0
2048 #define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2049 #define GLTCB_LL_DWRR_WB_SAT 0x000AE0FC /* Reset Source: CORER */
2050 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_S 0
2051 #define GLTCB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2052 #define GLTCB_WB_RL 0x000AE238 /* Reset Source: CORER */
2053 #define GLTCB_WB_RL_PERIOD_S 0
2054 #define GLTCB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
2057 #define GLTPB_WB_RL 0x00099460 /* Reset Source: CORER */
2058 #define GLTPB_WB_RL_PERIOD_S 0
2059 #define GLTPB_WB_RL_PERIOD_M MAKEMASK(0xFFFF, 0)
2062 #define E800_PRTDCB_FCCFG 0x001E4640 /* Reset Source: GLOBR */
2064 #define E800_PRTDCB_FCCFG_TFCE_M MAKEMASK(0x3, 3)
2065 #define E800_PRTDCB_FCRTV 0x001E4600 /* Reset Source: GLOBR */
2066 #define E800_PRTDCB_FCRTV_FC_REFRESH_TH_S 0
2067 #define E800_PRTDCB_FCRTV_FC_REFRESH_TH_M MAKEMASK(0xFFFF, 0)
2068 #define E800_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */
2070 #define E800_PRTDCB_FCTTVN_TTV_2N_S 0
2071 #define E800_PRTDCB_FCTTVN_TTV_2N_M MAKEMASK(0xFFFF, 0)
2073 #define E800_PRTDCB_FCTTVN_TTV_2N_P1_M MAKEMASK(0xFFFF, 16)
2074 #define PRTDCB_GENC 0x00083000 /* Reset Source: CORER */
2076 #define PRTDCB_GENC_NUMTC_M MAKEMASK(0xF, 2)
2078 #define PRTDCB_GENC_FCOEUP_M MAKEMASK(0x7, 6)
2082 #define PRTDCB_GENC_PFCLDA_M MAKEMASK(0xFFFF, 16)
2083 #define PRTDCB_GENS 0x00083020 /* Reset Source: CORER */
2084 #define PRTDCB_GENS_DCBX_STATUS_S 0
2085 #define PRTDCB_GENS_DCBX_STATUS_M MAKEMASK(0x7, 0)
2086 #define PRTDCB_PRS_RETSC 0x002001A0 /* Reset Source: CORER */
2087 #define PRTDCB_PRS_RETSC_ETS_MODE_S 0
2088 #define PRTDCB_PRS_RETSC_ETS_MODE_M BIT(0)
2092 #define PRTDCB_PRS_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2093 #define PRTDCB_PRS_RPRRC 0x00200180 /* Reset Source: CORER */
2094 #define PRTDCB_PRS_RPRRC_BWSHARE_S 0
2095 #define PRTDCB_PRS_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0)
2098 #define PRTDCB_RETSC 0x001222A0 /* Reset Source: CORER */
2099 #define PRTDCB_RETSC_ETS_MODE_S 0
2100 #define PRTDCB_RETSC_ETS_MODE_M BIT(0)
2104 #define PRTDCB_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2105 #define PRTDCB_RPRRC 0x001220C0 /* Reset Source: CORER */
2106 #define PRTDCB_RPRRC_BWSHARE_S 0
2107 #define PRTDCB_RPRRC_BWSHARE_M MAKEMASK(0x3FF, 0)
2110 #define PRTDCB_RPRRS 0x001220E0 /* Reset Source: CORER */
2111 #define PRTDCB_RPRRS_CREDITS_S 0
2112 #define PRTDCB_RPRRS_CREDITS_M MAKEMASK(0xFFFFFFFF, 0)
2113 #define PRTDCB_RUP_TDPU 0x00040960 /* Reset Source: CORER */
2114 #define PRTDCB_RUP_TDPU_NOVLANUP_S 0
2115 #define PRTDCB_RUP_TDPU_NOVLANUP_M MAKEMASK(0x7, 0)
2116 #define PRTDCB_RUP2TC 0x001D2640 /* Reset Source: CORER */
2117 #define PRTDCB_RUP2TC_UP0TC_S 0
2118 #define PRTDCB_RUP2TC_UP0TC_M MAKEMASK(0x7, 0)
2120 #define PRTDCB_RUP2TC_UP1TC_M MAKEMASK(0x7, 3)
2122 #define PRTDCB_RUP2TC_UP2TC_M MAKEMASK(0x7, 6)
2124 #define PRTDCB_RUP2TC_UP3TC_M MAKEMASK(0x7, 9)
2126 #define PRTDCB_RUP2TC_UP4TC_M MAKEMASK(0x7, 12)
2128 #define PRTDCB_RUP2TC_UP5TC_M MAKEMASK(0x7, 15)
2130 #define PRTDCB_RUP2TC_UP6TC_M MAKEMASK(0x7, 18)
2132 #define PRTDCB_RUP2TC_UP7TC_M MAKEMASK(0x7, 21)
2133 #define PRTDCB_SWT_RETSC 0x0020A140 /* Reset Source: CORER */
2134 #define PRTDCB_SWT_RETSC_ETS_MODE_S 0
2135 #define PRTDCB_SWT_RETSC_ETS_MODE_M BIT(0)
2139 #define PRTDCB_SWT_RETSC_ETS_MAX_EXP_M MAKEMASK(0xF, 2)
2140 #define PRTDCB_TCB_DWRR_CREDITS 0x000AE000 /* Reset Source: CORER */
2141 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0
2142 #define PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2143 #define PRTDCB_TCB_DWRR_QUANTA 0x000AE020 /* Reset Source: CORER */
2144 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0
2145 #define PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2146 #define PRTDCB_TCB_DWRR_SAT 0x000AE040 /* Reset Source: CORER */
2147 #define PRTDCB_TCB_DWRR_SAT_SATURATION_S 0
2148 #define PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2149 #define PRTDCB_TCUPM_NO_EXCEED_DM 0x000BC3C0 /* Reset Source: CORER */
2150 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_S 0
2151 #define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2152 #define PRTDCB_TCUPM_REG_CM 0x000BC360 /* Reset Source: CORER */
2153 #define PRTDCB_TCUPM_REG_CM_MONITOR_S 0
2154 #define PRTDCB_TCUPM_REG_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2155 #define PRTDCB_TCUPM_REG_CTHR 0x000BC380 /* Reset Source: CORER */
2156 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_S 0
2157 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_M MAKEMASK(0x7FFF, 0)
2159 #define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_M MAKEMASK(0x7FFF, 15)
2160 #define PRTDCB_TCUPM_REG_DM 0x000BC3A0 /* Reset Source: CORER */
2161 #define PRTDCB_TCUPM_REG_DM_MONITOR_S 0
2162 #define PRTDCB_TCUPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2163 #define PRTDCB_TCUPM_REG_DTHR 0x000BC3E0 /* Reset Source: CORER */
2164 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_S 0
2165 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2167 #define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2168 #define PRTDCB_TCUPM_REG_PE_HB_DM 0x000BC400 /* Reset Source: CORER */
2169 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_S 0
2170 #define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2171 #define PRTDCB_TCUPM_REG_PE_HB_DTHR 0x000BC420 /* Reset Source: CORER */
2172 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_S 0
2173 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2175 #define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2176 #define PRTDCB_TCUPM_WAIT_PFC_CM 0x000BC440 /* Reset Source: CORER */
2177 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_S 0
2178 #define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2179 #define PRTDCB_TCUPM_WAIT_PFC_CTHR 0x000BC460 /* Reset Source: CORER */
2180 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_S 0
2181 #define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_M MAKEMASK(0x7FFF, 0)
2182 #define PRTDCB_TCUPM_WAIT_PFC_DM 0x000BC480 /* Reset Source: CORER */
2183 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_S 0
2184 #define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2185 #define PRTDCB_TCUPM_WAIT_PFC_DTHR 0x000BC4A0 /* Reset Source: CORER */
2186 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_S 0
2187 #define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2188 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM 0x000BC4C0 /* Reset Source: CORER */
2189 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_S 0
2190 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2191 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR 0x000BC4E0 /* Reset Source: CORER */
2192 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_S 0
2193 #define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2194 #define PRTDCB_TDPUC 0x00040940 /* Reset Source: CORER */
2195 #define PRTDCB_TDPUC_MAX_TXFRAME_S 0
2196 #define PRTDCB_TDPUC_MAX_TXFRAME_M MAKEMASK(0xFFFF, 0)
2221 #define PRTDCB_TFCS 0x001E4560 /* Reset Source: GLOBR */
2222 #define PRTDCB_TFCS_TXOFF_S 0
2223 #define PRTDCB_TFCS_TXOFF_M BIT(0)
2240 #define PRTDCB_TLPM_REG_DM 0x000A0000 /* Reset Source: CORER */
2241 #define PRTDCB_TLPM_REG_DM_MONITOR_S 0
2242 #define PRTDCB_TLPM_REG_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2243 #define PRTDCB_TLPM_REG_DTHR 0x000A0020 /* Reset Source: CORER */
2244 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_S 0
2245 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)
2247 #define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)
2248 #define PRTDCB_TLPM_WAIT_PFC_DM 0x000A0040 /* Reset Source: CORER */
2249 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_S 0
2250 #define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2251 #define PRTDCB_TLPM_WAIT_PFC_DTHR 0x000A0060 /* Reset Source: CORER */
2252 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_S 0
2253 #define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)
2254 #define PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
2256 #define PRTDCB_TPFCTS_PFCTIMER_S 0
2257 #define PRTDCB_TPFCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0)
2258 #define PRTDCB_TUP2TC 0x001D26C0 /* Reset Source: CORER */
2259 #define PRTDCB_TUP2TC_UP0TC_S 0
2260 #define PRTDCB_TUP2TC_UP0TC_M MAKEMASK(0x7, 0)
2262 #define PRTDCB_TUP2TC_UP1TC_M MAKEMASK(0x7, 3)
2264 #define PRTDCB_TUP2TC_UP2TC_M MAKEMASK(0x7, 6)
2266 #define PRTDCB_TUP2TC_UP3TC_M MAKEMASK(0x7, 9)
2268 #define PRTDCB_TUP2TC_UP4TC_M MAKEMASK(0x7, 12)
2270 #define PRTDCB_TUP2TC_UP5TC_M MAKEMASK(0x7, 15)
2272 #define PRTDCB_TUP2TC_UP6TC_M MAKEMASK(0x7, 18)
2274 #define PRTDCB_TUP2TC_UP7TC_M MAKEMASK(0x7, 21)
2275 #define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */
2276 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0
2277 #define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)
2279 #define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
2280 #define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
2282 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0
2283 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
2285 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
2287 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
2289 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)
2291 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)
2293 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)
2295 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)
2297 #define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)
2298 #define PRTDCB_TX_DSCP2UP_IPV6_LUT(_i) (0x00040AA0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */
2300 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_S 0
2301 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
2303 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
2305 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
2307 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)
2309 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)
2311 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)
2313 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)
2315 #define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)
2316 #define PRTTCB_BULK_DWRR_REG_CREDITS 0x000AE060 /* Reset Source: CORER */
2317 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0
2318 #define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2319 #define PRTTCB_BULK_DWRR_WB_CREDITS 0x000AE080 /* Reset Source: CORER */
2320 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0
2321 #define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2322 #define PRTTCB_CREDIT_EXP 0x000AE100 /* Reset Source: CORER */
2323 #define PRTTCB_CREDIT_EXP_EXPANSION_S 0
2324 #define PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
2325 #define PRTTCB_LL_DWRR_REG_CREDITS 0x000AE0A0 /* Reset Source: CORER */
2326 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
2327 #define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2328 #define PRTTCB_LL_DWRR_WB_CREDITS 0x000AE0C0 /* Reset Source: CORER */
2329 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
2330 #define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2331 #define TCDCB_TCUPM_WAIT_CM(_i) (0x000BC520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2333 #define TCDCB_TCUPM_WAIT_CM_MONITOR_S 0
2334 #define TCDCB_TCUPM_WAIT_CM_MONITOR_M MAKEMASK(0x7FFF, 0)
2335 #define TCDCB_TCUPM_WAIT_CTHR(_i) (0x000BC5A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2337 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_S 0
2338 #define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_M MAKEMASK(0x7FFF, 0)
2339 #define TCDCB_TCUPM_WAIT_DM(_i) (0x000BC620 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2341 #define TCDCB_TCUPM_WAIT_DM_MONITOR_S 0
2342 #define TCDCB_TCUPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2343 #define TCDCB_TCUPM_WAIT_DTHR(_i) (0x000BC6A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2345 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_S 0
2346 #define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2347 #define TCDCB_TCUPM_WAIT_PE_HB_DM(_i) (0x000BC720 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2349 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_S 0
2350 #define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)
2351 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR(_i) (0x000BC7A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2353 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_S 0
2354 #define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2355 #define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2357 #define TCDCB_TLPM_WAIT_DM_MONITOR_S 0
2358 #define TCDCB_TLPM_WAIT_DM_MONITOR_M MAKEMASK(0x7FFFF, 0)
2359 #define TCDCB_TLPM_WAIT_DTHR(_i) (0x000A0100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2361 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_S 0
2362 #define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_M MAKEMASK(0xFFF, 0)
2363 #define TCTCB_WB_RL_TC_CFG(_i) (0x000AE138 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2365 #define TCTCB_WB_RL_TC_CFG_TOKENS_S 0
2366 #define TCTCB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
2368 #define TCTCB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
2369 #define TCTCB_WB_RL_TC_STAT(_i) (0x000AE1B8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2371 #define TCTCB_WB_RL_TC_STAT_BUCKET_S 0
2372 #define TCTCB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
2373 #define TPB_BULK_DWRR_REG_QUANTA 0x00099340 /* Reset Source: CORER */
2374 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_S 0
2375 #define TPB_BULK_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2376 #define TPB_BULK_DWRR_REG_SAT 0x00099350 /* Reset Source: CORER */
2377 #define TPB_BULK_DWRR_REG_SAT_SATURATION_S 0
2378 #define TPB_BULK_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2379 #define TPB_BULK_DWRR_WB_QUANTA 0x00099344 /* Reset Source: CORER */
2380 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_S 0
2381 #define TPB_BULK_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2382 #define TPB_BULK_DWRR_WB_SAT 0x00099354 /* Reset Source: CORER */
2383 #define TPB_BULK_DWRR_WB_SAT_SATURATION_S 0
2384 #define TPB_BULK_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2385 #define TPB_GLDCB_TCB_WB_SP 0x0009966C /* Reset Source: CORER */
2386 #define TPB_GLDCB_TCB_WB_SP_WB_SP_S 0
2387 #define TPB_GLDCB_TCB_WB_SP_WB_SP_M BIT(0)
2388 #define TPB_GLTCB_CREDIT_EXP_CTL 0x00099664 /* Reset Source: CORER */
2389 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_S 0
2390 #define TPB_GLTCB_CREDIT_EXP_CTL_EN_M BIT(0)
2392 #define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_M MAKEMASK(0x1FF, 1)
2393 #define TPB_LL_DWRR_REG_QUANTA 0x00099348 /* Reset Source: CORER */
2394 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_S 0
2395 #define TPB_LL_DWRR_REG_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2396 #define TPB_LL_DWRR_REG_SAT 0x00099358 /* Reset Source: CORER */
2397 #define TPB_LL_DWRR_REG_SAT_SATURATION_S 0
2398 #define TPB_LL_DWRR_REG_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2399 #define TPB_LL_DWRR_WB_QUANTA 0x0009934C /* Reset Source: CORER */
2400 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_S 0
2401 #define TPB_LL_DWRR_WB_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2402 #define TPB_LL_DWRR_WB_SAT 0x0009935C /* Reset Source: CORER */
2403 #define TPB_LL_DWRR_WB_SAT_SATURATION_S 0
2404 #define TPB_LL_DWRR_WB_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2405 #define TPB_PRTDCB_TCB_DWRR_CREDITS 0x000991C0 /* Reset Source: CORER */
2406 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_S 0
2407 #define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2408 #define TPB_PRTDCB_TCB_DWRR_QUANTA 0x00099220 /* Reset Source: CORER */
2409 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_S 0
2410 #define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_M MAKEMASK(0x7FF, 0)
2411 #define TPB_PRTDCB_TCB_DWRR_SAT 0x00099260 /* Reset Source: CORER */
2412 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_S 0
2413 #define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_M MAKEMASK(0x1FFFF, 0)
2414 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS 0x000992A0 /* Reset Source: CORER */
2415 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0
2416 #define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2417 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS 0x000992C0 /* Reset Source: CORER */
2418 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0
2419 #define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2420 #define TPB_PRTTCB_CREDIT_EXP 0x00099644 /* Reset Source: CORER */
2421 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S 0
2422 #define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
2423 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS 0x00099300 /* Reset Source: CORER */
2424 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
2425 #define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2426 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */
2427 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
2428 #define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
2429 #define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2431 #define TPB_WB_RL_TC_CFG_TOKENS_S 0
2432 #define TPB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
2434 #define TPB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
2435 #define TPB_WB_RL_TC_STAT(_i) (0x000993E0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
2437 #define TPB_WB_RL_TC_STAT_BUCKET_S 0
2438 #define TPB_WB_RL_TC_STAT_BUCKET_M MAKEMASK(0x1FFFF, 0)
2439 #define E800_GL_ACLEXT_CDMD_L1SEL(_i) (0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2441 #define E800_GL_ACLEXT_CDMD_L1SEL_RX_SEL_S 0
2442 #define E800_GL_ACLEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2444 #define E800_GL_ACLEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2446 #define E800_GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2448 #define E800_GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2450 #define E800_GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2451 #define E800_GL_ACLEXT_CTLTBL_L2ADDR(_i) (0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2453 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2454 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2456 #define E800_GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2459 #define E800_GL_ACLEXT_CTLTBL_L2DATA(_i) (0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2461 #define E800_GL_ACLEXT_CTLTBL_L2DATA_DATA_S 0
2462 #define E800_GL_ACLEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2463 #define E800_GL_ACLEXT_DFLT_L2PRFL(_i) (0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2465 #define E800_GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2466 #define E800_GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2467 #define GL_ACLEXT_DFLT_L2PRFL_ACL(_i) (0x00393800 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2469 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_S 0
2470 #define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2471 #define E800_GL_ACLEXT_FLGS_L1SEL0_1(_i) (0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2473 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S 0
2474 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2476 #define E800_GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2477 #define E800_GL_ACLEXT_FLGS_L1SEL2_3(_i) (0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2479 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S 0
2480 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2482 #define E800_GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2483 #define E800_GL_ACLEXT_FLGS_L1TBL(_i) (0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2485 #define E800_GL_ACLEXT_FLGS_L1TBL_LSB_S 0
2486 #define E800_GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2488 #define E800_GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2489 #define E800_GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2491 #define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
2492 #define E800_GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2495 #define E800_GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2497 #define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
2498 #define E800_GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2501 #define E800_GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2503 #define E800_GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S 0
2504 #define E800_GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2507 #define E800_GL_ACLEXT_K2N_L2DATA(_i) (0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2509 #define E800_GL_ACLEXT_K2N_L2DATA_DATA0_S 0
2510 #define E800_GL_ACLEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2512 #define E800_GL_ACLEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2514 #define E800_GL_ACLEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2516 #define E800_GL_ACLEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2517 #define E800_GL_ACLEXT_L2_PMASK0(_i) (0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2519 #define E800_GL_ACLEXT_L2_PMASK0_BITMASK_S 0
2520 #define E800_GL_ACLEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2521 #define E800_GL_ACLEXT_L2_PMASK1(_i) (0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2523 #define E800_GL_ACLEXT_L2_PMASK1_BITMASK_S 0
2524 #define E800_GL_ACLEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2525 #define E800_GL_ACLEXT_L2_TMASK0(_i) (0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2527 #define E800_GL_ACLEXT_L2_TMASK0_BITMASK_S 0
2528 #define E800_GL_ACLEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2529 #define E800_GL_ACLEXT_L2_TMASK1(_i) (0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2531 #define E800_GL_ACLEXT_L2_TMASK1_BITMASK_S 0
2532 #define E800_GL_ACLEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2533 #define E800_GL_ACLEXT_L2BMP0_3(_i) (0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2535 #define E800_GL_ACLEXT_L2BMP0_3_BMP0_S 0
2536 #define E800_GL_ACLEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
2538 #define E800_GL_ACLEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
2540 #define E800_GL_ACLEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
2542 #define E800_GL_ACLEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
2543 #define E800_GL_ACLEXT_L2BMP4_7(_i) (0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2545 #define E800_GL_ACLEXT_L2BMP4_7_BMP4_S 0
2546 #define E800_GL_ACLEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
2548 #define E800_GL_ACLEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
2550 #define E800_GL_ACLEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
2552 #define E800_GL_ACLEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
2553 #define E800_GL_ACLEXT_L2PRTMOD(_i) (0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2555 #define E800_GL_ACLEXT_L2PRTMOD_XLT1_S 0
2556 #define E800_GL_ACLEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2558 #define E800_GL_ACLEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2559 #define E800_GL_ACLEXT_N2N_L2ADDR(_i) (0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2561 #define E800_GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S 0
2562 #define E800_GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2565 #define E800_GL_ACLEXT_N2N_L2DATA(_i) (0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2567 #define E800_GL_ACLEXT_N2N_L2DATA_DATA0_S 0
2568 #define E800_GL_ACLEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2570 #define E800_GL_ACLEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2572 #define E800_GL_ACLEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2574 #define E800_GL_ACLEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2575 #define E800_GL_ACLEXT_P2P_L1ADDR(_i) (0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2577 #define E800_GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S 0
2578 #define E800_GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2581 #define E800_GL_ACLEXT_P2P_L1DATA(_i) (0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2583 #define E800_GL_ACLEXT_P2P_L1DATA_DATA_S 0
2584 #define E800_GL_ACLEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2585 #define E800_GL_ACLEXT_PID_L2GKTYPE(_i) (0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2587 #define E800_GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2588 #define E800_GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2589 #define E800_GL_ACLEXT_PLVL_SEL(_i) (0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2591 #define E800_GL_ACLEXT_PLVL_SEL_PLVL_SEL_S 0
2592 #define E800_GL_ACLEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2593 #define E800_GL_ACLEXT_TCAM_L2ADDR(_i) (0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2595 #define E800_GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S 0
2596 #define E800_GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2599 #define E800_GL_ACLEXT_TCAM_L2DATALSB(_i) (0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2601 #define E800_GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S 0
2602 #define E800_GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2603 #define E800_GL_ACLEXT_TCAM_L2DATAMSB(_i) (0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2605 #define E800_GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2606 #define E800_GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2607 #define E800_GL_ACLEXT_XLT0_L1ADDR(_i) (0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2609 #define E800_GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S 0
2610 #define E800_GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2613 #define E800_GL_ACLEXT_XLT0_L1DATA(_i) (0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2615 #define E800_GL_ACLEXT_XLT0_L1DATA_DATA_S 0
2616 #define E800_GL_ACLEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2617 #define E800_GL_ACLEXT_XLT1_L2ADDR(_i) (0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2619 #define E800_GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S 0
2620 #define E800_GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2623 #define E800_GL_ACLEXT_XLT1_L2DATA(_i) (0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2625 #define E800_GL_ACLEXT_XLT1_L2DATA_DATA_S 0
2626 #define E800_GL_ACLEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2627 #define E800_GL_ACLEXT_XLT2_L2ADDR(_i) (0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2629 #define E800_GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S 0
2630 #define E800_GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2633 #define E800_GL_ACLEXT_XLT2_L2DATA(_i) (0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2635 #define E800_GL_ACLEXT_XLT2_L2DATA_DATA_S 0
2636 #define E800_GL_ACLEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2637 #define GL_PREEXT_CDMD_L1SEL(_i) (0x0020F054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2639 #define GL_PREEXT_CDMD_L1SEL_RX_SEL_S 0
2641 #define E800_GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2642 #define E830_GL_PREEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x3F, 0)
2645 #define E800_GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2646 #define E830_GL_PREEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x3F, 8)
2649 #define E800_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2650 #define E830_GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x3F, 16)
2653 #define E800_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2654 #define E830_GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x3F, 24)
2656 #define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2657 #define GL_PREEXT_CTLTBL_L2ADDR(_i) (0x0020F084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2659 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2660 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2662 #define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2665 #define GL_PREEXT_CTLTBL_L2DATA(_i) (0x0020F090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2667 #define GL_PREEXT_CTLTBL_L2DATA_DATA_S 0
2668 #define GL_PREEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2669 #define GL_PREEXT_DFLT_L2PRFL(_i) (0x0020F138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2671 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2672 #define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2673 #define GL_PREEXT_FLGS_L1SEL0_1(_i) (0x0020F06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2675 #define GL_PREEXT_FLGS_L1SEL0_1_FLS0_S 0
2677 #define E800_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2678 #define E830_GL_PREEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x3FF, 0)
2681 #define E800_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2682 #define E830_GL_PREEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x3FF, 16)
2683 #define GL_PREEXT_FLGS_L1SEL2_3(_i) (0x0020F078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2685 #define GL_PREEXT_FLGS_L1SEL2_3_FLS2_S 0
2687 #define E800_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2688 #define E830_GL_PREEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x3FF, 0)
2691 #define E800_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2692 #define E830_GL_PREEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x3FF, 16)
2693 #define GL_PREEXT_FLGS_L1TBL(_i) (0x0020F060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2695 #define GL_PREEXT_FLGS_L1TBL_LSB_S 0
2696 #define GL_PREEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2698 #define GL_PREEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2699 #define GL_PREEXT_FORCE_L1CDID(_i) (0x0020F018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2701 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0
2702 #define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2705 #define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2707 #define GL_PREEXT_FORCE_PID_STATIC_PID_S 0
2708 #define GL_PREEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2711 #define GL_PREEXT_K2N_L2ADDR(_i) (0x0020F144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2713 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_S 0
2714 #define GL_PREEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2717 #define GL_PREEXT_K2N_L2DATA(_i) (0x0020F150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2719 #define GL_PREEXT_K2N_L2DATA_DATA0_S 0
2720 #define GL_PREEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2722 #define GL_PREEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2724 #define GL_PREEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2726 #define GL_PREEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2727 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2729 #define GL_PREEXT_L2_PMASK0_BITMASK_S 0
2730 #define GL_PREEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2731 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2733 #define GL_PREEXT_L2_PMASK1_BITMASK_S 0
2734 #define GL_PREEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2735 #define GL_PREEXT_L2_TMASK0(_i) (0x0020F498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2737 #define GL_PREEXT_L2_TMASK0_BITMASK_S 0
2738 #define GL_PREEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2739 #define GL_PREEXT_L2_TMASK1(_i) (0x0020F4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2741 #define GL_PREEXT_L2_TMASK1_BITMASK_S 0
2742 #define GL_PREEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2743 #define GL_PREEXT_L2BMP0_3(_i) (0x0020F0A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2745 #define GL_PREEXT_L2BMP0_3_BMP0_S 0
2746 #define GL_PREEXT_L2BMP0_3_BMP0_M MAKEMASK(0xFF, 0)
2748 #define GL_PREEXT_L2BMP0_3_BMP1_M MAKEMASK(0xFF, 8)
2750 #define GL_PREEXT_L2BMP0_3_BMP2_M MAKEMASK(0xFF, 16)
2752 #define GL_PREEXT_L2BMP0_3_BMP3_M MAKEMASK(0xFF, 24)
2753 #define GL_PREEXT_L2BMP4_7(_i) (0x0020F0B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2755 #define GL_PREEXT_L2BMP4_7_BMP4_S 0
2756 #define GL_PREEXT_L2BMP4_7_BMP4_M MAKEMASK(0xFF, 0)
2758 #define GL_PREEXT_L2BMP4_7_BMP5_M MAKEMASK(0xFF, 8)
2760 #define GL_PREEXT_L2BMP4_7_BMP6_M MAKEMASK(0xFF, 16)
2762 #define GL_PREEXT_L2BMP4_7_BMP7_M MAKEMASK(0xFF, 24)
2763 #define GL_PREEXT_L2PRTMOD(_i) (0x0020F09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2765 #define GL_PREEXT_L2PRTMOD_XLT1_S 0
2766 #define GL_PREEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2768 #define GL_PREEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2769 #define GL_PREEXT_N2N_L2ADDR(_i) (0x0020F15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2771 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_S 0
2772 #define GL_PREEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2775 #define GL_PREEXT_N2N_L2DATA(_i) (0x0020F168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2777 #define GL_PREEXT_N2N_L2DATA_DATA0_S 0
2778 #define GL_PREEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2780 #define GL_PREEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2782 #define GL_PREEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2784 #define GL_PREEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2785 #define GL_PREEXT_P2P_L1ADDR(_i) (0x0020F024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2787 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_S 0
2788 #define GL_PREEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2791 #define GL_PREEXT_P2P_L1DATA(_i) (0x0020F030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2793 #define GL_PREEXT_P2P_L1DATA_DATA_S 0
2794 #define GL_PREEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2795 #define GL_PREEXT_PID_L2GKTYPE(_i) (0x0020F0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2797 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2798 #define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2799 #define GL_PREEXT_PLVL_SEL(_i) (0x0020F00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2801 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_S 0
2802 #define GL_PREEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
2803 #define GL_PREEXT_TCAM_L2ADDR(_i) (0x0020F114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2805 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_S 0
2806 #define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
2809 #define GL_PREEXT_TCAM_L2DATALSB(_i) (0x0020F120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2811 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_S 0
2812 #define GL_PREEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
2813 #define GL_PREEXT_TCAM_L2DATAMSB(_i) (0x0020F12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2815 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_S 0
2816 #define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
2817 #define GL_PREEXT_XLT0_L1ADDR(_i) (0x0020F03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2819 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_S 0
2820 #define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
2823 #define GL_PREEXT_XLT0_L1DATA(_i) (0x0020F048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2825 #define GL_PREEXT_XLT0_L1DATA_DATA_S 0
2826 #define GL_PREEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2827 #define GL_PREEXT_XLT1_L2ADDR(_i) (0x0020F0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2829 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_S 0
2830 #define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
2833 #define GL_PREEXT_XLT1_L2DATA(_i) (0x0020F0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2835 #define GL_PREEXT_XLT1_L2DATA_DATA_S 0
2836 #define GL_PREEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2837 #define GL_PREEXT_XLT2_L2ADDR(_i) (0x0020F0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2839 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_S 0
2840 #define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
2843 #define GL_PREEXT_XLT2_L2DATA(_i) (0x0020F0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2845 #define GL_PREEXT_XLT2_L2DATA_DATA_S 0
2846 #define GL_PREEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2847 #define GL_PSTEXT_CDMD_L1SEL(_i) (0x0020E054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2849 #define GL_PSTEXT_CDMD_L1SEL_RX_SEL_S 0
2851 #define E800_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x1F, 0)
2852 #define E830_GL_PSTEXT_CDMD_L1SEL_RX_SEL_M MAKEMASK(0x3F, 0)
2855 #define E800_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x1F, 8)
2856 #define E830_GL_PSTEXT_CDMD_L1SEL_TX_SEL_M MAKEMASK(0x3F, 8)
2859 #define E800_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x1F, 16)
2860 #define E830_GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M MAKEMASK(0x3F, 16)
2863 #define E800_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x1F, 24)
2864 #define E830_GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M MAKEMASK(0x3F, 24)
2866 #define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_M MAKEMASK(0x3, 30)
2867 #define GL_PSTEXT_CTLTBL_L2ADDR(_i) (0x0020E084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2869 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_S 0
2870 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_M MAKEMASK(0x7, 0)
2872 #define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_M MAKEMASK(0x7, 8)
2875 #define GL_PSTEXT_CTLTBL_L2DATA(_i) (0x0020E090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2877 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_S 0
2878 #define GL_PSTEXT_CTLTBL_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2879 #define GL_PSTEXT_DFLT_L2PRFL(_i) (0x0020E138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2881 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_S 0
2882 #define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_M MAKEMASK(0xFFFF, 0)
2883 #define GL_PSTEXT_FL15_BMPLSB(_i) (0x0020E480 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2885 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_S 0
2886 #define GL_PSTEXT_FL15_BMPLSB_BMPLSB_M MAKEMASK(0xFFFFFFFF, 0)
2887 #define GL_PSTEXT_FL15_BMPMSB(_i) (0x0020E48C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2889 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_S 0
2890 #define GL_PSTEXT_FL15_BMPMSB_BMPMSB_M MAKEMASK(0xFFFFFFFF, 0)
2891 #define GL_PSTEXT_FLGS_L1SEL0_1(_i) (0x0020E06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2893 #define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_S 0
2895 #define E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x1FF, 0)
2896 #define E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M MAKEMASK(0x3FF, 0)
2899 #define E800_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x1FF, 16)
2900 #define E830_GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M MAKEMASK(0x3FF, 16)
2901 #define GL_PSTEXT_FLGS_L1SEL2_3(_i) (0x0020E078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2903 #define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_S 0
2905 #define E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x1FF, 0)
2906 #define E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M MAKEMASK(0x3FF, 0)
2909 #define E800_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x1FF, 16)
2910 #define E830_GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M MAKEMASK(0x3FF, 16)
2911 #define GL_PSTEXT_FLGS_L1TBL(_i) (0x0020E060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2913 #define GL_PSTEXT_FLGS_L1TBL_LSB_S 0
2914 #define GL_PSTEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
2916 #define GL_PSTEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
2917 #define GL_PSTEXT_FORCE_L1CDID(_i) (0x0020E018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2919 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0
2920 #define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
2923 #define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2925 #define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0
2926 #define GL_PSTEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
2929 #define GL_PSTEXT_K2N_L2ADDR(_i) (0x0020E144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2931 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_S 0
2932 #define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_M MAKEMASK(0x7F, 0)
2935 #define GL_PSTEXT_K2N_L2DATA(_i) (0x0020E150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2937 #define GL_PSTEXT_K2N_L2DATA_DATA0_S 0
2938 #define GL_PSTEXT_K2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2940 #define GL_PSTEXT_K2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2942 #define GL_PSTEXT_K2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2944 #define GL_PSTEXT_K2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2945 #define GL_PSTEXT_L2_PMASK0(_i) (0x0020E0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2947 #define GL_PSTEXT_L2_PMASK0_BITMASK_S 0
2948 #define GL_PSTEXT_L2_PMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2949 #define GL_PSTEXT_L2_PMASK1(_i) (0x0020E108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2951 #define GL_PSTEXT_L2_PMASK1_BITMASK_S 0
2952 #define GL_PSTEXT_L2_PMASK1_BITMASK_M MAKEMASK(0xFFFF, 0)
2953 #define GL_PSTEXT_L2_TMASK0(_i) (0x0020E498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2955 #define GL_PSTEXT_L2_TMASK0_BITMASK_S 0
2956 #define GL_PSTEXT_L2_TMASK0_BITMASK_M MAKEMASK(0xFFFFFFFF, 0)
2957 #define GL_PSTEXT_L2_TMASK1(_i) (0x0020E4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2959 #define GL_PSTEXT_L2_TMASK1_BITMASK_S 0
2960 #define GL_PSTEXT_L2_TMASK1_BITMASK_M MAKEMASK(0xFF, 0)
2961 #define GL_PSTEXT_L2PRTMOD(_i) (0x0020E09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2963 #define GL_PSTEXT_L2PRTMOD_XLT1_S 0
2964 #define GL_PSTEXT_L2PRTMOD_XLT1_M MAKEMASK(0x3, 0)
2966 #define GL_PSTEXT_L2PRTMOD_XLT2_M MAKEMASK(0x3, 8)
2967 #define GL_PSTEXT_N2N_L2ADDR(_i) (0x0020E15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2969 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_S 0
2970 #define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_M MAKEMASK(0x3F, 0)
2973 #define GL_PSTEXT_N2N_L2DATA(_i) (0x0020E168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2975 #define GL_PSTEXT_N2N_L2DATA_DATA0_S 0
2976 #define GL_PSTEXT_N2N_L2DATA_DATA0_M MAKEMASK(0xFF, 0)
2978 #define GL_PSTEXT_N2N_L2DATA_DATA1_M MAKEMASK(0xFF, 8)
2980 #define GL_PSTEXT_N2N_L2DATA_DATA2_M MAKEMASK(0xFF, 16)
2982 #define GL_PSTEXT_N2N_L2DATA_DATA3_M MAKEMASK(0xFF, 24)
2983 #define GL_PSTEXT_P2P_L1ADDR(_i) (0x0020E024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2985 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_S 0
2986 #define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_M BIT(0)
2989 #define GL_PSTEXT_P2P_L1DATA(_i) (0x0020E030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2991 #define GL_PSTEXT_P2P_L1DATA_DATA_S 0
2992 #define GL_PSTEXT_P2P_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
2993 #define GL_PSTEXT_PID_L2GKTYPE(_i) (0x0020E0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2995 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_S 0
2996 #define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_M MAKEMASK(0x3, 0)
2997 #define GL_PSTEXT_PLVL_SEL(_i) (0x0020E00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
2999 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_S 0
3000 #define GL_PSTEXT_PLVL_SEL_PLVL_SEL_M BIT(0)
3001 #define GL_PSTEXT_PRFLM_CTRL(_i) (0x0020E474 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3003 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_S 0
3004 #define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_M MAKEMASK(0xFF, 0)
3009 #define GL_PSTEXT_PRFLM_DATA_0(_i) (0x0020E174 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3011 #define GL_PSTEXT_PRFLM_DATA_0_PROT_S 0
3012 #define GL_PSTEXT_PRFLM_DATA_0_PROT_M MAKEMASK(0xFF, 0)
3014 #define GL_PSTEXT_PRFLM_DATA_0_OFF_M MAKEMASK(0x1FF, 16)
3015 #define GL_PSTEXT_PRFLM_DATA_1(_i) (0x0020E274 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3017 #define GL_PSTEXT_PRFLM_DATA_1_PROT_S 0
3018 #define GL_PSTEXT_PRFLM_DATA_1_PROT_M MAKEMASK(0xFF, 0)
3020 #define GL_PSTEXT_PRFLM_DATA_1_OFF_M MAKEMASK(0x1FF, 16)
3021 #define GL_PSTEXT_PRFLM_DATA_2(_i) (0x0020E374 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3023 #define GL_PSTEXT_PRFLM_DATA_2_PROT_S 0
3024 #define GL_PSTEXT_PRFLM_DATA_2_PROT_M MAKEMASK(0xFF, 0)
3026 #define GL_PSTEXT_PRFLM_DATA_2_OFF_M MAKEMASK(0x1FF, 16)
3027 #define GL_PSTEXT_TCAM_L2ADDR(_i) (0x0020E114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3029 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_S 0
3030 #define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_M MAKEMASK(0x3FF, 0)
3033 #define GL_PSTEXT_TCAM_L2DATALSB(_i) (0x0020E120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3035 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_S 0
3036 #define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_M MAKEMASK(0xFFFFFFFF, 0)
3037 #define GL_PSTEXT_TCAM_L2DATAMSB(_i) (0x0020E12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3039 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_S 0
3040 #define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_M MAKEMASK(0xFF, 0)
3041 #define GL_PSTEXT_XLT0_L1ADDR(_i) (0x0020E03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3043 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_S 0
3044 #define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_M MAKEMASK(0xFF, 0)
3047 #define GL_PSTEXT_XLT0_L1DATA(_i) (0x0020E048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3049 #define GL_PSTEXT_XLT0_L1DATA_DATA_S 0
3050 #define GL_PSTEXT_XLT0_L1DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3051 #define GL_PSTEXT_XLT1_L2ADDR(_i) (0x0020E0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3053 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_S 0
3054 #define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_M MAKEMASK(0x7FF, 0)
3057 #define GL_PSTEXT_XLT1_L2DATA(_i) (0x0020E0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3059 #define GL_PSTEXT_XLT1_L2DATA_DATA_S 0
3060 #define GL_PSTEXT_XLT1_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3061 #define GL_PSTEXT_XLT2_L2ADDR(_i) (0x0020E0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3063 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_S 0
3064 #define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_M MAKEMASK(0x1FF, 0)
3067 #define GL_PSTEXT_XLT2_L2DATA(_i) (0x0020E0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3069 #define GL_PSTEXT_XLT2_L2DATA_DATA_S 0
3070 #define GL_PSTEXT_XLT2_L2DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3071 #define GLFLXP_PTYPE_TRANSLATION(_i) (0x0045C000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3073 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_S 0
3074 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_M MAKEMASK(0xFF, 0)
3076 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_M MAKEMASK(0xFF, 8)
3078 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_M MAKEMASK(0xFF, 16)
3080 #define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_M MAKEMASK(0xFF, 24)
3081 #define GLFLXP_RX_CMD_LX_PROT_IDX(_i) (0x0045C400 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3083 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0
3084 #define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0)
3086 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)
3088 #define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)
3090 #define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
3092 #define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
3093 #define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */
3095 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0
3096 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M MAKEMASK(0xFF, 0)
3098 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M MAKEMASK(0xFF, 8)
3100 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M MAKEMASK(0xFF, 16)
3102 #define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_M MAKEMASK(0xFF, 24)
3103 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...4 */ /* Reset Source: CORER */
3105 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0
3106 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M MAKEMASK(0x3F, 0)
3108 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M MAKEMASK(0x3F, 8)
3110 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M MAKEMASK(0x3F, 16)
3112 #define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M MAKEMASK(0x3F, 24)
3113 #define GLFLXP_RXDID_FLAGS1_OVERRIDE(_i) (0x0045D600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3115 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_S 0
3116 #define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_M MAKEMASK(0xF, 0)
3117 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045C800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3119 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
3120 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M MAKEMASK(0xFF, 0)
3122 #define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3124 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3125 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045C900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3127 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
3128 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M MAKEMASK(0xFF, 0)
3130 #define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3132 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3133 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045CA00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3135 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
3136 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M MAKEMASK(0xFF, 0)
3138 #define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3140 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3141 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045CB00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3143 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
3144 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M MAKEMASK(0xFF, 0)
3146 #define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3148 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3149 #define GLFLXP_RXDID_FLX_WRD_4(_i) (0x0045CC00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3151 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_S 0
3152 #define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_M MAKEMASK(0xFF, 0)
3154 #define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3156 #define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3157 #define GLFLXP_RXDID_FLX_WRD_5(_i) (0x0045CD00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3159 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_S 0
3160 #define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_M MAKEMASK(0xFF, 0)
3162 #define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
3164 #define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M MAKEMASK(0x3, 30)
3165 #define GLFLXP_TX_SCHED_CORRECT(_i, _j) (0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 */ /* Reset Source: CORER */
3167 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S 0
3168 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0)
3170 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8)
3172 #define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
3174 #define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24)
3175 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
3177 #define QRXFLXP_CNTXT_RXDID_IDX_S 0
3178 #define QRXFLXP_CNTXT_RXDID_IDX_M MAKEMASK(0x3F, 0)
3180 #define QRXFLXP_CNTXT_RXDID_PRIO_M MAKEMASK(0x7, 8)
3183 #define GL_FWSTS 0x00083048 /* Reset Source: POR */
3184 #define GL_FWSTS_FWS0B_S 0
3185 #define GL_FWSTS_FWS0B_M MAKEMASK(0xFF, 0)
3191 #define GL_FWSTS_FWS1B_M MAKEMASK(0xFF, 16)
3192 #define GL_TCVMLR_DRAIN_CNTR_CTL 0x000A21E0 /* Reset Source: CORER */
3193 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_S 0
3194 #define GL_TCVMLR_DRAIN_CNTR_CTL_OP_M BIT(0)
3196 #define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_M MAKEMASK(0x7, 1)
3198 #define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_M MAKEMASK(0x3FFF, 4)
3199 #define GL_TCVMLR_DRAIN_DONE_DEC 0x000A21A8 /* Reset Source: CORER */
3200 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_S 0
3201 #define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_M BIT(0)
3203 #define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_M MAKEMASK(0x1F, 1)
3205 #define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_M MAKEMASK(0xFF, 6)
3206 #define GL_TCVMLR_DRAIN_DONE_TCLAN(_i) (0x000A20A8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3208 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_S 0
3209 #define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_M MAKEMASK(0xFF, 0)
3210 #define GL_TCVMLR_DRAIN_DONE_TPB(_i) (0x000A2128 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
3212 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_S 0
3213 #define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_M MAKEMASK(0xFF, 0)
3214 #define GL_TCVMLR_DRAIN_MARKER 0x000A2008 /* Reset Source: CORER */
3215 #define GL_TCVMLR_DRAIN_MARKER_PORT_S 0
3216 #define GL_TCVMLR_DRAIN_MARKER_PORT_M MAKEMASK(0x7, 0)
3218 #define GL_TCVMLR_DRAIN_MARKER_TC_M MAKEMASK(0x1F, 3)
3219 #define GL_TCVMLR_ERR_STAT 0x000A2024 /* Reset Source: CORER */
3220 #define GL_TCVMLR_ERR_STAT_ERROR_S 0
3221 #define GL_TCVMLR_ERR_STAT_ERROR_M BIT(0)
3225 #define GL_TCVMLR_ERR_STAT_STAT_M MAKEMASK(0x7, 2)
3227 #define GL_TCVMLR_ERR_STAT_ENT_TYPE_M MAKEMASK(0x7, 5)
3229 #define GL_TCVMLR_ERR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 8)
3230 #define GL_TCVMLR_QCFG 0x000A2010 /* Reset Source: CORER */
3231 #define GL_TCVMLR_QCFG_QID_S 0
3232 #define GL_TCVMLR_QCFG_QID_M MAKEMASK(0x3FFF, 0)
3236 #define GL_TCVMLR_QCFG_PORT_M MAKEMASK(0x7, 15)
3238 #define GL_TCVMLR_QCFG_TC_M MAKEMASK(0x1F, 18)
3239 #define GL_TCVMLR_QCFG_RD 0x000A2014 /* Reset Source: CORER */
3240 #define GL_TCVMLR_QCFG_RD_QID_S 0
3241 #define GL_TCVMLR_QCFG_RD_QID_M MAKEMASK(0x3FFF, 0)
3243 #define GL_TCVMLR_QCFG_RD_PORT_M MAKEMASK(0x7, 14)
3245 #define GL_TCVMLR_QCFG_RD_TC_M MAKEMASK(0x1F, 17)
3246 #define GL_TCVMLR_QCNTR 0x000A200C /* Reset Source: CORER */
3247 #define GL_TCVMLR_QCNTR_CNTR_S 0
3248 #define GL_TCVMLR_QCNTR_CNTR_M MAKEMASK(0x7FFF, 0)
3249 #define GL_TCVMLR_QCTL 0x000A2004 /* Reset Source: CORER */
3250 #define GL_TCVMLR_QCTL_QID_S 0
3251 #define GL_TCVMLR_QCTL_QID_M MAKEMASK(0x3FFF, 0)
3254 #define GL_TCVMLR_REQ_STAT 0x000A2018 /* Reset Source: CORER */
3255 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_S 0
3256 #define GL_TCVMLR_REQ_STAT_ENT_TYPE_M MAKEMASK(0x7, 0)
3258 #define GL_TCVMLR_REQ_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3)
3262 #define GL_TCVMLR_REQ_STAT_WRITE_STATUS_M MAKEMASK(0x7, 18)
3263 #define GL_TCVMLR_STAT 0x000A201C /* Reset Source: CORER */
3264 #define GL_TCVMLR_STAT_ENT_TYPE_S 0
3265 #define GL_TCVMLR_STAT_ENT_TYPE_M MAKEMASK(0x7, 0)
3267 #define GL_TCVMLR_STAT_ENT_ID_M MAKEMASK(0x3FFF, 3)
3269 #define GL_TCVMLR_STAT_STATUS_M MAKEMASK(0x7, 17)
3270 #define GL_XLR_MARKER_TRIG_TCVMLR 0x000A2000 /* Reset Source: CORER */
3271 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_S 0
3272 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
3274 #define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
3276 #define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_M MAKEMASK(0x7, 12)
3278 #define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_M MAKEMASK(0x7, 16)
3279 #define GL_XLR_MARKER_TRIG_VMLR 0x00093804 /* Reset Source: CORER */
3280 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_S 0
3281 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
3283 #define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
3285 #define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_M MAKEMASK(0x7, 12)
3287 #define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_M MAKEMASK(0x7, 16)
3288 #define GLGEN_ANA_ABORT_PTYPE 0x0020C21C /* Reset Source: CORER */
3289 #define GLGEN_ANA_ABORT_PTYPE_ABORT_S 0
3290 #define GLGEN_ANA_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
3291 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT 0x0020C208 /* Reset Source: CORER */
3292 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
3293 #define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3294 #define GLGEN_ANA_CFG_CTRL 0x0020C104 /* Reset Source: CORER */
3295 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_S 0
3296 #define GLGEN_ANA_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
3298 #define GLGEN_ANA_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
3300 #define GLGEN_ANA_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
3302 #define GLGEN_ANA_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29)
3303 #define GLGEN_ANA_CFG_HTBL_LU_RESULT 0x0020C158 /* Reset Source: CORER */
3304 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_S 0
3305 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
3307 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
3309 #define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3310 #define GLGEN_ANA_CFG_LU_KEY(_i) (0x0020C14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3312 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_S 0
3313 #define GLGEN_ANA_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3314 #define GLGEN_ANA_CFG_RDDATA(_i) (0x0020C10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3316 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_S 0
3317 #define GLGEN_ANA_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3318 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT 0x0020C15C /* Reset Source: CORER */
3319 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_S 0
3320 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
3322 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
3324 #define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3325 #define GLGEN_ANA_CFG_WRDATA 0x0020C108 /* Reset Source: CORER */
3326 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_S 0
3327 #define GLGEN_ANA_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3328 #define GLGEN_ANA_DEF_PTYPE 0x0020C100 /* Reset Source: CORER */
3329 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_S 0
3330 #define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
3331 #define GLGEN_ANA_ERR_CTRL 0x0020C220 /* Reset Source: CORER */
3332 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_S 0
3333 #define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0)
3334 #define GLGEN_ANA_FLAG_MAP(_i) (0x0020C000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3336 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_S 0
3337 #define GLGEN_ANA_FLAG_MAP_FLAG_EN_M BIT(0)
3339 #define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1)
3340 #define GLGEN_ANA_INV_NODE_PTYPE 0x0020C210 /* Reset Source: CORER */
3341 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
3342 #define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
3343 #define GLGEN_ANA_INV_PTYPE_MARKER 0x0020C218 /* Reset Source: CORER */
3344 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
3345 #define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
3346 #define GLGEN_ANA_LAST_PROT_ID(_i) (0x0020C1E4 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */
3348 #define GLGEN_ANA_LAST_PROT_ID_EN_S 0
3349 #define GLGEN_ANA_LAST_PROT_ID_EN_M BIT(0)
3351 #define GLGEN_ANA_LAST_PROT_ID_PROT_ID_M MAKEMASK(0xFF, 1)
3352 #define GLGEN_ANA_NMPG_KEYMASK(_i) (0x0020C1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3354 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_S 0
3355 #define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3356 #define GLGEN_ANA_NMPG0_HASHKEY(_i) (0x0020C1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3358 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_S 0
3359 #define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3360 #define GLGEN_ANA_NO_HIT_PG_NM_PG 0x0020C204 /* Reset Source: CORER */
3361 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_S 0
3362 #define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0)
3363 #define GLGEN_ANA_OUT_OF_PKT 0x0020C200 /* Reset Source: CORER */
3364 #define GLGEN_ANA_OUT_OF_PKT_NPC_S 0
3365 #define GLGEN_ANA_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3366 #define GLGEN_ANA_P2P(_i) (0x0020C160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3368 #define GLGEN_ANA_P2P_TARGET_PROF_S 0
3369 #define GLGEN_ANA_P2P_TARGET_PROF_M MAKEMASK(0xF, 0)
3370 #define GLGEN_ANA_PG_KEYMASK(_i) (0x0020C1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3372 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_S 0
3373 #define GLGEN_ANA_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3374 #define GLGEN_ANA_PG0_HASHKEY(_i) (0x0020C1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3376 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_S 0
3377 #define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3378 #define GLGEN_ANA_PROFIL_CTRL 0x0020C1FC /* Reset Source: CORER */
3379 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
3380 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
3382 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
3384 #define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
3386 #define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
3388 #define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
3391 #define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */
3392 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0
3393 #define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
3394 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */
3395 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
3396 #define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
3397 #define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */
3398 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0
3399 #define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
3401 #define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
3403 #define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
3405 #define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_M MAKEMASK(0x7, 29)
3406 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT 0x0020D158 /* Reset Source: CORER */
3407 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_S 0
3408 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_HIT_M BIT(0)
3410 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)
3412 #define GLGEN_ANA_TX_CFG_HTBL_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3413 #define GLGEN_ANA_TX_CFG_LU_KEY(_i) (0x0020D14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
3415 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S 0
3416 #define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3417 #define GLGEN_ANA_TX_CFG_RDDATA(_i) (0x0020D10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3419 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0
3420 #define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3421 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */
3422 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
3423 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
3425 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
3427 #define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
3428 #define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */
3429 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S 0
3430 #define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
3431 #define GLGEN_ANA_TX_DEF_PTYPE 0x0020D100 /* Reset Source: CORER */
3432 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S 0
3433 #define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
3434 #define GLGEN_ANA_TX_DFD_PACE_OUT 0x0020D4CC /* Reset Source: CORER */
3435 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_S 0
3436 #define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M BIT(0)
3437 #define GLGEN_ANA_TX_ERR_CTRL 0x0020D220 /* Reset Source: CORER */
3438 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_S 0
3439 #define GLGEN_ANA_TX_ERR_CTRL_ERR_MASK_EN_M MAKEMASK(0xFFFFFFFF, 0)
3440 #define GLGEN_ANA_TX_FLAG_MAP(_i) (0x0020D000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
3442 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_S 0
3443 #define GLGEN_ANA_TX_FLAG_MAP_FLAG_EN_M BIT(0)
3445 #define GLGEN_ANA_TX_FLAG_MAP_EXT_FLAG_ID_M MAKEMASK(0x3F, 1)
3446 #define GLGEN_ANA_TX_INV_NODE_PTYPE 0x0020D210 /* Reset Source: CORER */
3447 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0
3448 #define GLGEN_ANA_TX_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)
3449 #define GLGEN_ANA_TX_INV_PROT_ID 0x0020D214 /* Reset Source: CORER */
3450 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_S 0
3451 #define GLGEN_ANA_TX_INV_PROT_ID_INV_PROT_ID_M MAKEMASK(0xFF, 0)
3452 #define GLGEN_ANA_TX_INV_PTYPE_MARKER 0x0020D218 /* Reset Source: CORER */
3453 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0
3454 #define GLGEN_ANA_TX_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)
3455 #define GLGEN_ANA_TX_NMPG_KEYMASK(_i) (0x0020D1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3457 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_S 0
3458 #define GLGEN_ANA_TX_NMPG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3459 #define GLGEN_ANA_TX_NMPG0_HASHKEY(_i) (0x0020D1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3461 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_S 0
3462 #define GLGEN_ANA_TX_NMPG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3463 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG 0x0020D204 /* Reset Source: CORER */
3464 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_S 0
3465 #define GLGEN_ANA_TX_NO_HIT_PG_NM_PG_NPC_M MAKEMASK(0xFF, 0)
3466 #define GLGEN_ANA_TX_P2P(_i) (0x0020D160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
3468 #define GLGEN_ANA_TX_P2P_TARGET_PROF_S 0
3469 #define GLGEN_ANA_TX_P2P_TARGET_PROF_M MAKEMASK(0xF, 0)
3470 #define GLGEN_ANA_TX_PG_KEYMASK(_i) (0x0020D1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3472 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_S 0
3473 #define GLGEN_ANA_TX_PG_KEYMASK_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3474 #define GLGEN_ANA_TX_PG0_HASHKEY(_i) (0x0020D1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
3476 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_S 0
3477 #define GLGEN_ANA_TX_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
3478 #define GLGEN_ANA_TX_PROFIL_CTRL 0x0020D1FC /* Reset Source: CORER */
3479 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
3480 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
3482 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
3484 #define GLGEN_ANA_TX_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
3486 #define GLGEN_ANA_TX_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
3488 #define GLGEN_ANA_TX_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
3491 #define GLGEN_ASSERT_HLP 0x000B81E4 /* Reset Source: POR */
3492 #define GLGEN_ASSERT_HLP_CORE_ON_RST_S 0
3493 #define GLGEN_ASSERT_HLP_CORE_ON_RST_M BIT(0)
3496 #define GLGEN_CLKSTAT 0x000B8184 /* Reset Source: POR */
3497 #define GLGEN_CLKSTAT_U_CLK_SPEED_S 0
3498 #define GLGEN_CLKSTAT_U_CLK_SPEED_M MAKEMASK(0x7, 0)
3500 #define GLGEN_CLKSTAT_L_CLK_SPEED_M MAKEMASK(0x7, 3)
3502 #define GLGEN_CLKSTAT_PSM_CLK_SPEED_M MAKEMASK(0x7, 6)
3504 #define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_M MAKEMASK(0x7, 9)
3506 #define GLGEN_CLKSTAT_UANA_CLK_SPEED_M MAKEMASK(0x7, 12)
3508 #define GLGEN_CLKSTAT_PE_CLK_SPEED_M MAKEMASK(0x7, 18)
3509 #define GLGEN_CLKSTAT_SRC 0x000B826C /* Reset Source: POR */
3510 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_S 0
3511 #define GLGEN_CLKSTAT_SRC_U_CLK_SRC_M MAKEMASK(0x3, 0)
3513 #define GLGEN_CLKSTAT_SRC_L_CLK_SRC_M MAKEMASK(0x3, 2)
3515 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M MAKEMASK(0x3, 4)
3517 #define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_M MAKEMASK(0x3, 6)
3519 #define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_M MAKEMASK(0xF, 8)
3520 #define GLGEN_ECC_ERR_INT_TOG_MASK_H 0x00093A00 /* Reset Source: CORER */
3521 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_S 0
3522 #define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)
3523 #define GLGEN_ECC_ERR_INT_TOG_MASK_L 0x000939FC /* Reset Source: CORER */
3524 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_S 0
3525 #define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)
3526 #define GLGEN_ECC_ERR_RST_MASK_H 0x000939F8 /* Reset Source: CORER */
3527 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_S 0
3528 #define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)
3529 #define GLGEN_ECC_ERR_RST_MASK_L 0x000939F4 /* Reset Source: CORER */
3530 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_S 0
3531 #define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)
3532 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: POR */
3534 #define GLGEN_GPIO_CTL_IN_VALUE_S 0
3535 #define GLGEN_GPIO_CTL_IN_VALUE_M BIT(0)
3547 #define GLGEN_GPIO_CTL_PIN_FUNC_M MAKEMASK(0xF, 8)
3549 #define GLGEN_GPIO_CTL_INT_MODE_M MAKEMASK(0x3, 12)
3550 #define GLGEN_MARKER_COUNT 0x000939E8 /* Reset Source: CORER */
3551 #define GLGEN_MARKER_COUNT_MARKER_COUNT_S 0
3552 #define GLGEN_MARKER_COUNT_MARKER_COUNT_M MAKEMASK(0xFF, 0)
3555 #define GLGEN_RSTAT 0x000B8188 /* Reset Source: POR */
3556 #define GLGEN_RSTAT_DEVSTATE_S 0
3557 #define GLGEN_RSTAT_DEVSTATE_M MAKEMASK(0x3, 0)
3559 #define GLGEN_RSTAT_RESET_TYPE_M MAKEMASK(0x3, 2)
3561 #define GLGEN_RSTAT_CORERCNT_M MAKEMASK(0x3, 4)
3563 #define GLGEN_RSTAT_GLOBRCNT_M MAKEMASK(0x3, 6)
3565 #define GLGEN_RSTAT_EMPRCNT_M MAKEMASK(0x3, 8)
3567 #define GLGEN_RSTAT_TIME_TO_RST_M MAKEMASK(0x3F, 10)
3574 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
3575 #define GLGEN_RSTCTL_GRSTDEL_S 0
3576 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, 0)
3583 #define GLGEN_RTRIG 0x000B8190 /* Reset Source: CORER */
3584 #define GLGEN_RTRIG_CORER_S 0
3585 #define GLGEN_RTRIG_CORER_M BIT(0)
3590 #define GLGEN_STAT 0x000B612C /* Reset Source: POR */
3591 #define GLGEN_STAT_RSVD4FW_S 0
3592 #define GLGEN_STAT_RSVD4FW_M MAKEMASK(0xFF, 0)
3593 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3595 #define GLGEN_VFLRSTAT_VFLRS_S 0
3596 #define GLGEN_VFLRSTAT_VFLRS_M MAKEMASK(0xFFFFFFFF, 0)
3597 #define GLGEN_XLR_MSK2HLP_RDY 0x000939F0 /* Reset Source: CORER */
3598 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_S 0
3599 #define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_M BIT(0)
3600 #define GLGEN_XLR_TRNS_WAIT_COUNT 0x000939EC /* Reset Source: CORER */
3601 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_S 0
3602 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_M MAKEMASK(0x1F, 0)
3604 #define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_M MAKEMASK(0xFF, 8)
3605 #define GLVFGEN_TIMER 0x000B8214 /* Reset Source: POR */
3606 #define GLVFGEN_TIMER_GTIME_S 0
3607 #define GLVFGEN_TIMER_GTIME_M MAKEMASK(0xFFFFFFFF, 0)
3608 #define PFGEN_CTRL 0x00091000 /* Reset Source: CORER */
3609 #define PFGEN_CTRL_PFSWR_S 0
3610 #define PFGEN_CTRL_PFSWR_M BIT(0)
3611 #define PFGEN_DRUN 0x00091180 /* Reset Source: CORER */
3612 #define PFGEN_DRUN_DRVUNLD_S 0
3613 #define PFGEN_DRUN_DRVUNLD_M BIT(0)
3614 #define PFGEN_PFRSTAT 0x00091080 /* Reset Source: CORER */
3615 #define PFGEN_PFRSTAT_PFRD_S 0
3616 #define PFGEN_PFRSTAT_PFRD_M BIT(0)
3617 #define PFGEN_PORTNUM 0x001D2400 /* Reset Source: CORER */
3618 #define PFGEN_PORTNUM_PORT_NUM_S 0
3619 #define PFGEN_PORTNUM_PORT_NUM_M MAKEMASK(0x7, 0)
3620 #define PFGEN_STATE 0x00088000 /* Reset Source: CORER */
3621 #define PFGEN_STATE_PFPEEN_S 0
3622 #define PFGEN_STATE_PFPEEN_M BIT(0)
3629 #define PRT_TCVMLR_DRAIN_CNTR 0x000A21C0 /* Reset Source: CORER */
3630 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_S 0
3631 #define PRT_TCVMLR_DRAIN_CNTR_CNTR_M MAKEMASK(0x3FFF, 0)
3632 #define PRTGEN_CNF 0x000B8120 /* Reset Source: POR */
3633 #define PRTGEN_CNF_PORT_DIS_S 0
3634 #define PRTGEN_CNF_PORT_DIS_M BIT(0)
3639 #define PRTGEN_CNF2 0x000B8160 /* Reset Source: POR */
3640 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_S 0
3641 #define PRTGEN_CNF2_ACTIVATE_PORT_LINK_M BIT(0)
3642 #define PRTGEN_CNF3 0x000B8280 /* Reset Source: POR */
3643 #define PRTGEN_CNF3_PORT_STAGERING_EN_S 0
3644 #define PRTGEN_CNF3_PORT_STAGERING_EN_M BIT(0)
3645 #define PRTGEN_STATUS 0x000B8100 /* Reset Source: POR */
3646 #define PRTGEN_STATUS_PORT_VALID_S 0
3647 #define PRTGEN_STATUS_PORT_VALID_M BIT(0)
3650 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: VFR */
3652 #define VFGEN_RSTAT_VFR_STATE_S 0
3653 #define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, 0)
3654 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3656 #define VPGEN_VFRSTAT_VFRD_S 0
3657 #define VPGEN_VFRSTAT_VFRD_M BIT(0)
3658 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
3660 #define VPGEN_VFRTRIG_VFSWR_S 0
3661 #define VPGEN_VFRTRIG_VFSWR_M BIT(0)
3662 #define VSIGEN_RSTAT(_VSI) (0x00092800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
3664 #define VSIGEN_RSTAT_VMRD_S 0
3665 #define VSIGEN_RSTAT_VMRD_M BIT(0)
3666 #define VSIGEN_RTRIG(_VSI) (0x00091800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
3668 #define VSIGEN_RTRIG_VMSWR_S 0
3669 #define VSIGEN_RTRIG_VMSWR_M BIT(0)
3670 #define GLHMC_APBVTINUSEBASE(_i) (0x00524A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3672 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_S 0
3673 #define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)
3674 #define GLHMC_CEQPART(_i) (0x005031C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3676 #define GLHMC_CEQPART_PMCEQBASE_S 0
3677 #define GLHMC_CEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0)
3679 #define GLHMC_CEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16)
3680 #define GLHMC_DBCQMAX 0x005220F0 /* Reset Source: CORER */
3681 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_S 0
3682 #define GLHMC_DBCQMAX_GLHMC_DBCQMAX_M MAKEMASK(0xFFFFF, 0)
3683 #define GLHMC_DBCQPART(_i) (0x00503180 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3685 #define GLHMC_DBCQPART_PMDBCQBASE_S 0
3686 #define GLHMC_DBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0)
3688 #define GLHMC_DBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16)
3689 #define GLHMC_DBQPMAX 0x005220EC /* Reset Source: CORER */
3690 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_S 0
3691 #define GLHMC_DBQPMAX_GLHMC_DBQPMAX_M MAKEMASK(0x7FFFF, 0)
3692 #define GLHMC_DBQPPART(_i) (0x005044C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3694 #define GLHMC_DBQPPART_PMDBQPBASE_S 0
3695 #define GLHMC_DBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0)
3697 #define GLHMC_DBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16)
3698 #define GLHMC_FSIAVBASE(_i) (0x00525600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3700 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_S 0
3701 #define GLHMC_FSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0)
3702 #define GLHMC_FSIAVCNT(_i) (0x00525700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3704 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_S 0
3705 #define GLHMC_FSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0)
3706 #define GLHMC_FSIAVMAX 0x00522068 /* Reset Source: CORER */
3707 #define GLHMC_FSIAVMAX_PMFSIAVMAX_S 0
3708 #define GLHMC_FSIAVMAX_PMFSIAVMAX_M MAKEMASK(0x3FFFF, 0)
3709 #define GLHMC_FSIAVOBJSZ 0x00522064 /* Reset Source: CORER */
3710 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S 0
3711 #define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M MAKEMASK(0xF, 0)
3712 #define GLHMC_FSIMCBASE(_i) (0x00526000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3714 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_S 0
3715 #define GLHMC_FSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0)
3716 #define GLHMC_FSIMCCNT(_i) (0x00526100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3718 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_S 0
3719 #define GLHMC_FSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0)
3720 #define GLHMC_FSIMCMAX 0x00522060 /* Reset Source: CORER */
3721 #define GLHMC_FSIMCMAX_PMFSIMCMAX_S 0
3722 #define GLHMC_FSIMCMAX_PMFSIMCMAX_M MAKEMASK(0x3FFF, 0)
3723 #define GLHMC_FSIMCOBJSZ 0x0052205C /* Reset Source: CORER */
3724 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S 0
3725 #define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_M MAKEMASK(0xF, 0)
3726 #define GLHMC_FWPDINV 0x0052207C /* Reset Source: CORER */
3727 #define GLHMC_FWPDINV_PMSDIDX_S 0
3728 #define GLHMC_FWPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
3732 #define GLHMC_FWPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
3733 #define GLHMC_FWPDINV_FPMAT 0x0010207C /* Reset Source: CORER */
3734 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_S 0
3735 #define GLHMC_FWPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
3739 #define GLHMC_FWPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
3740 #define GLHMC_FWSDDATAHIGH 0x00522078 /* Reset Source: CORER */
3741 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0
3742 #define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
3743 #define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */
3744 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
3745 #define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
3746 #define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */
3747 #define GLHMC_FWSDDATALOW_PMSDVALID_S 0
3748 #define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)
3752 #define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
3754 #define GLHMC_FWSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
3755 #define GLHMC_FWSDDATALOW_FPMAT 0x00102074 /* Reset Source: CORER */
3756 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_S 0
3757 #define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
3761 #define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
3763 #define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
3764 #define GLHMC_PEARPBASE(_i) (0x00524800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3766 #define GLHMC_PEARPBASE_FPMPEARPBASE_S 0
3767 #define GLHMC_PEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0)
3768 #define GLHMC_PEARPCNT(_i) (0x00524900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3770 #define GLHMC_PEARPCNT_FPMPEARPCNT_S 0
3771 #define GLHMC_PEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3772 #define GLHMC_PEARPMAX 0x00522038 /* Reset Source: CORER */
3773 #define GLHMC_PEARPMAX_PMPEARPMAX_S 0
3774 #define GLHMC_PEARPMAX_PMPEARPMAX_M MAKEMASK(0x1FFFF, 0)
3775 #define GLHMC_PEARPOBJSZ 0x00522034 /* Reset Source: CORER */
3776 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S 0
3777 #define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_M MAKEMASK(0x7, 0)
3778 #define GLHMC_PECQBASE(_i) (0x00524200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3780 #define GLHMC_PECQBASE_FPMPECQBASE_S 0
3781 #define GLHMC_PECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0)
3782 #define GLHMC_PECQCNT(_i) (0x00524300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3784 #define GLHMC_PECQCNT_FPMPECQCNT_S 0
3785 #define GLHMC_PECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0)
3786 #define GLHMC_PECQOBJSZ 0x00522020 /* Reset Source: CORER */
3787 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_S 0
3788 #define GLHMC_PECQOBJSZ_PMPECQOBJSZ_M MAKEMASK(0xF, 0)
3789 #define GLHMC_PEHDRBASE(_i) (0x00526200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3791 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S 0
3792 #define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0)
3793 #define GLHMC_PEHDRCNT(_i) (0x00526300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3795 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S 0
3796 #define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0)
3797 #define GLHMC_PEHDRMAX 0x00522008 /* Reset Source: CORER */
3798 #define GLHMC_PEHDRMAX_PMPEHDRMAX_S 0
3799 #define GLHMC_PEHDRMAX_PMPEHDRMAX_M MAKEMASK(0x7FFFF, 0)
3801 #define GLHMC_PEHDRMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3802 #define GLHMC_PEHDROBJSZ 0x00522004 /* Reset Source: CORER */
3803 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S 0
3804 #define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_M MAKEMASK(0xF, 0)
3806 #define GLHMC_PEHDROBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3807 #define GLHMC_PEHTCNT(_i) (0x00524700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3809 #define GLHMC_PEHTCNT_FPMPEHTCNT_S 0
3810 #define GLHMC_PEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
3811 #define GLHMC_PEHTCNT_FPMAT(_i) (0x00104700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3813 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_S 0
3814 #define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
3815 #define GLHMC_PEHTEBASE(_i) (0x00524600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3817 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_S 0
3818 #define GLHMC_PEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
3819 #define GLHMC_PEHTEBASE_FPMAT(_i) (0x00104600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3821 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_S 0
3822 #define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
3823 #define GLHMC_PEHTEOBJSZ 0x0052202C /* Reset Source: CORER */
3824 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S 0
3825 #define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0)
3826 #define GLHMC_PEHTEOBJSZ_FPMAT 0x0010202C /* Reset Source: CORER */
3827 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_S 0
3828 #define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_M MAKEMASK(0xF, 0)
3829 #define GLHMC_PEHTMAX 0x00522030 /* Reset Source: CORER */
3830 #define GLHMC_PEHTMAX_PMPEHTMAX_S 0
3831 #define GLHMC_PEHTMAX_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0)
3832 #define GLHMC_PEHTMAX_FPMAT 0x00102030 /* Reset Source: CORER */
3833 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_S 0
3834 #define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_M MAKEMASK(0x1FFFFF, 0)
3835 #define GLHMC_PEMDBASE(_i) (0x00526400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3837 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_S 0
3838 #define GLHMC_PEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0)
3839 #define GLHMC_PEMDCNT(_i) (0x00526500 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3841 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_S 0
3842 #define GLHMC_PEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0)
3843 #define GLHMC_PEMDMAX 0x00522010 /* Reset Source: CORER */
3844 #define GLHMC_PEMDMAX_PMPEMDMAX_S 0
3845 #define GLHMC_PEMDMAX_PMPEMDMAX_M MAKEMASK(0xFFFFFF, 0)
3847 #define GLHMC_PEMDMAX_RSVD_M MAKEMASK(0xFF, 24)
3848 #define GLHMC_PEMDOBJSZ 0x0052200C /* Reset Source: CORER */
3849 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_S 0
3850 #define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_M MAKEMASK(0xF, 0)
3852 #define GLHMC_PEMDOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3853 #define GLHMC_PEMRBASE(_i) (0x00524C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3855 #define GLHMC_PEMRBASE_FPMPEMRBASE_S 0
3856 #define GLHMC_PEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
3857 #define GLHMC_PEMRCNT(_i) (0x00524D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3859 #define GLHMC_PEMRCNT_FPMPEMRSZ_S 0
3860 #define GLHMC_PEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
3861 #define GLHMC_PEMRMAX 0x00522040 /* Reset Source: CORER */
3862 #define GLHMC_PEMRMAX_PMPEMRMAX_S 0
3863 #define GLHMC_PEMRMAX_PMPEMRMAX_M MAKEMASK(0x7FFFFF, 0)
3864 #define GLHMC_PEMROBJSZ 0x0052203C /* Reset Source: CORER */
3865 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_S 0
3866 #define GLHMC_PEMROBJSZ_PMPEMROBJSZ_M MAKEMASK(0xF, 0)
3867 #define GLHMC_PEOOISCBASE(_i) (0x00526600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3869 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S 0
3870 #define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
3871 #define GLHMC_PEOOISCCNT(_i) (0x00526700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3873 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S 0
3874 #define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
3875 #define GLHMC_PEOOISCFFLBASE(_i) (0x00526C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3877 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
3878 #define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
3879 #define GLHMC_PEOOISCFFLCNT_PMAT(_i) (0x00526D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3881 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_S 0
3882 #define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3883 #define GLHMC_PEOOISCFFLMAX 0x005220A4 /* Reset Source: CORER */
3884 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S 0
3885 #define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_M MAKEMASK(0x7FFFF, 0)
3887 #define GLHMC_PEOOISCFFLMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3888 #define GLHMC_PEOOISCMAX 0x00522018 /* Reset Source: CORER */
3889 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_S 0
3890 #define GLHMC_PEOOISCMAX_PMPEOOISCMAX_M MAKEMASK(0x7FFFF, 0)
3892 #define GLHMC_PEOOISCMAX_RSVD_M MAKEMASK(0x1FFF, 19)
3893 #define GLHMC_PEOOISCOBJSZ 0x00522014 /* Reset Source: CORER */
3894 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S 0
3895 #define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_M MAKEMASK(0xF, 0)
3897 #define GLHMC_PEOOISCOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3898 #define GLHMC_PEPBLBASE(_i) (0x00525800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3900 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_S 0
3901 #define GLHMC_PEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0)
3902 #define GLHMC_PEPBLCNT(_i) (0x00525900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3904 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_S 0
3905 #define GLHMC_PEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3906 #define GLHMC_PEPBLMAX 0x0052206C /* Reset Source: CORER */
3907 #define GLHMC_PEPBLMAX_PMPEPBLMAX_S 0
3908 #define GLHMC_PEPBLMAX_PMPEPBLMAX_M MAKEMASK(0x1FFFFFFF, 0)
3909 #define GLHMC_PEQ1BASE(_i) (0x00525200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3911 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_S 0
3912 #define GLHMC_PEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0)
3913 #define GLHMC_PEQ1CNT(_i) (0x00525300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3915 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_S 0
3916 #define GLHMC_PEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0)
3917 #define GLHMC_PEQ1FLBASE(_i) (0x00525400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3919 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S 0
3920 #define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0)
3921 #define GLHMC_PEQ1FLMAX 0x00522058 /* Reset Source: CORER */
3922 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S 0
3923 #define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_M MAKEMASK(0x3FFFFFF, 0)
3924 #define GLHMC_PEQ1MAX 0x00522054 /* Reset Source: CORER */
3925 #define GLHMC_PEQ1MAX_PMPEQ1MAX_S 0
3926 #define GLHMC_PEQ1MAX_PMPEQ1MAX_M MAKEMASK(0xFFFFFFF, 0)
3927 #define GLHMC_PEQ1OBJSZ 0x00522050 /* Reset Source: CORER */
3928 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S 0
3929 #define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_M MAKEMASK(0xF, 0)
3930 #define GLHMC_PEQPBASE(_i) (0x00524000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3932 #define GLHMC_PEQPBASE_FPMPEQPBASE_S 0
3933 #define GLHMC_PEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0)
3934 #define GLHMC_PEQPCNT(_i) (0x00524100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3936 #define GLHMC_PEQPCNT_FPMPEQPCNT_S 0
3937 #define GLHMC_PEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0)
3938 #define GLHMC_PEQPOBJSZ 0x0052201C /* Reset Source: CORER */
3939 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S 0
3940 #define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_M MAKEMASK(0xF, 0)
3941 #define GLHMC_PERRFBASE(_i) (0x00526800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3943 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_S 0
3944 #define GLHMC_PERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
3945 #define GLHMC_PERRFCNT(_i) (0x00526900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3947 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_S 0
3948 #define GLHMC_PERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
3949 #define GLHMC_PERRFFLBASE(_i) (0x00526A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3951 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S 0
3952 #define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
3953 #define GLHMC_PERRFFLCNT_PMAT(_i) (0x00526B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3955 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S 0
3956 #define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_M MAKEMASK(0x1FFFFFFF, 0)
3957 #define GLHMC_PERRFFLMAX 0x005220A0 /* Reset Source: CORER */
3958 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_S 0
3959 #define GLHMC_PERRFFLMAX_PMPERRFFLMAX_M MAKEMASK(0x3FFFFFF, 0)
3961 #define GLHMC_PERRFFLMAX_RSVD_M MAKEMASK(0x3F, 26)
3962 #define GLHMC_PERRFMAX 0x0052209C /* Reset Source: CORER */
3963 #define GLHMC_PERRFMAX_PMPERRFMAX_S 0
3964 #define GLHMC_PERRFMAX_PMPERRFMAX_M MAKEMASK(0xFFFFFFF, 0)
3966 #define GLHMC_PERRFMAX_RSVD_M MAKEMASK(0xF, 28)
3967 #define GLHMC_PERRFOBJSZ 0x00522098 /* Reset Source: CORER */
3968 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S 0
3969 #define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_M MAKEMASK(0xF, 0)
3971 #define GLHMC_PERRFOBJSZ_RSVD_M MAKEMASK(0xFFFFFFF, 4)
3972 #define GLHMC_PETIMERBASE(_i) (0x00525A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3974 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_S 0
3975 #define GLHMC_PETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
3976 #define GLHMC_PETIMERCNT(_i) (0x00525B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3978 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_S 0
3979 #define GLHMC_PETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
3980 #define GLHMC_PETIMERMAX 0x00522084 /* Reset Source: CORER */
3981 #define GLHMC_PETIMERMAX_PMPETIMERMAX_S 0
3982 #define GLHMC_PETIMERMAX_PMPETIMERMAX_M MAKEMASK(0x1FFFFFFF, 0)
3983 #define GLHMC_PETIMEROBJSZ 0x00522080 /* Reset Source: CORER */
3984 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S 0
3985 #define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_M MAKEMASK(0xF, 0)
3986 #define GLHMC_PEXFBASE(_i) (0x00524E00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3988 #define GLHMC_PEXFBASE_FPMPEXFBASE_S 0
3989 #define GLHMC_PEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0)
3990 #define GLHMC_PEXFCNT(_i) (0x00524F00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3992 #define GLHMC_PEXFCNT_FPMPEXFCNT_S 0
3993 #define GLHMC_PEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0)
3994 #define GLHMC_PEXFFLBASE(_i) (0x00525000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
3996 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S 0
3997 #define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
3998 #define GLHMC_PEXFFLMAX 0x0052204C /* Reset Source: CORER */
3999 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_S 0
4000 #define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M MAKEMASK(0xFFFFFFF, 0)
4001 #define GLHMC_PEXFMAX 0x00522048 /* Reset Source: CORER */
4002 #define GLHMC_PEXFMAX_PMPEXFMAX_S 0
4003 #define GLHMC_PEXFMAX_PMPEXFMAX_M MAKEMASK(0xFFFFFFF, 0)
4004 #define GLHMC_PEXFOBJSZ 0x00522044 /* Reset Source: CORER */
4005 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S 0
4006 #define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_M MAKEMASK(0xF, 0)
4007 #define GLHMC_PFPESDPART(_i) (0x00520880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
4009 #define GLHMC_PFPESDPART_PMSDBASE_S 0
4010 #define GLHMC_PFPESDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
4012 #define GLHMC_PFPESDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4013 #define GLHMC_PFPESDPART_FPMAT(_i) (0x00100880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
4015 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_S 0
4016 #define GLHMC_PFPESDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
4018 #define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4019 #define GLHMC_SDPART(_i) (0x00520800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
4021 #define GLHMC_SDPART_PMSDBASE_S 0
4022 #define GLHMC_SDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
4024 #define GLHMC_SDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4025 #define GLHMC_SDPART_FPMAT(_i) (0x00100800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
4027 #define GLHMC_SDPART_FPMAT_PMSDBASE_S 0
4028 #define GLHMC_SDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
4030 #define GLHMC_SDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4031 #define GLHMC_VFAPBVTINUSEBASE(_i) (0x0052CA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4033 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_S 0
4034 #define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)
4035 #define GLHMC_VFCEQPART(_i) (0x00502F00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4037 #define GLHMC_VFCEQPART_PMCEQBASE_S 0
4038 #define GLHMC_VFCEQPART_PMCEQBASE_M MAKEMASK(0x3FF, 0)
4040 #define GLHMC_VFCEQPART_PMCEQSIZE_M MAKEMASK(0x3FF, 16)
4041 #define GLHMC_VFDBCQPART(_i) (0x00502E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4043 #define GLHMC_VFDBCQPART_PMDBCQBASE_S 0
4044 #define GLHMC_VFDBCQPART_PMDBCQBASE_M MAKEMASK(0x3FFF, 0)
4046 #define GLHMC_VFDBCQPART_PMDBCQSIZE_M MAKEMASK(0x7FFF, 16)
4047 #define GLHMC_VFDBQPPART(_i) (0x00504520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4049 #define GLHMC_VFDBQPPART_PMDBQPBASE_S 0
4050 #define GLHMC_VFDBQPPART_PMDBQPBASE_M MAKEMASK(0x3FFF, 0)
4052 #define GLHMC_VFDBQPPART_PMDBQPSIZE_M MAKEMASK(0x7FFF, 16)
4053 #define GLHMC_VFFSIAVBASE(_i) (0x0052D600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4055 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_S 0
4056 #define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_M MAKEMASK(0xFFFFFF, 0)
4057 #define GLHMC_VFFSIAVCNT(_i) (0x0052D700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4059 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_S 0
4060 #define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_M MAKEMASK(0x1FFFFFFF, 0)
4061 #define GLHMC_VFFSIMCBASE(_i) (0x0052E000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4063 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_S 0
4064 #define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_M MAKEMASK(0xFFFFFF, 0)
4065 #define GLHMC_VFFSIMCCNT(_i) (0x0052E100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4067 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_S 0
4068 #define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_M MAKEMASK(0x1FFFFFFF, 0)
4069 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4071 #define GLHMC_VFPDINV_PMSDIDX_S 0
4072 #define GLHMC_VFPDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
4076 #define GLHMC_VFPDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
4077 #define GLHMC_VFPDINV_FPMAT(_i) (0x00108300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4079 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_S 0
4080 #define GLHMC_VFPDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4084 #define GLHMC_VFPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
4085 #define GLHMC_VFPEARPBASE(_i) (0x0052C800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4087 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_S 0
4088 #define GLHMC_VFPEARPBASE_FPMPEARPBASE_M MAKEMASK(0xFFFFFF, 0)
4089 #define GLHMC_VFPEARPCNT(_i) (0x0052C900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4091 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_S 0
4092 #define GLHMC_VFPEARPCNT_FPMPEARPCNT_M MAKEMASK(0x1FFFFFFF, 0)
4093 #define GLHMC_VFPECQBASE(_i) (0x0052C200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4095 #define GLHMC_VFPECQBASE_FPMPECQBASE_S 0
4096 #define GLHMC_VFPECQBASE_FPMPECQBASE_M MAKEMASK(0xFFFFFF, 0)
4097 #define GLHMC_VFPECQCNT(_i) (0x0052C300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4099 #define GLHMC_VFPECQCNT_FPMPECQCNT_S 0
4100 #define GLHMC_VFPECQCNT_FPMPECQCNT_M MAKEMASK(0x1FFFFFFF, 0)
4101 #define GLHMC_VFPEHDRBASE(_i) (0x0052E200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4103 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_S 0
4104 #define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_M MAKEMASK(0xFFFFFFFF, 0)
4105 #define GLHMC_VFPEHDRCNT(_i) (0x0052E300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4107 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_S 0
4108 #define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_M MAKEMASK(0xFFFFFFFF, 0)
4109 #define GLHMC_VFPEHTCNT(_i) (0x0052C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4111 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_S 0
4112 #define GLHMC_VFPEHTCNT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
4113 #define GLHMC_VFPEHTCNT_FPMAT(_i) (0x0010C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4115 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_S 0
4116 #define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_M MAKEMASK(0x1FFFFFFF, 0)
4117 #define GLHMC_VFPEHTEBASE(_i) (0x0052C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4119 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_S 0
4120 #define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
4121 #define GLHMC_VFPEHTEBASE_FPMAT(_i) (0x0010C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4123 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_S 0
4124 #define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_M MAKEMASK(0xFFFFFF, 0)
4125 #define GLHMC_VFPEMDBASE(_i) (0x0052E400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4127 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_S 0
4128 #define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_M MAKEMASK(0xFFFFFFFF, 0)
4129 #define GLHMC_VFPEMDCNT(_i) (0x0052E500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4131 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_S 0
4132 #define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_M MAKEMASK(0xFFFFFFFF, 0)
4133 #define GLHMC_VFPEMRBASE(_i) (0x0052CC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4135 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_S 0
4136 #define GLHMC_VFPEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
4137 #define GLHMC_VFPEMRCNT(_i) (0x0052CD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4139 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_S 0
4140 #define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
4141 #define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4143 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
4144 #define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
4145 #define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4147 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0
4148 #define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
4149 #define GLHMC_VFPEOOISCFFLBASE(_i) (0x0052EC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4151 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
4152 #define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
4153 #define GLHMC_VFPEPBLBASE(_i) (0x0052D800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4155 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_S 0
4156 #define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_M MAKEMASK(0xFFFFFF, 0)
4157 #define GLHMC_VFPEPBLCNT(_i) (0x0052D900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4159 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_S 0
4160 #define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_M MAKEMASK(0x1FFFFFFF, 0)
4161 #define GLHMC_VFPEQ1BASE(_i) (0x0052D200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4163 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_S 0
4164 #define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_M MAKEMASK(0xFFFFFF, 0)
4165 #define GLHMC_VFPEQ1CNT(_i) (0x0052D300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4167 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_S 0
4168 #define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_M MAKEMASK(0x1FFFFFFF, 0)
4169 #define GLHMC_VFPEQ1FLBASE(_i) (0x0052D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4171 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_S 0
4172 #define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_M MAKEMASK(0xFFFFFF, 0)
4173 #define GLHMC_VFPEQPBASE(_i) (0x0052C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4175 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_S 0
4176 #define GLHMC_VFPEQPBASE_FPMPEQPBASE_M MAKEMASK(0xFFFFFF, 0)
4177 #define GLHMC_VFPEQPCNT(_i) (0x0052C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4179 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_S 0
4180 #define GLHMC_VFPEQPCNT_FPMPEQPCNT_M MAKEMASK(0x1FFFFFFF, 0)
4181 #define GLHMC_VFPERRFBASE(_i) (0x0052E800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4183 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S 0
4184 #define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
4185 #define GLHMC_VFPERRFCNT(_i) (0x0052E900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4187 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S 0
4188 #define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
4189 #define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4191 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
4192 #define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
4193 #define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4195 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0
4196 #define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
4197 #define GLHMC_VFPETIMERCNT(_i) (0x0052DB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4199 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S 0
4200 #define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
4201 #define GLHMC_VFPEXFBASE(_i) (0x0052CE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4203 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_S 0
4204 #define GLHMC_VFPEXFBASE_FPMPEXFBASE_M MAKEMASK(0xFFFFFF, 0)
4205 #define GLHMC_VFPEXFCNT(_i) (0x0052CF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4207 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_S 0
4208 #define GLHMC_VFPEXFCNT_FPMPEXFCNT_M MAKEMASK(0x1FFFFFFF, 0)
4209 #define GLHMC_VFPEXFFLBASE(_i) (0x0052D000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4211 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S 0
4212 #define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
4213 #define GLHMC_VFSDDATAHIGH(_i) (0x00528200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4215 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S 0
4216 #define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4217 #define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4219 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
4220 #define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4221 #define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4223 #define GLHMC_VFSDDATALOW_PMSDVALID_S 0
4224 #define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0)
4228 #define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4230 #define GLHMC_VFSDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4231 #define GLHMC_VFSDDATALOW_FPMAT(_i) (0x00108100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4233 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_S 0
4234 #define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_M BIT(0)
4238 #define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4240 #define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4241 #define GLHMC_VFSDPART(_i) (0x00528800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4243 #define GLHMC_VFSDPART_PMSDBASE_S 0
4244 #define GLHMC_VFSDPART_PMSDBASE_M MAKEMASK(0xFFF, 0)
4246 #define GLHMC_VFSDPART_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4247 #define GLHMC_VFSDPART_FPMAT(_i) (0x00108800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
4249 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_S 0
4250 #define GLHMC_VFSDPART_FPMAT_PMSDBASE_M MAKEMASK(0xFFF, 0)
4252 #define GLHMC_VFSDPART_FPMAT_PMSDSIZE_M MAKEMASK(0x1FFF, 16)
4253 #define GLMDOC_CACHESIZE 0x0051C06C /* Reset Source: CORER */
4254 #define GLMDOC_CACHESIZE_WORD_SIZE_S 0
4255 #define GLMDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4257 #define GLMDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4259 #define GLMDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4260 #define GLPBLOC0_CACHESIZE 0x00518074 /* Reset Source: CORER */
4261 #define GLPBLOC0_CACHESIZE_WORD_SIZE_S 0
4262 #define GLPBLOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4264 #define GLPBLOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4266 #define GLPBLOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4267 #define GLPBLOC1_CACHESIZE 0x0051A074 /* Reset Source: CORER */
4268 #define GLPBLOC1_CACHESIZE_WORD_SIZE_S 0
4269 #define GLPBLOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4271 #define GLPBLOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4273 #define GLPBLOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4274 #define GLPDOC_CACHESIZE 0x00530048 /* Reset Source: CORER */
4275 #define GLPDOC_CACHESIZE_WORD_SIZE_S 0
4276 #define GLPDOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4278 #define GLPDOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4280 #define GLPDOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4281 #define GLPDOC_CACHESIZE_FPMAT 0x00110088 /* Reset Source: CORER */
4282 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_S 0
4283 #define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_M MAKEMASK(0xFF, 0)
4285 #define GLPDOC_CACHESIZE_FPMAT_SETS_M MAKEMASK(0xFFF, 8)
4287 #define GLPDOC_CACHESIZE_FPMAT_WAYS_M MAKEMASK(0xF, 20)
4288 #define GLPEOC0_CACHESIZE 0x005140A8 /* Reset Source: CORER */
4289 #define GLPEOC0_CACHESIZE_WORD_SIZE_S 0
4290 #define GLPEOC0_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4292 #define GLPEOC0_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4294 #define GLPEOC0_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4295 #define GLPEOC1_CACHESIZE 0x005160A8 /* Reset Source: CORER */
4296 #define GLPEOC1_CACHESIZE_WORD_SIZE_S 0
4297 #define GLPEOC1_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4299 #define GLPEOC1_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4301 #define GLPEOC1_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4302 #define PFHMC_ERRORDATA 0x00520500 /* Reset Source: PFR */
4303 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_S 0
4304 #define PFHMC_ERRORDATA_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0)
4305 #define PFHMC_ERRORDATA_FPMAT 0x00100500 /* Reset Source: PFR */
4306 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_S 0
4307 #define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_M MAKEMASK(0x3FFFFFFF, 0)
4308 #define PFHMC_ERRORINFO 0x00520400 /* Reset Source: PFR */
4309 #define PFHMC_ERRORINFO_PMF_INDEX_S 0
4310 #define PFHMC_ERRORINFO_PMF_INDEX_M MAKEMASK(0x1F, 0)
4314 #define PFHMC_ERRORINFO_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
4316 #define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
4319 #define PFHMC_ERRORINFO_FPMAT 0x00100400 /* Reset Source: PFR */
4320 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S 0
4321 #define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M MAKEMASK(0x1F, 0)
4325 #define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
4327 #define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
4330 #define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */
4331 #define PFHMC_PDINV_PMSDIDX_S 0
4332 #define PFHMC_PDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
4336 #define PFHMC_PDINV_PMPDIDX_M MAKEMASK(0x1FF, 16)
4337 #define PFHMC_PDINV_FPMAT 0x00100300 /* Reset Source: PFR */
4338 #define PFHMC_PDINV_FPMAT_PMSDIDX_S 0
4339 #define PFHMC_PDINV_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4343 #define PFHMC_PDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
4344 #define PFHMC_SDCMD 0x00520000 /* Reset Source: PFR */
4345 #define PFHMC_SDCMD_PMSDIDX_S 0
4346 #define PFHMC_SDCMD_PMSDIDX_M MAKEMASK(0xFFF, 0)
4351 #define PFHMC_SDCMD_FPMAT 0x00100000 /* Reset Source: PFR */
4352 #define PFHMC_SDCMD_FPMAT_PMSDIDX_S 0
4353 #define PFHMC_SDCMD_FPMAT_PMSDIDX_M MAKEMASK(0xFFF, 0)
4358 #define PFHMC_SDDATAHIGH 0x00520200 /* Reset Source: PFR */
4359 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_S 0
4360 #define PFHMC_SDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4361 #define PFHMC_SDDATAHIGH_FPMAT 0x00100200 /* Reset Source: PFR */
4362 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
4363 #define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
4364 #define PFHMC_SDDATALOW 0x00520100 /* Reset Source: PFR */
4365 #define PFHMC_SDDATALOW_PMSDVALID_S 0
4366 #define PFHMC_SDDATALOW_PMSDVALID_M BIT(0)
4370 #define PFHMC_SDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4372 #define PFHMC_SDDATALOW_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4373 #define PFHMC_SDDATALOW_FPMAT 0x00100100 /* Reset Source: PFR */
4374 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_S 0
4375 #define PFHMC_SDDATALOW_FPMAT_PMSDVALID_M BIT(0)
4379 #define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
4381 #define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_M MAKEMASK(0xFFFFF, 12)
4382 #define GL_DSI_REPC 0x00294208 /* Reset Source: CORER */
4383 #define GL_DSI_REPC_NO_DESC_CNT_S 0
4384 #define GL_DSI_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0)
4386 #define GL_DSI_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16)
4387 #define GL_MDCK_TDAT_TCLAN 0x000FC0DC /* Reset Source: CORER */
4388 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_S 0
4389 #define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_M BIT(0)
4430 #define GLCORE_CLKCTL_H 0x000B81E8 /* Reset Source: POR */
4431 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_S 0
4432 #define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_M MAKEMASK(0x3, 0)
4434 #define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_M MAKEMASK(0x3, 2)
4436 #define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_M MAKEMASK(0x3, 4)
4438 #define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_M MAKEMASK(0x3, 6)
4440 #define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_M MAKEMASK(0x7, 8)
4441 #define GLCORE_CLKCTL_L 0x000B8254 /* Reset Source: POR */
4442 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_S 0
4443 #define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_M MAKEMASK(0x3, 0)
4445 #define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_M MAKEMASK(0x3, 2)
4447 #define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_M MAKEMASK(0x3, 4)
4449 #define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_M MAKEMASK(0x3, 6)
4451 #define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_M MAKEMASK(0x7, 8)
4452 #define GLCORE_CLKCTL_M 0x000B8258 /* Reset Source: POR */
4453 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_S 0
4454 #define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_M MAKEMASK(0x3, 0)
4456 #define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_M MAKEMASK(0x3, 2)
4458 #define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_M MAKEMASK(0x3, 4)
4460 #define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_M MAKEMASK(0x3, 6)
4462 #define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_M MAKEMASK(0x7, 8)
4463 #define GLFOC_CACHESIZE 0x000AA074 /* Reset Source: CORER */
4464 #define GLFOC_CACHESIZE_WORD_SIZE_S 0
4465 #define GLFOC_CACHESIZE_WORD_SIZE_M MAKEMASK(0xFF, 0)
4467 #define GLFOC_CACHESIZE_SETS_M MAKEMASK(0xFFF, 8)
4469 #define GLFOC_CACHESIZE_WAYS_M MAKEMASK(0xF, 20)
4470 #define GLMAC_CLKSTAT 0x000B8210 /* Reset Source: POR */
4471 #define GLMAC_CLKSTAT_P0_CLK_SPEED_S 0
4472 #define GLMAC_CLKSTAT_P0_CLK_SPEED_M MAKEMASK(0xF, 0)
4474 #define GLMAC_CLKSTAT_P1_CLK_SPEED_M MAKEMASK(0xF, 4)
4476 #define GLMAC_CLKSTAT_P2_CLK_SPEED_M MAKEMASK(0xF, 8)
4478 #define GLMAC_CLKSTAT_P3_CLK_SPEED_M MAKEMASK(0xF, 12)
4480 #define GLMAC_CLKSTAT_P4_CLK_SPEED_M MAKEMASK(0xF, 16)
4482 #define GLMAC_CLKSTAT_P5_CLK_SPEED_M MAKEMASK(0xF, 20)
4484 #define GLMAC_CLKSTAT_P6_CLK_SPEED_M MAKEMASK(0xF, 24)
4486 #define GLMAC_CLKSTAT_P7_CLK_SPEED_M MAKEMASK(0xF, 28)
4487 #define GLTPB_100G_MAC_FC_THRESH 0x00099510 /* Reset Source: CORER */
4488 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_S 0
4489 #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
4491 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
4492 #define E800_GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */
4493 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0
4494 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
4496 #define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
4497 #define GLTPB_PACING_10G 0x000994E4 /* Reset Source: CORER */
4498 #define GLTPB_PACING_10G_N_S 0
4499 #define GLTPB_PACING_10G_N_M MAKEMASK(0xFF, 0)
4501 #define GLTPB_PACING_10G_K_M MAKEMASK(0xFF, 8)
4503 #define GLTPB_PACING_10G_S_M MAKEMASK(0x1FF, 16)
4504 #define GLTPB_PACING_25G 0x000994E0 /* Reset Source: CORER */
4505 #define GLTPB_PACING_25G_N_S 0
4506 #define GLTPB_PACING_25G_N_M MAKEMASK(0xFF, 0)
4508 #define GLTPB_PACING_25G_K_M MAKEMASK(0xFF, 8)
4510 #define GLTPB_PACING_25G_S_M MAKEMASK(0x1FF, 16)
4511 #define GLTPB_PORT_PACING_SPEED 0x000994E8 /* Reset Source: CORER */
4512 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_S 0
4513 #define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_M BIT(0)
4528 #define TPB_CFG_SCHEDULED_BC_THRESHOLD 0x00099494 /* Reset Source: CORER */
4529 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_S 0
4530 #define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_M MAKEMASK(0x7FFF, 0)
4531 #define GL_UFUSE_SOC 0x000A400C /* Reset Source: POR */
4532 #define GL_UFUSE_SOC_PORT_MODE_S 0
4533 #define GL_UFUSE_SOC_PORT_MODE_M MAKEMASK(0x3, 0)
4535 #define GL_UFUSE_SOC_BANDWIDTH_M MAKEMASK(0x3, 2)
4553 #define E800_GL_UFUSE_SOC_SPARE_FUSES_M MAKEMASK(0xF, 12)
4554 #define EMPINT_GPIO_ENA 0x000880C0 /* Reset Source: POR */
4555 #define EMPINT_GPIO_ENA_GPIO0_ENA_S 0
4556 #define EMPINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
4569 #define GLGEN_MAC_LINK_TOPO 0x000B81DC /* Reset Source: GLOBR */
4570 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_S 0
4571 #define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M MAKEMASK(0x3, 0)
4572 #define GLINT_CEQCTL(_INT) (0x0015C000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4574 #define GLINT_CEQCTL_MSIX_INDX_S 0
4575 #define GLINT_CEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4577 #define GLINT_CEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4582 #define GLINT_CTL 0x0016CC54 /* Reset Source: CORER */
4583 #define GLINT_CTL_DIS_AUTOMASK_S 0
4584 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
4586 #define GLINT_CTL_RSVD_M MAKEMASK(0x7FFF, 1)
4588 #define GLINT_CTL_ITR_GRAN_200_M MAKEMASK(0xF, 16)
4590 #define GLINT_CTL_ITR_GRAN_100_M MAKEMASK(0xF, 20)
4592 #define GLINT_CTL_ITR_GRAN_50_M MAKEMASK(0xF, 24)
4594 #define GLINT_CTL_ITR_GRAN_25_M MAKEMASK(0xF, 28)
4595 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4597 #define GLINT_DYN_CTL_INTENA_S 0
4598 #define GLINT_DYN_CTL_INTENA_M BIT(0)
4604 #define GLINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
4606 #define GLINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
4610 #define GLINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
4615 #define GLINT_FW_TOOL_CTL 0x0016C840 /* Reset Source: CORER */
4616 #define GLINT_FW_TOOL_CTL_MSIX_INDX_S 0
4617 #define GLINT_FW_TOOL_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4619 #define GLINT_FW_TOOL_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4624 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: CORER */
4626 #define GLINT_ITR_INTERVAL_S 0
4627 #define GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, 0)
4628 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4630 #define GLINT_RATE_INTERVAL_S 0
4631 #define GLINT_RATE_INTERVAL_M MAKEMASK(0x3F, 0)
4634 #define GLINT_TSYN_PFMSTR(_i) (0x0016CCC0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
4636 #define GLINT_TSYN_PFMSTR_PF_MASTER_S 0
4637 #define GLINT_TSYN_PFMSTR_PF_MASTER_M MAKEMASK(0x7, 0)
4638 #define GLINT_TSYN_PHY 0x0016CC50 /* Reset Source: CORER */
4639 #define GLINT_TSYN_PHY_PHY_INDX_S 0
4641 #define E800_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0)
4642 #define E830_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0xFF, 0)
4643 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
4645 #define GLINT_VECT2FUNC_VF_NUM_S 0
4646 #define GLINT_VECT2FUNC_VF_NUM_M MAKEMASK(0xFF, 0)
4648 #define GLINT_VECT2FUNC_PF_NUM_M MAKEMASK(0x7, 12)
4651 #define PF0INT_FW_HLP_CTL 0x0016C844 /* Reset Source: CORER */
4652 #define PF0INT_FW_HLP_CTL_MSIX_INDX_S 0
4653 #define PF0INT_FW_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4655 #define PF0INT_FW_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4660 #define PF0INT_FW_PSM_CTL 0x0016C848 /* Reset Source: CORER */
4661 #define PF0INT_FW_PSM_CTL_MSIX_INDX_S 0
4662 #define PF0INT_FW_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4664 #define PF0INT_FW_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4669 #define PF0INT_MBX_CPM_CTL 0x0016B2C0 /* Reset Source: CORER */
4670 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_S 0
4671 #define PF0INT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4673 #define PF0INT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4678 #define PF0INT_MBX_HLP_CTL 0x0016B2C4 /* Reset Source: CORER */
4679 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_S 0
4680 #define PF0INT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4682 #define PF0INT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4687 #define PF0INT_MBX_PSM_CTL 0x0016B2C8 /* Reset Source: CORER */
4688 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_S 0
4689 #define PF0INT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4691 #define PF0INT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4696 #define PF0INT_OICR_CPM 0x0016CC40 /* Reset Source: CORER */
4697 #define PF0INT_OICR_CPM_INTEVENT_S 0
4698 #define PF0INT_OICR_CPM_INTEVENT_M BIT(0)
4703 #define E800_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2)
4704 #define E830_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0x3F, 2)
4720 #define PF0INT_OICR_CPM_RSV2_M MAKEMASK(0x3, 17)
4747 #define PF0INT_OICR_CTL_CPM 0x0016CC48 /* Reset Source: CORER */
4748 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_S 0
4749 #define PF0INT_OICR_CTL_CPM_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4751 #define PF0INT_OICR_CTL_CPM_ITR_INDX_M MAKEMASK(0x3, 11)
4756 #define PF0INT_OICR_CTL_HLP 0x0016CC5C /* Reset Source: CORER */
4757 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_S 0
4758 #define PF0INT_OICR_CTL_HLP_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4760 #define PF0INT_OICR_CTL_HLP_ITR_INDX_M MAKEMASK(0x3, 11)
4765 #define PF0INT_OICR_CTL_PSM 0x0016CC64 /* Reset Source: CORER */
4766 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_S 0
4767 #define PF0INT_OICR_CTL_PSM_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4769 #define PF0INT_OICR_CTL_PSM_ITR_INDX_M MAKEMASK(0x3, 11)
4774 #define PF0INT_OICR_ENA_CPM 0x0016CC60 /* Reset Source: CORER */
4775 #define PF0INT_OICR_ENA_CPM_RSV0_S 0
4776 #define PF0INT_OICR_ENA_CPM_RSV0_M BIT(0)
4778 #define PF0INT_OICR_ENA_CPM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4779 #define PF0INT_OICR_ENA_HLP 0x0016CC4C /* Reset Source: CORER */
4780 #define PF0INT_OICR_ENA_HLP_RSV0_S 0
4781 #define PF0INT_OICR_ENA_HLP_RSV0_M BIT(0)
4783 #define PF0INT_OICR_ENA_HLP_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4784 #define PF0INT_OICR_ENA_PSM 0x0016CC58 /* Reset Source: CORER */
4785 #define PF0INT_OICR_ENA_PSM_RSV0_S 0
4786 #define PF0INT_OICR_ENA_PSM_RSV0_M BIT(0)
4788 #define PF0INT_OICR_ENA_PSM_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
4789 #define PF0INT_OICR_HLP 0x0016CC68 /* Reset Source: CORER */
4790 #define PF0INT_OICR_HLP_INTEVENT_S 0
4791 #define PF0INT_OICR_HLP_INTEVENT_M BIT(0)
4796 #define E800_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2)
4797 #define E830_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0x3F, 2)
4813 #define PF0INT_OICR_HLP_RSV2_M MAKEMASK(0x3, 17)
4840 #define PF0INT_OICR_PSM 0x0016CC44 /* Reset Source: CORER */
4841 #define PF0INT_OICR_PSM_INTEVENT_S 0
4842 #define PF0INT_OICR_PSM_INTEVENT_M BIT(0)
4847 #define E800_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2)
4848 #define E830_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0x3F, 2)
4864 #define PF0INT_OICR_PSM_RSV2_M MAKEMASK(0x3, 17)
4891 #define PF0INT_SB_CPM_CTL 0x0016B2CC /* Reset Source: CORER */
4892 #define PF0INT_SB_CPM_CTL_MSIX_INDX_S 0
4893 #define PF0INT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4895 #define PF0INT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4900 #define PF0INT_SB_HLP_CTL 0x0016B640 /* Reset Source: CORER */
4901 #define PF0INT_SB_HLP_CTL_MSIX_INDX_S 0
4902 #define PF0INT_SB_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4904 #define PF0INT_SB_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4909 #define PFINT_AEQCTL 0x0016CB00 /* Reset Source: CORER */
4910 #define PFINT_AEQCTL_MSIX_INDX_S 0
4911 #define PFINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4913 #define PFINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
4918 #define PFINT_ALLOC 0x001D2600 /* Reset Source: CORER */
4919 #define PFINT_ALLOC_FIRST_S 0
4920 #define PFINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0)
4922 #define PFINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12)
4925 #define PFINT_ALLOC_PCI 0x0009D800 /* Reset Source: PCIR */
4926 #define PFINT_ALLOC_PCI_FIRST_S 0
4927 #define PFINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0)
4929 #define PFINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12)
4932 #define PFINT_FW_CTL 0x0016C800 /* Reset Source: CORER */
4933 #define PFINT_FW_CTL_MSIX_INDX_S 0
4934 #define PFINT_FW_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4936 #define PFINT_FW_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4941 #define PFINT_GPIO_ENA 0x00088080 /* Reset Source: CORER */
4942 #define PFINT_GPIO_ENA_GPIO0_ENA_S 0
4943 #define PFINT_GPIO_ENA_GPIO0_ENA_M BIT(0)
4956 #define PFINT_MBX_CTL 0x0016B280 /* Reset Source: CORER */
4957 #define PFINT_MBX_CTL_MSIX_INDX_S 0
4958 #define PFINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
4960 #define PFINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
4965 #define PFINT_OICR 0x0016CA00 /* Reset Source: CORER */
4966 #define PFINT_OICR_INTEVENT_S 0
4967 #define PFINT_OICR_INTEVENT_M BIT(0)
4972 #define E800_PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2)
4973 #define E830_PFINT_OICR_RSV1_M MAKEMASK(0x3F, 2)
4989 #define PFINT_OICR_RSV2_M MAKEMASK(0x3, 17)
5016 #define PFINT_OICR_CTL 0x0016CA80 /* Reset Source: CORER */
5017 #define PFINT_OICR_CTL_MSIX_INDX_S 0
5018 #define PFINT_OICR_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5020 #define PFINT_OICR_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5025 #define PFINT_OICR_ENA 0x0016C900 /* Reset Source: CORER */
5026 #define PFINT_OICR_ENA_RSV0_S 0
5027 #define PFINT_OICR_ENA_RSV0_M BIT(0)
5029 #define PFINT_OICR_ENA_INT_ENA_M MAKEMASK(0x7FFFFFFF, 1)
5030 #define PFINT_SB_CTL 0x0016B600 /* Reset Source: CORER */
5031 #define PFINT_SB_CTL_MSIX_INDX_S 0
5032 #define PFINT_SB_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5034 #define PFINT_SB_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5039 #define PFINT_TSYN_MSK 0x0016C980 /* Reset Source: CORER */
5040 #define PFINT_TSYN_MSK_PHY_INDX_S 0
5042 #define E800_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0)
5043 #define E830_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0xFF, 0)
5044 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5046 #define QINT_RQCTL_MSIX_INDX_S 0
5047 #define QINT_RQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5049 #define QINT_RQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
5054 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */
5056 #define QINT_TQCTL_MSIX_INDX_S 0
5057 #define QINT_TQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5059 #define QINT_TQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
5064 #define VPINT_AEQCTL(_VF) (0x0016B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5066 #define VPINT_AEQCTL_MSIX_INDX_S 0
5067 #define VPINT_AEQCTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5069 #define VPINT_AEQCTL_ITR_INDX_M MAKEMASK(0x3, 11)
5074 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5076 #define VPINT_ALLOC_FIRST_S 0
5077 #define VPINT_ALLOC_FIRST_M MAKEMASK(0x7FF, 0)
5079 #define VPINT_ALLOC_LAST_M MAKEMASK(0x7FF, 12)
5082 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */
5084 #define VPINT_ALLOC_PCI_FIRST_S 0
5085 #define VPINT_ALLOC_PCI_FIRST_M MAKEMASK(0x7FF, 0)
5087 #define VPINT_ALLOC_PCI_LAST_M MAKEMASK(0x7FF, 12)
5090 #define VPINT_MBX_CPM_CTL(_VP128) (0x0016B000 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
5092 #define VPINT_MBX_CPM_CTL_MSIX_INDX_S 0
5093 #define VPINT_MBX_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5095 #define VPINT_MBX_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5100 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
5102 #define VPINT_MBX_CTL_MSIX_INDX_S 0
5103 #define VPINT_MBX_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5105 #define VPINT_MBX_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5110 #define VPINT_MBX_HLP_CTL(_VP16) (0x0016B200 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5112 #define VPINT_MBX_HLP_CTL_MSIX_INDX_S 0
5113 #define VPINT_MBX_HLP_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5115 #define VPINT_MBX_HLP_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5120 #define VPINT_MBX_PSM_CTL(_VP16) (0x0016B240 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5122 #define VPINT_MBX_PSM_CTL_MSIX_INDX_S 0
5123 #define VPINT_MBX_PSM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5125 #define VPINT_MBX_PSM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5130 #define VPINT_SB_CPM_CTL(_VP128) (0x0016B400 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
5132 #define VPINT_SB_CPM_CTL_MSIX_INDX_S 0
5133 #define VPINT_SB_CPM_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0)
5135 #define VPINT_SB_CPM_CTL_ITR_INDX_M MAKEMASK(0x3, 11)
5140 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE(_i) (0x00049240 + ((_i) * 4)) /* _i=0...20 */ /* Reset Source: CORER */
5142 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_S 0
5143 #define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_M MAKEMASK(0xFF, 0)
5144 #define GL_TDPU_PSM_DEFAULT_RECIPE(_i) (0x00049294 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
5146 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_S 0
5147 #define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_M BIT(0)
5156 #define GLLAN_PF_RECIPE(_i) (0x0029420C + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
5158 #define GLLAN_PF_RECIPE_RECIPE_S 0
5159 #define GLLAN_PF_RECIPE_RECIPE_M MAKEMASK(0x3, 0)
5160 #define GLLAN_RCTL_0 0x002941F8 /* Reset Source: CORER */
5161 #define GLLAN_RCTL_0_PXE_MODE_S 0
5162 #define GLLAN_RCTL_0_PXE_MODE_M BIT(0)
5163 #define GLLAN_RCTL_1 0x002941FC /* Reset Source: CORER */
5165 #define GLLAN_RCTL_1_RXMAX_EXPANSION_M MAKEMASK(0xF, 12)
5172 #define GLLAN_TSOMSK_F 0x00049308 /* Reset Source: CORER */
5173 #define GLLAN_TSOMSK_F_TCPMSKF_S 0
5174 #define GLLAN_TSOMSK_F_TCPMSKF_M MAKEMASK(0xFFF, 0)
5175 #define GLLAN_TSOMSK_L 0x00049310 /* Reset Source: CORER */
5176 #define GLLAN_TSOMSK_L_TCPMSKL_S 0
5177 #define GLLAN_TSOMSK_L_TCPMSKL_M MAKEMASK(0xFFF, 0)
5178 #define GLLAN_TSOMSK_M 0x0004930C /* Reset Source: CORER */
5179 #define GLLAN_TSOMSK_M_TCPMSKM_S 0
5180 #define GLLAN_TSOMSK_M_TCPMSKM_M MAKEMASK(0xFFF, 0)
5181 #define PFLAN_CP_QALLOC 0x00075700 /* Reset Source: CORER */
5182 #define PFLAN_CP_QALLOC_FIRSTQ_S 0
5183 #define PFLAN_CP_QALLOC_FIRSTQ_M MAKEMASK(0x1FF, 0)
5185 #define PFLAN_CP_QALLOC_LASTQ_M MAKEMASK(0x1FF, 16)
5188 #define PFLAN_DB_QALLOC 0x00075680 /* Reset Source: CORER */
5189 #define PFLAN_DB_QALLOC_FIRSTQ_S 0
5190 #define PFLAN_DB_QALLOC_FIRSTQ_M MAKEMASK(0xFF, 0)
5192 #define PFLAN_DB_QALLOC_LASTQ_M MAKEMASK(0xFF, 16)
5195 #define PFLAN_RX_QALLOC 0x001D2500 /* Reset Source: CORER */
5196 #define PFLAN_RX_QALLOC_FIRSTQ_S 0
5197 #define PFLAN_RX_QALLOC_FIRSTQ_M MAKEMASK(0x7FF, 0)
5199 #define PFLAN_RX_QALLOC_LASTQ_M MAKEMASK(0x7FF, 16)
5202 #define PFLAN_TX_QALLOC 0x001D2580 /* Reset Source: CORER */
5203 #define PFLAN_TX_QALLOC_FIRSTQ_S 0
5204 #define PFLAN_TX_QALLOC_FIRSTQ_M MAKEMASK(0x3FFF, 0)
5206 #define PFLAN_TX_QALLOC_LASTQ_M MAKEMASK(0x3FFF, 16)
5209 #define PRT_TDPUL2TAGSEN 0x00040BA0 /* Reset Source: CORER */
5210 #define PRT_TDPUL2TAGSEN_ENABLE_S 0
5211 #define PRT_TDPUL2TAGSEN_ENABLE_M MAKEMASK(0xFF, 0)
5213 #define PRT_TDPUL2TAGSEN_NONLAST_TAG_M MAKEMASK(0xFF, 8)
5214 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) /* _i=0...7, _QRX=0...2047 */ /* Reset Source: CORER */
5216 #define QRX_CONTEXT_RXQ_CONTEXT_S 0
5217 #define QRX_CONTEXT_RXQ_CONTEXT_M MAKEMASK(0xFFFFFFFF, 0)
5218 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */
5220 #define QRX_CTRL_QENA_REQ_S 0
5221 #define QRX_CTRL_QENA_REQ_M BIT(0)
5230 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5232 #define QRX_ITR_NO_EXPR_S 0
5233 #define QRX_ITR_NO_EXPR_M BIT(0)
5234 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
5236 #define QRX_TAIL_TAIL_S 0
5237 #define QRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0)
5238 #define VPDSI_RX_QTABLE(_i, _VP16) (0x00074C00 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */
5240 #define VPDSI_RX_QTABLE_PAGE_INDEX0_S 0
5241 #define VPDSI_RX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0)
5243 #define VPDSI_RX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8)
5245 #define VPDSI_RX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16)
5247 #define VPDSI_RX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24)
5248 #define VPDSI_TX_QTABLE(_i, _VP16) (0x001D2000 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */
5250 #define VPDSI_TX_QTABLE_PAGE_INDEX0_S 0
5251 #define VPDSI_TX_QTABLE_PAGE_INDEX0_M MAKEMASK(0x7F, 0)
5253 #define VPDSI_TX_QTABLE_PAGE_INDEX1_M MAKEMASK(0x7F, 8)
5255 #define VPDSI_TX_QTABLE_PAGE_INDEX2_M MAKEMASK(0x7F, 16)
5257 #define VPDSI_TX_QTABLE_PAGE_INDEX3_M MAKEMASK(0x7F, 24)
5258 #define VPLAN_DB_QTABLE(_i, _VF) (0x00070000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...3, _VF=0...255 */ /* Reset Source: CORER */
5260 #define VPLAN_DB_QTABLE_QINDEX_S 0
5261 #define VPLAN_DB_QTABLE_QINDEX_M MAKEMASK(0x1FF, 0)
5262 #define VPLAN_DSI_VF_MODE(_VP16) (0x002D2C00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
5264 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_S 0
5265 #define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_M BIT(0)
5266 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5268 #define VPLAN_RX_QBASE_VFFIRSTQ_S 0
5269 #define VPLAN_RX_QBASE_VFFIRSTQ_M MAKEMASK(0x7FF, 0)
5271 #define VPLAN_RX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16)
5274 #define VPLAN_RX_QTABLE(_i, _VF) (0x00060000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */
5276 #define VPLAN_RX_QTABLE_QINDEX_S 0
5277 #define VPLAN_RX_QTABLE_QINDEX_M MAKEMASK(0xFFF, 0)
5278 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5280 #define VPLAN_RXQ_MAPENA_RX_ENA_S 0
5281 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
5282 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5284 #define VPLAN_TX_QBASE_VFFIRSTQ_S 0
5285 #define VPLAN_TX_QBASE_VFFIRSTQ_M MAKEMASK(0x3FFF, 0)
5287 #define VPLAN_TX_QBASE_VFNUMQ_M MAKEMASK(0xFF, 16)
5290 #define VPLAN_TX_QTABLE(_i, _VF) (0x001C0000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */
5292 #define VPLAN_TX_QTABLE_QINDEX_S 0
5293 #define VPLAN_TX_QTABLE_QINDEX_M MAKEMASK(0x7FFF, 0)
5294 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5296 #define VPLAN_TXQ_MAPENA_TX_ENA_S 0
5297 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
5298 #define VSILAN_QBASE(_VSI) (0x0044C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
5300 #define VSILAN_QBASE_VSIBASE_S 0
5301 #define VSILAN_QBASE_VSIBASE_M MAKEMASK(0x7FF, 0)
5304 #define VSILAN_QTABLE(_i, _VSI) (0x00440000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...7, _VSI=0...767 */ /* Reset Source: PFR */
5306 #define VSILAN_QTABLE_QINDEX_0_S 0
5307 #define VSILAN_QTABLE_QINDEX_0_M MAKEMASK(0x7FF, 0)
5309 #define VSILAN_QTABLE_QINDEX_1_M MAKEMASK(0x7FF, 16)
5310 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E31C0 /* Reset Source: GLOBR */
5311 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0
5312 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)
5313 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E34C0 /* Reset Source: GLOBR */
5314 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0
5315 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
5316 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */
5317 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0
5318 #define E800_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
5319 #define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
5320 #define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
5321 #define E800_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
5322 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
5323 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
5324 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5325 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
5326 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
5327 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
5328 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
5329 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0
5330 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
5331 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */
5332 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0
5333 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5334 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E32A0 /* Reset Source: GLOBR */
5335 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0
5336 #define E800_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0)
5337 #define E800_PRTMAC_HSEC_CTL_RX_QUANTA_S 0x001E3C40 /* Reset Source: GLOBR */
5338 #define E800_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0
5339 #define E800_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0)
5340 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E31A0 /* Reset Source: GLOBR */
5341 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0
5342 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
5343 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
5345 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0
5346 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
5347 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
5349 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
5350 #define E800_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
5351 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E3960 /* Reset Source: GLOBR */
5352 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0
5353 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
5354 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E3980 /* Reset Source: GLOBR */
5355 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0
5356 #define E800_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0)
5358 #define E800_PRTMAC_LINK_DOWN_COUNTER 0x001E47C0 /* Reset Source: GLOBR */
5359 #define E830_PRTMAC_LINK_DOWN_COUNTER 0x001E2460 /* Reset Source: GLOBR */
5360 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_S 0
5361 #define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_M MAKEMASK(0xFFFF, 0)
5363 #define E800_PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
5364 #define E830_PRTMAC_MD_OVRRIDE_ENABLE(_i) (0x001E2500 + ((_i) * 32)) /* _i=0...1 */ /* Reset Source: GLOBR */
5368 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_S 0
5369 #define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
5371 #define E800_PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */
5372 #define E830_PRTMAC_MD_OVRRIDE_VAL(_i) (0x001E2600 + ((_i) * 32)) /* _i=0...1 */ /* Reset Source: GLOBR */
5376 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_S 0
5377 #define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)
5378 #define PRTMAC_RX_CNT_MRKR 0x001E48E0 /* Reset Source: GLOBR */
5379 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_S 0
5380 #define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
5382 #define E800_PRTMAC_RX_PKT_DRP_CNT 0x001E3C20 /* Reset Source: GLOBR */
5383 #define E830_PRTMAC_RX_PKT_DRP_CNT 0x001E2420 /* Reset Source: GLOBR */
5384 #define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_S 0
5386 #define E800_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 0)
5387 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M MAKEMASK(0xFFF, 0)
5392 #define E800_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16)
5393 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xF, 28)
5394 #define PRTMAC_TX_CNT_MRKR 0x001E48C0 /* Reset Source: GLOBR */
5395 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_S 0
5396 #define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_M MAKEMASK(0xFFFF, 0)
5398 #define E800_PRTMAC_TX_LNK_UP_CNT 0x001E4840 /* Reset Source: GLOBR */
5399 #define E830_PRTMAC_TX_LNK_UP_CNT 0x001E2480 /* Reset Source: GLOBR */
5400 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_S 0
5401 #define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_M MAKEMASK(0xFFFF, 0)
5402 #define GL_MDCK_CFG1_TX_PQM 0x002D2DF4 /* Reset Source: CORER */
5403 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_S 0
5404 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_M MAKEMASK(0xFF, 0)
5406 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_M MAKEMASK(0x3F, 8)
5408 #define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_M MAKEMASK(0x3F, 16)
5409 #define GL_MDCK_EN_TX_PQM 0x002D2DFC /* Reset Source: CORER */
5410 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_S 0
5411 #define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_M BIT(0)
5461 #define E800_GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)
5462 #define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
5463 #define GL_MDCK_RX_DESC_ADDR_S 0
5464 #define GL_MDCK_RX_DESC_ADDR_M BIT(0)
5465 #define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
5466 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
5467 #define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
5488 #define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
5489 #define GL_MDET_RX_QNUM_S 0
5490 #define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
5492 #define GL_MDET_RX_VF_NUM_M MAKEMASK(0xFF, 15)
5494 #define GL_MDET_RX_PF_NUM_M MAKEMASK(0x7, 23)
5496 #define GL_MDET_RX_MAL_TYPE_M MAKEMASK(0x1F, 26)
5499 #define GL_MDET_TX_PQM 0x002D2E00 /* Reset Source: CORER */
5500 #define GL_MDET_TX_PQM_PF_NUM_S 0
5501 #define GL_MDET_TX_PQM_PF_NUM_M MAKEMASK(0x7, 0)
5503 #define GL_MDET_TX_PQM_VF_NUM_M MAKEMASK(0xFF, 4)
5505 #define GL_MDET_TX_PQM_QNUM_M MAKEMASK(0x3FFF, 12)
5507 #define GL_MDET_TX_PQM_MAL_TYPE_M MAKEMASK(0x1F, 26)
5510 #define GL_MDET_TX_TCLAN 0x000FC068 /* Reset Source: CORER */
5511 #define GL_MDET_TX_TCLAN_QNUM_S 0
5512 #define GL_MDET_TX_TCLAN_QNUM_M MAKEMASK(0x7FFF, 0)
5514 #define GL_MDET_TX_TCLAN_VF_NUM_M MAKEMASK(0xFF, 15)
5516 #define GL_MDET_TX_TCLAN_PF_NUM_M MAKEMASK(0x7, 23)
5518 #define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26)
5521 #define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */
5522 #define GL_MDET_TX_TDPU_QNUM_S 0
5523 #define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
5525 #define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15)
5527 #define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23)
5529 #define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
5532 #define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */
5533 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0
5534 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)
5535 #define PF_MDET_RX 0x00294280 /* Reset Source: CORER */
5536 #define PF_MDET_RX_VALID_S 0
5537 #define PF_MDET_RX_VALID_M BIT(0)
5538 #define PF_MDET_TX_PQM 0x002D2C80 /* Reset Source: CORER */
5539 #define PF_MDET_TX_PQM_VALID_S 0
5540 #define PF_MDET_TX_PQM_VALID_M BIT(0)
5541 #define PF_MDET_TX_TCLAN 0x000FC000 /* Reset Source: CORER */
5542 #define PF_MDET_TX_TCLAN_VALID_S 0
5543 #define PF_MDET_TX_TCLAN_VALID_M BIT(0)
5544 #define PF_MDET_TX_TDPU 0x00040800 /* Reset Source: CORER */
5545 #define PF_MDET_TX_TDPU_VALID_S 0
5546 #define PF_MDET_TX_TDPU_VALID_M BIT(0)
5547 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5549 #define VP_MDET_RX_VALID_S 0
5550 #define VP_MDET_RX_VALID_M BIT(0)
5551 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5553 #define VP_MDET_TX_PQM_VALID_S 0
5554 #define VP_MDET_TX_PQM_VALID_M BIT(0)
5555 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5557 #define VP_MDET_TX_TCLAN_VALID_S 0
5558 #define VP_MDET_TX_TCLAN_VALID_M BIT(0)
5559 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
5561 #define VP_MDET_TX_TDPU_VALID_S 0
5562 #define VP_MDET_TX_TDPU_VALID_M BIT(0)
5563 #define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */
5565 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
5566 #define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
5567 #define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */
5568 #define GL_FWRESETCNT_FWRESETCNT_S 0
5569 #define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)
5571 #define E800_GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */
5572 #define E830_GL_MNG_FW_RAM_STAT 0x000830F4 /* Reset Source: POR */
5573 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0
5574 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)
5577 #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */
5578 #define GL_MNG_FWSM_FW_MODES_S 0
5580 #define E800_GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0)
5581 #define E830_GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x3, 0)
5586 #define E800_GL_MNG_FWSM_RSV0_M MAKEMASK(0x7F, 3)
5587 #define E830_GL_MNG_FWSM_RSV0_M MAKEMASK(0xFF, 2)
5591 #define GL_MNG_FWSM_RSV1_M MAKEMASK(0xF, 11)
5601 #define GL_MNG_FWSM_EXT_ERR_IND_M MAKEMASK(0x3F, 19)
5605 #define GL_MNG_FWSM_RESERVED_11_M MAKEMASK(0xF, 26)
5607 #define GL_MNG_FWSM_RSV5_M MAKEMASK(0x3, 30)
5608 #define GL_MNG_HWARB_CTRL 0x000B6130 /* Reset Source: POR */
5609 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_S 0
5610 #define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M BIT(0)
5612 #define E800_GL_MNG_SHA_EXTEND(_i) (0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
5613 #define E830_GL_MNG_SHA_EXTEND(_i) (0x00083340 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
5617 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_S 0
5618 #define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_M MAKEMASK(0xFFFFFFFF, 0)
5620 #define E800_GL_MNG_SHA_EXTEND_ROM(_i) (0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */
5621 #define E830_GL_MNG_SHA_EXTEND_ROM(_i) (0x000832C0 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
5625 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_S 0
5626 #define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_M MAKEMASK(0xFFFFFFFF, 0)
5627 #define GL_MNG_SHA_EXTEND_STATUS 0x00083148 /* Reset Source: EMPR */
5628 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_S 0
5629 #define GL_MNG_SHA_EXTEND_STATUS_STAGE_M MAKEMASK(0x7, 0)
5634 #define GL_SWT_PRT2MDEF(_i) (0x00216018 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: POR */
5636 #define GL_SWT_PRT2MDEF_MDEFIDX_S 0
5637 #define GL_SWT_PRT2MDEF_MDEFIDX_M MAKEMASK(0x7, 0)
5640 #define PRT_MNG_MANC 0x00214720 /* Reset Source: POR */
5641 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_S 0
5642 #define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_M BIT(0)
5657 #define PRT_MNG_MAVTV(_i) (0x00214780 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5659 #define PRT_MNG_MAVTV_VID_S 0
5660 #define PRT_MNG_MAVTV_VID_M MAKEMASK(0xFFF, 0)
5661 #define PRT_MNG_MDEF(_i) (0x00214880 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5663 #define PRT_MNG_MDEF_MAC_EXACT_AND_S 0
5664 #define PRT_MNG_MDEF_MAC_EXACT_AND_M MAKEMASK(0xF, 0)
5668 #define PRT_MNG_MDEF_VLAN_AND_M MAKEMASK(0xFF, 5)
5670 #define PRT_MNG_MDEF_IPV4_ADDRESS_AND_M MAKEMASK(0xF, 13)
5672 #define PRT_MNG_MDEF_IPV6_ADDRESS_AND_M MAKEMASK(0xF, 17)
5674 #define PRT_MNG_MDEF_MAC_EXACT_OR_M MAKEMASK(0xF, 21)
5689 #define PRT_MNG_MDEF_EXT(_i) (0x00214A00 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */
5691 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_S 0
5692 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_M MAKEMASK(0xF, 0)
5694 #define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_M MAKEMASK(0xF, 4)
5696 #define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_M MAKEMASK(0xFFFF, 8)
5713 #define PRT_MNG_MDEFVSI(_i) (0x00214980 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5715 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_S 0
5716 #define PRT_MNG_MDEFVSI_MDEFVSI_2N_M MAKEMASK(0xFFFF, 0)
5718 #define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_M MAKEMASK(0xFFFF, 16)
5719 #define PRT_MNG_METF(_i) (0x00214120 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5721 #define PRT_MNG_METF_ETYPE_S 0
5722 #define PRT_MNG_METF_ETYPE_M MAKEMASK(0xFFFF, 0)
5725 #define PRT_MNG_MFUTP(_i) (0x00214320 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */
5727 #define PRT_MNG_MFUTP_MFUTP_N_S 0
5728 #define PRT_MNG_MFUTP_MFUTP_N_M MAKEMASK(0xFFFF, 0)
5735 #define PRT_MNG_MIPAF4(_i) (0x002141A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5737 #define PRT_MNG_MIPAF4_MIPAF_S 0
5738 #define PRT_MNG_MIPAF4_MIPAF_M MAKEMASK(0xFFFFFFFF, 0)
5739 #define PRT_MNG_MIPAF6(_i) (0x00214520 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */
5741 #define PRT_MNG_MIPAF6_MIPAF_S 0
5742 #define PRT_MNG_MIPAF6_MIPAF_M MAKEMASK(0xFFFFFFFF, 0)
5743 #define PRT_MNG_MMAH(_i) (0x00214220 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5745 #define PRT_MNG_MMAH_MMAH_S 0
5746 #define PRT_MNG_MMAH_MMAH_M MAKEMASK(0xFFFF, 0)
5747 #define PRT_MNG_MMAL(_i) (0x002142A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */
5749 #define PRT_MNG_MMAL_MMAL_S 0
5750 #define PRT_MNG_MMAL_MMAL_M MAKEMASK(0xFFFFFFFF, 0)
5751 #define PRT_MNG_MNGONLY 0x00214740 /* Reset Source: POR */
5752 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_S 0
5753 #define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_M MAKEMASK(0xFF, 0)
5754 #define PRT_MNG_MSFM 0x00214760 /* Reset Source: POR */
5755 #define PRT_MNG_MSFM_PORT_26F_UDP_S 0
5756 #define PRT_MNG_MSFM_PORT_26F_UDP_M BIT(0)
5771 #define MSIX_PBA_PAGE(_i) (0x02E08000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */
5773 #define MSIX_PBA_PAGE_PENBIT_S 0
5774 #define MSIX_PBA_PAGE_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
5775 #define MSIX_PBA1(_i) (0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */
5777 #define MSIX_PBA1_PENBIT_S 0
5778 #define MSIX_PBA1_PENBIT_M MAKEMASK(0xFFFFFFFF, 0)
5779 #define MSIX_TADD_PAGE(_i) (0x02E00000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5781 #define MSIX_TADD_PAGE_MSIXTADD10_S 0
5782 #define MSIX_TADD_PAGE_MSIXTADD10_M MAKEMASK(0x3, 0)
5784 #define MSIX_TADD_PAGE_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
5785 #define MSIX_TADD1(_i) (0x00000000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5787 #define MSIX_TADD1_MSIXTADD10_S 0
5788 #define MSIX_TADD1_MSIXTADD10_M MAKEMASK(0x3, 0)
5790 #define MSIX_TADD1_MSIXTADD_M MAKEMASK(0x3FFFFFFF, 2)
5791 #define MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5793 #define MSIX_TMSG_MSIXTMSG_S 0
5794 #define MSIX_TMSG_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
5795 #define MSIX_TMSG_PAGE(_i) (0x02E00008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5797 #define MSIX_TMSG_PAGE_MSIXTMSG_S 0
5798 #define MSIX_TMSG_PAGE_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
5799 #define MSIX_TUADD_PAGE(_i) (0x02E00004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5801 #define MSIX_TUADD_PAGE_MSIXTUADD_S 0
5802 #define MSIX_TUADD_PAGE_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
5803 #define MSIX_TUADD1(_i) (0x00000004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5805 #define MSIX_TUADD1_MSIXTUADD_S 0
5806 #define MSIX_TUADD1_MSIXTUADD_M MAKEMASK(0xFFFFFFFF, 0)
5807 #define MSIX_TVCTRL_PAGE(_i) (0x02E0000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5809 #define MSIX_TVCTRL_PAGE_MASK_S 0
5810 #define MSIX_TVCTRL_PAGE_MASK_M BIT(0)
5811 #define MSIX_TVCTRL1(_i) (0x0000000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */
5813 #define MSIX_TVCTRL1_MASK_S 0
5814 #define MSIX_TVCTRL1_MASK_M BIT(0)
5815 #define GLNVM_AL_DONE_HLP 0x000824C4 /* Reset Source: POR */
5816 #define GLNVM_AL_DONE_HLP_HLP_CORER_S 0
5817 #define GLNVM_AL_DONE_HLP_HLP_CORER_M BIT(0)
5820 #define GLNVM_ALTIMERS 0x000B6140 /* Reset Source: POR */
5821 #define GLNVM_ALTIMERS_PCI_ALTIMER_S 0
5822 #define GLNVM_ALTIMERS_PCI_ALTIMER_M MAKEMASK(0xFFF, 0)
5824 #define GLNVM_ALTIMERS_GEN_ALTIMER_M MAKEMASK(0xFFFFF, 12)
5825 #define GLNVM_FLA 0x000B6108 /* Reset Source: POR */
5828 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */
5829 #define GLNVM_GENS_NVM_PRES_S 0
5830 #define GLNVM_GENS_NVM_PRES_M BIT(0)
5832 #define GLNVM_GENS_SR_SIZE_M MAKEMASK(0x7, 5)
5839 #define GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset Source: POR */
5841 #define GLNVM_PROTCSR_ADDR_BLOCK_S 0
5842 #define GLNVM_PROTCSR_ADDR_BLOCK_M MAKEMASK(0xFFFFFF, 0)
5843 #define GLNVM_ULD 0x000B6008 /* Reset Source: POR */
5844 #define GLNVM_ULD_PCIER_DONE_S 0
5845 #define GLNVM_ULD_PCIER_DONE_M BIT(0)
5864 #define GLNVM_ULT 0x000B6154 /* Reset Source: POR */
5865 #define GLNVM_ULT_CONF_PCIR_AE_S 0
5866 #define GLNVM_ULT_CONF_PCIR_AE_M BIT(0)
5888 #define GLNVM_ULT_RESERVED_4_M MAKEMASK(0x1FFFFF, 11)
5889 #define GL_COTF_MARKER_STATUS 0x00200200 /* Reset Source: CORER */
5890 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_S 0
5891 #define GL_COTF_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFF, 0)
5892 #define GL_COTF_MARKER_TRIG_RCU_PRS(_i) (0x002001D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
5894 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_S 0
5895 #define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_M BIT(0)
5896 #define GL_PRS_MARKER_ERROR 0x00200204 /* Reset Source: CORER */
5897 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_S 0
5898 #define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_M BIT(0)
5903 #define GL_PRS_RX_PIPE_INIT0(_i) (0x0020000C + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
5905 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_S 0
5906 #define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5907 #define GL_PRS_RX_PIPE_INIT1 0x00200028 /* Reset Source: CORER */
5908 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_S 0
5909 #define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5910 #define GL_PRS_RX_PIPE_INIT2 0x0020002C /* Reset Source: CORER */
5911 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_S 0
5912 #define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5913 #define GL_PRS_RX_SIZE_CTRL 0x00200004 /* Reset Source: CORER */
5914 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_S 0
5915 #define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0)
5919 #define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16)
5922 #define GL_PRS_TX_PIPE_INIT0(_i) (0x00202018 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
5924 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_S 0
5925 #define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5926 #define GL_PRS_TX_PIPE_INIT1 0x00202034 /* Reset Source: CORER */
5927 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_S 0
5928 #define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5929 #define GL_PRS_TX_PIPE_INIT2 0x00202038 /* Reset Source: CORER */
5930 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_S 0
5931 #define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_M MAKEMASK(0xFFFF, 0)
5932 #define GL_PRS_TX_SIZE_CTRL 0x00202014 /* Reset Source: CORER */
5933 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_S 0
5934 #define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_M MAKEMASK(0x3FF, 0)
5938 #define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_M MAKEMASK(0x3FF, 16)
5941 #define GL_QH_MARKER_STATUS 0x002001FC /* Reset Source: CORER */
5942 #define GL_QH_MARKER_STATUS_MRKR_BUSY_S 0
5943 #define GL_QH_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xF, 0)
5944 #define GL_QH_MARKER_TRIG_RCU_PRS(_i) (0x002001C4 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
5946 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_S 0
5947 #define GL_QH_MARKER_TRIG_RCU_PRS_QPID_M MAKEMASK(0x3FFFF, 0)
5949 #define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_M MAKEMASK(0xFF, 18)
5951 #define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 26)
5954 #define GL_RPRS_ANA_CSR_CTRL 0x00200708 /* Reset Source: CORER */
5955 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_S 0
5956 #define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
5959 #define GL_TPRS_ANA_CSR_CTRL 0x00202100 /* Reset Source: CORER */
5960 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_S 0
5961 #define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_M BIT(0)
5964 #define GL_TPRS_MNG_PM_THR 0x00202004 /* Reset Source: CORER */
5965 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_S 0
5966 #define GL_TPRS_MNG_PM_THR_MNG_PM_THR_M MAKEMASK(0x3FFF, 0)
5967 #define GL_TPRS_PM_CNT(_i) (0x00202008 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
5969 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_S 0
5970 #define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_M MAKEMASK(0x3FFF, 0)
5971 #define GL_TPRS_PM_THR 0x00202000 /* Reset Source: CORER */
5972 #define GL_TPRS_PM_THR_PM_THR_S 0
5973 #define GL_TPRS_PM_THR_PM_THR_M MAKEMASK(0x3FFF, 0)
5974 #define GL_XLR_MARKER_LOG_RCU_PRS(_i) (0x00200208 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
5976 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_S 0
5977 #define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_M MAKEMASK(0xFFFFFFFF, 0)
5978 #define GL_XLR_MARKER_STATUS(_i) (0x002001F4 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
5980 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_S 0
5981 #define GL_XLR_MARKER_STATUS_MRKR_BUSY_M MAKEMASK(0xFFFFFFFF, 0)
5982 #define GL_XLR_MARKER_TRIG_PE 0x005008C0 /* Reset Source: CORER */
5983 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_S 0
5984 #define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
5986 #define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M MAKEMASK(0x3, 10)
5988 #define GL_XLR_MARKER_TRIG_PE_PF_NUM_M MAKEMASK(0x7, 12)
5990 #define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M MAKEMASK(0x7, 16)
5991 #define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */
5992 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0
5993 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
5995 #define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
5997 #define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12)
5999 #define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 16)
6000 #define GL_CLKGATE_EVENTS 0x0009DE70 /* Reset Source: PERST */
6001 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0
6002 #define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0)
6004 #define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 16)
6005 #define GLPCI_BYTCTH_NP_C 0x000BFDA8 /* Reset Source: PCIR */
6006 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_S 0
6007 #define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
6008 #define GLPCI_BYTCTH_P 0x0009E970 /* Reset Source: PCIR */
6009 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_S 0
6010 #define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
6011 #define GLPCI_BYTCTL_NP_C 0x000BFDAC /* Reset Source: PCIR */
6012 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_S 0
6013 #define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
6014 #define GLPCI_BYTCTL_P 0x0009E994 /* Reset Source: PCIR */
6015 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_S 0
6016 #define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_M MAKEMASK(0xFFFFFFFF, 0)
6017 #define GLPCI_CAPCTRL 0x0009DE88 /* Reset Source: PCIR */
6018 #define GLPCI_CAPCTRL_VPD_EN_S 0
6019 #define GLPCI_CAPCTRL_VPD_EN_M BIT(0)
6020 #define GLPCI_CAPSUP 0x0009DE8C /* Reset Source: PCIR */
6021 #define GLPCI_CAPSUP_PCIE_VER_S 0
6022 #define GLPCI_CAPSUP_PCIE_VER_M BIT(0)
6061 #define GLPCI_CNF 0x0009DEA0 /* Reset Source: POR */
6068 #define GLPCI_CNF2 0x000BE004 /* Reset Source: PCIR */
6069 #define GLPCI_CNF2_RO_DIS_S 0
6070 #define GLPCI_CNF2_RO_DIS_M BIT(0)
6073 #define GLPCI_DREVID 0x0009E9AC /* Reset Source: PCIR */
6074 #define GLPCI_DREVID_DEFAULT_REVID_S 0
6075 #define GLPCI_DREVID_DEFAULT_REVID_M MAKEMASK(0xFF, 0)
6076 #define GLPCI_GSCL_1_NP_C 0x000BFDA4 /* Reset Source: PCIR */
6080 #define GLPCI_GSCL_1_NP_C_RT_EVENT_M MAKEMASK(0x1F, 9)
6084 #define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_M MAKEMASK(0x1F, 15)
6091 #define GLPCI_GSCL_1_P 0x0009E9B4 /* Reset Source: PCIR */
6092 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_S 0
6093 #define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_M BIT(0)
6118 #define GLPCI_GSCL_2 0x0009E998 /* Reset Source: PCIR */
6119 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_S 0
6120 #define GLPCI_GSCL_2_GIO_EVENT_NUM_0_M MAKEMASK(0xFF, 0)
6122 #define GLPCI_GSCL_2_GIO_EVENT_NUM_1_M MAKEMASK(0xFF, 8)
6124 #define GLPCI_GSCL_2_GIO_EVENT_NUM_2_M MAKEMASK(0xFF, 16)
6126 #define GLPCI_GSCL_2_GIO_EVENT_NUM_3_M MAKEMASK(0xFF, 24)
6127 #define GLPCI_GSCL_5_8(_i) (0x0009E954 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */
6129 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_S 0
6130 #define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_M MAKEMASK(0xFFFF, 0)
6132 #define GLPCI_GSCL_5_8_LBC_TIMER_N_M MAKEMASK(0xFFFF, 16)
6133 #define GLPCI_GSCN_0_3(_i) (0x0009E99C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */
6135 #define GLPCI_GSCN_0_3_EVENT_COUNTER_S 0
6136 #define GLPCI_GSCN_0_3_EVENT_COUNTER_M MAKEMASK(0xFFFFFFFF, 0)
6137 #define GLPCI_LATCT_NP_C 0x000BFDA0 /* Reset Source: PCIR */
6138 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_S 0
6139 #define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_M MAKEMASK(0xFFFFFFFF, 0)
6140 #define GLPCI_LBARCTRL 0x0009DE74 /* Reset Source: POR */
6141 #define GLPCI_LBARCTRL_PREFBAR_S 0
6142 #define GLPCI_LBARCTRL_PREFBAR_M BIT(0)
6150 #define GLPCI_LBARCTRL_PE_DB_SIZE_M MAKEMASK(0x3, 4)
6154 #define GLPCI_LBARCTRL_EXROM_SIZE_M MAKEMASK(0x7, 11)
6156 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_M MAKEMASK(0x3, 14)
6157 #define GLPCI_LINKCAP 0x0009DE90 /* Reset Source: PCIR */
6158 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_S 0
6159 #define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_M MAKEMASK(0x3F, 0)
6161 #define GLPCI_LINKCAP_MAX_LINK_WIDTH_M MAKEMASK(0xF, 9)
6162 #define GLPCI_NPQ_CFG 0x000BFD80 /* Reset Source: PCIR */
6163 #define GLPCI_NPQ_CFG_EXTEND_TO_S 0
6164 #define GLPCI_NPQ_CFG_EXTEND_TO_M BIT(0)
6168 #define GLPCI_NPQ_CFG_WEIGHT_AVG_M MAKEMASK(0xF, 2)
6170 #define GLPCI_NPQ_CFG_NPQ_SPARE_M MAKEMASK(0x3FF, 6)
6172 #define GLPCI_NPQ_CFG_NPQ_ERR_STAT_M MAKEMASK(0xF, 16)
6173 #define GLPCI_PKTCT_NP_C 0x000BFD9C /* Reset Source: PCIR */
6174 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_S 0
6175 #define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0)
6176 #define GLPCI_PKTCT_P 0x0009E9B0 /* Reset Source: PCIR */
6177 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_S 0
6178 #define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_M MAKEMASK(0xFFFFFFFF, 0)
6179 #define GLPCI_PMSUP 0x0009DE94 /* Reset Source: PCIR */
6180 #define GLPCI_PMSUP_RESERVED_0_S 0
6181 #define GLPCI_PMSUP_RESERVED_0_M MAKEMASK(0x3, 0)
6183 #define GLPCI_PMSUP_RESERVED_1_M MAKEMASK(0x7, 2)
6185 #define GLPCI_PMSUP_RESERVED_2_M MAKEMASK(0x7, 5)
6187 #define GLPCI_PMSUP_L0S_ACC_LAT_M MAKEMASK(0x7, 8)
6189 #define GLPCI_PMSUP_L1_ACC_LAT_M MAKEMASK(0x7, 11)
6193 #define GLPCI_PMSUP_OBFF_SUP_M MAKEMASK(0x3, 15)
6194 #define GLPCI_PUSH_PE_IF_TO_STATUS 0x0009DF44 /* Reset Source: PCIR */
6195 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_S 0
6196 #define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_M BIT(0)
6197 #define GLPCI_PWRDATA 0x0009DE7C /* Reset Source: PCIR */
6198 #define GLPCI_PWRDATA_D0_POWER_S 0
6199 #define GLPCI_PWRDATA_D0_POWER_M MAKEMASK(0xFF, 0)
6201 #define GLPCI_PWRDATA_COMM_POWER_M MAKEMASK(0xFF, 8)
6203 #define GLPCI_PWRDATA_D3_POWER_M MAKEMASK(0xFF, 16)
6205 #define GLPCI_PWRDATA_DATA_SCALE_M MAKEMASK(0x3, 24)
6206 #define GLPCI_REVID 0x0009DE98 /* Reset Source: PCIR */
6207 #define GLPCI_REVID_NVM_REVID_S 0
6208 #define GLPCI_REVID_NVM_REVID_M MAKEMASK(0xFF, 0)
6209 #define GLPCI_SERH 0x0009DE84 /* Reset Source: PCIR */
6210 #define GLPCI_SERH_SER_NUM_H_S 0
6211 #define GLPCI_SERH_SER_NUM_H_M MAKEMASK(0xFFFF, 0)
6212 #define GLPCI_SERL 0x0009DE80 /* Reset Source: PCIR */
6213 #define GLPCI_SERL_SER_NUM_L_S 0
6214 #define GLPCI_SERL_SER_NUM_L_M MAKEMASK(0xFFFFFFFF, 0)
6215 #define GLPCI_SUBVENID 0x0009DEE8 /* Reset Source: PCIR */
6216 #define GLPCI_SUBVENID_SUB_VEN_ID_S 0
6217 #define GLPCI_SUBVENID_SUB_VEN_ID_M MAKEMASK(0xFFFF, 0)
6218 #define GLPCI_UPADD 0x000BE0D4 /* Reset Source: PCIR */
6220 #define GLPCI_UPADD_ADDRESS_M MAKEMASK(0x7FFFFFFF, 1)
6221 #define GLPCI_VENDORID 0x0009DEC8 /* Reset Source: PCIR */
6222 #define GLPCI_VENDORID_VENDORID_S 0
6223 #define GLPCI_VENDORID_VENDORID_M MAKEMASK(0xFFFF, 0)
6224 #define GLPCI_VFSUP 0x0009DE9C /* Reset Source: PCIR */
6225 #define GLPCI_VFSUP_VF_PREFETCH_S 0
6226 #define GLPCI_VFSUP_VF_PREFETCH_M BIT(0)
6229 #define GLPCI_WATMK_CLNT_PIPEMON 0x000BFD90 /* Reset Source: PCIR */
6230 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_S 0
6231 #define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_M MAKEMASK(0xFFFF, 0)
6232 #define PF_FUNC_RID 0x0009E880 /* Reset Source: PCIR */
6233 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0
6234 #define PF_FUNC_RID_FUNCTION_NUMBER_M MAKEMASK(0x7, 0)
6236 #define PF_FUNC_RID_DEVICE_NUMBER_M MAKEMASK(0x1F, 3)
6238 #define PF_FUNC_RID_BUS_NUMBER_M MAKEMASK(0xFF, 8)
6239 #define PF_PCI_CIAA 0x0009E580 /* Reset Source: FLR */
6240 #define PF_PCI_CIAA_ADDRESS_S 0
6241 #define PF_PCI_CIAA_ADDRESS_M MAKEMASK(0xFFF, 0)
6243 #define PF_PCI_CIAA_VF_NUM_M MAKEMASK(0xFF, 12)
6244 #define PF_PCI_CIAD 0x0009E500 /* Reset Source: FLR */
6245 #define PF_PCI_CIAD_DATA_S 0
6246 #define PF_PCI_CIAD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
6247 #define PFPCI_CLASS 0x0009DB00 /* Reset Source: PCIR */
6248 #define PFPCI_CLASS_STORAGE_CLASS_S 0
6249 #define PFPCI_CLASS_STORAGE_CLASS_M BIT(0)
6252 #define PFPCI_CNF 0x0009DF00 /* Reset Source: PCIR */
6260 #define PFPCI_CNF_INT_PIN_M MAKEMASK(0x3, 5)
6261 #define PFPCI_DEVID 0x0009DE00 /* Reset Source: PCIR */
6262 #define PFPCI_DEVID_PF_DEV_ID_S 0
6263 #define PFPCI_DEVID_PF_DEV_ID_M MAKEMASK(0xFFFF, 0)
6265 #define PFPCI_DEVID_VF_DEV_ID_M MAKEMASK(0xFFFF, 16)
6266 #define PFPCI_FACTPS 0x0009E900 /* Reset Source: FLR */
6267 #define PFPCI_FACTPS_FUNC_POWER_STATE_S 0
6268 #define PFPCI_FACTPS_FUNC_POWER_STATE_M MAKEMASK(0x3, 0)
6271 #define PFPCI_FUNC 0x0009D980 /* Reset Source: POR */
6272 #define PFPCI_FUNC_FUNC_DIS_S 0
6273 #define PFPCI_FUNC_FUNC_DIS_M BIT(0)
6278 #define PFPCI_PF_FLUSH_DONE 0x0009E400 /* Reset Source: PCIR */
6279 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_S 0
6280 #define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6281 #define PFPCI_PM 0x0009DA80 /* Reset Source: POR */
6282 #define PFPCI_PM_PME_EN_S 0
6283 #define PFPCI_PM_PME_EN_M BIT(0)
6284 #define PFPCI_STATUS1 0x0009DA00 /* Reset Source: POR */
6285 #define PFPCI_STATUS1_FUNC_VALID_S 0
6286 #define PFPCI_STATUS1_FUNC_VALID_M BIT(0)
6287 #define PFPCI_SUBSYSID 0x0009D880 /* Reset Source: PCIR */
6288 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_S 0
6289 #define PFPCI_SUBSYSID_PF_SUBSYS_ID_M MAKEMASK(0xFFFF, 0)
6291 #define PFPCI_SUBSYSID_VF_SUBSYS_ID_M MAKEMASK(0xFFFF, 16)
6292 #define PFPCI_VF_FLUSH_DONE(_VF) (0x0009E000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */
6294 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_S 0
6295 #define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6296 #define PFPCI_VM_FLUSH_DONE 0x0009E480 /* Reset Source: PCIR */
6297 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_S 0
6298 #define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_M BIT(0)
6299 #define PFPCI_VMINDEX 0x0009E600 /* Reset Source: PCIR */
6300 #define PFPCI_VMINDEX_VMINDEX_S 0
6301 #define PFPCI_VMINDEX_VMINDEX_M MAKEMASK(0x3FF, 0)
6302 #define PFPCI_VMPEND 0x0009E800 /* Reset Source: PCIR */
6303 #define PFPCI_VMPEND_PENDING_S 0
6304 #define PFPCI_VMPEND_PENDING_M BIT(0)
6305 #define PQ_FIFO_STATUS 0x0009DF40 /* Reset Source: PCIR */
6306 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_S 0
6307 #define PQ_FIFO_STATUS_PQ_FIFO_COUNT_M MAKEMASK(0x7FFFFFFF, 0)
6310 #define GLPE_CPUSTATUS0 0x0050BA5C /* Reset Source: CORER */
6311 #define GLPE_CPUSTATUS0_PECPUSTATUS0_S 0
6312 #define GLPE_CPUSTATUS0_PECPUSTATUS0_M MAKEMASK(0xFFFFFFFF, 0)
6313 #define GLPE_CPUSTATUS1 0x0050BA60 /* Reset Source: CORER */
6314 #define GLPE_CPUSTATUS1_PECPUSTATUS1_S 0
6315 #define GLPE_CPUSTATUS1_PECPUSTATUS1_M MAKEMASK(0xFFFFFFFF, 0)
6316 #define GLPE_CPUSTATUS2 0x0050BA64 /* Reset Source: CORER */
6317 #define GLPE_CPUSTATUS2_PECPUSTATUS2_S 0
6318 #define GLPE_CPUSTATUS2_PECPUSTATUS2_M MAKEMASK(0xFFFFFFFF, 0)
6319 #define GLPE_MDQ_BASE(_i) (0x00536000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6321 #define GLPE_MDQ_BASE_MDOC_INDEX_S 0
6322 #define GLPE_MDQ_BASE_MDOC_INDEX_M MAKEMASK(0xFFFFFFF, 0)
6323 #define GLPE_MDQ_PTR(_i) (0x00537000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6325 #define GLPE_MDQ_PTR_MDQ_HEAD_S 0
6326 #define GLPE_MDQ_PTR_MDQ_HEAD_M MAKEMASK(0x3FFF, 0)
6328 #define GLPE_MDQ_PTR_MDQ_TAIL_M MAKEMASK(0x3FFF, 16)
6329 #define GLPE_MDQ_SIZE(_i) (0x00536800 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */
6331 #define GLPE_MDQ_SIZE_MDQ_SIZE_S 0
6332 #define GLPE_MDQ_SIZE_MDQ_SIZE_M MAKEMASK(0x3FFF, 0)
6333 #define GLPE_PEPM_CTRL 0x0050C000 /* Reset Source: PERST */
6334 #define GLPE_PEPM_CTRL_PEPM_ENABLE_S 0
6335 #define GLPE_PEPM_CTRL_PEPM_ENABLE_M BIT(0)
6339 #define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_M MAKEMASK(0xFF, 16)
6340 #define GLPE_PEPM_DEALLOC 0x0050C004 /* Reset Source: PERST */
6341 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_S 0
6342 #define GLPE_PEPM_DEALLOC_MDQ_CREDITS_M MAKEMASK(0x3FFF, 0)
6344 #define GLPE_PEPM_DEALLOC_PSQ_CREDITS_M MAKEMASK(0x1F, 14)
6346 #define GLPE_PEPM_DEALLOC_PQID_M MAKEMASK(0x1FF, 19)
6348 #define GLPE_PEPM_DEALLOC_PORT_M MAKEMASK(0x7, 28)
6351 #define GLPE_PEPM_PSQ_COUNT 0x0050C020 /* Reset Source: PERST */
6352 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_S 0
6353 #define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0xFFFF, 0)
6354 #define GLPE_PEPM_THRESH(_i) (0x0050C840 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */
6356 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_S 0
6357 #define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_M MAKEMASK(0x1F, 0)
6359 #define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_M MAKEMASK(0x3FFF, 16)
6360 #define GLPE_PFAEQEDROPCNT(_i) (0x00503240 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6362 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_S 0
6363 #define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6364 #define GLPE_PFCEQEDROPCNT(_i) (0x00503220 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6366 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_S 0
6367 #define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6368 #define GLPE_PFCQEDROPCNT(_i) (0x00503200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6370 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_S 0
6371 #define GLPE_PFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6372 #define GLPE_PFFLMOOISCALLOCERR(_i) (0x0050B960 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6374 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_S 0
6375 #define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6376 #define GLPE_PFFLMQ1ALLOCERR(_i) (0x0050B920 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6378 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_S 0
6379 #define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6380 #define GLPE_PFFLMRRFALLOCERR(_i) (0x0050B940 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6382 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_S 0
6383 #define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6384 #define GLPE_PFFLMXMITALLOCERR(_i) (0x0050B900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6386 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_S 0
6387 #define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6388 #define GLPE_PFTCPNOW50USCNT(_i) (0x0050B8C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
6390 #define GLPE_PFTCPNOW50USCNT_CNT_S 0
6391 #define GLPE_PFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
6392 #define GLPE_PUSH_PEPM 0x0053241C /* Reset Source: CORER */
6393 #define GLPE_PUSH_PEPM_MDQ_CREDITS_S 0
6394 #define GLPE_PUSH_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0)
6395 #define GLPE_VFAEQEDROPCNT(_i) (0x00503100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6397 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_S 0
6398 #define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6399 #define GLPE_VFCEQEDROPCNT(_i) (0x00503080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6401 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_S 0
6402 #define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6403 #define GLPE_VFCQEDROPCNT(_i) (0x00503000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6405 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_S 0
6406 #define GLPE_VFCQEDROPCNT_CQEDROPCNT_M MAKEMASK(0xFFFF, 0)
6407 #define GLPE_VFFLMOOISCALLOCERR(_i) (0x0050B580 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6409 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_S 0
6410 #define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6411 #define GLPE_VFFLMQ1ALLOCERR(_i) (0x0050B480 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6413 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_S 0
6414 #define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6415 #define GLPE_VFFLMRRFALLOCERR(_i) (0x0050B500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6417 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_S 0
6418 #define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6419 #define GLPE_VFFLMXMITALLOCERR(_i) (0x0050B400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
6421 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_S 0
6422 #define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_M MAKEMASK(0xFFFF, 0)
6423 #define GLPE_VFTCPNOW50USCNT(_i) (0x0050B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: PE_CORER */
6425 #define GLPE_VFTCPNOW50USCNT_CNT_S 0
6426 #define GLPE_VFTCPNOW50USCNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
6427 #define PFPE_AEQALLOC 0x00502D00 /* Reset Source: PFR */
6428 #define PFPE_AEQALLOC_AECOUNT_S 0
6429 #define PFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
6430 #define PFPE_CCQPHIGH 0x0050A100 /* Reset Source: PFR */
6431 #define PFPE_CCQPHIGH_PECCQPHIGH_S 0
6432 #define PFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
6433 #define PFPE_CCQPLOW 0x0050A080 /* Reset Source: PFR */
6434 #define PFPE_CCQPLOW_PECCQPLOW_S 0
6435 #define PFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
6436 #define PFPE_CCQPSTATUS 0x0050A000 /* Reset Source: PFR */
6437 #define PFPE_CCQPSTATUS_CCQP_DONE_S 0
6438 #define PFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
6440 #define PFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4)
6442 #define PFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
6445 #define PFPE_CQACK 0x00502C80 /* Reset Source: PFR */
6446 #define PFPE_CQACK_PECQID_S 0
6447 #define PFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0)
6448 #define PFPE_CQARM 0x00502C00 /* Reset Source: PFR */
6449 #define PFPE_CQARM_PECQID_S 0
6450 #define PFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0)
6451 #define PFPE_CQPDB 0x00500800 /* Reset Source: PFR */
6452 #define PFPE_CQPDB_WQHEAD_S 0
6453 #define PFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0)
6454 #define PFPE_CQPERRCODES 0x0050A200 /* Reset Source: PFR */
6455 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_S 0
6456 #define PFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
6458 #define PFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
6459 #define PFPE_CQPTAIL 0x00500880 /* Reset Source: PFR */
6460 #define PFPE_CQPTAIL_WQTAIL_S 0
6461 #define PFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0)
6464 #define PFPE_IPCONFIG0 0x0050A180 /* Reset Source: PFR */
6465 #define PFPE_IPCONFIG0_PEIPID_S 0
6466 #define PFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0)
6471 #define PFPE_MRTEIDXMASK 0x0050A300 /* Reset Source: PFR */
6472 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
6473 #define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
6474 #define E800_PFPE_RCVUNEXPECTEDERROR 0x0050A380 /* Reset Source: PFR */
6475 #define E800_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
6476 #define E800_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
6477 #define PFPE_TCPNOWTIMER 0x0050A280 /* Reset Source: PFR */
6478 #define PFPE_TCPNOWTIMER_TCP_NOW_S 0
6479 #define PFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
6480 #define PFPE_WQEALLOC 0x00504400 /* Reset Source: PFR */
6481 #define PFPE_WQEALLOC_PEQPID_S 0
6482 #define PFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0)
6484 #define PFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
6485 #define PRT_PEPM_COUNT(_i) (0x0050C040 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */
6487 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_S 0
6488 #define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_M MAKEMASK(0x1F, 0)
6490 #define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_M MAKEMASK(0x3FFF, 16)
6491 #define VFPE_AEQALLOC(_VF) (0x00502800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6493 #define VFPE_AEQALLOC_AECOUNT_S 0
6494 #define VFPE_AEQALLOC_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
6495 #define VFPE_CCQPHIGH(_VF) (0x00508800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6497 #define VFPE_CCQPHIGH_PECCQPHIGH_S 0
6498 #define VFPE_CCQPHIGH_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
6499 #define VFPE_CCQPLOW(_VF) (0x00508400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6501 #define VFPE_CCQPLOW_PECCQPLOW_S 0
6502 #define VFPE_CCQPLOW_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
6503 #define VFPE_CCQPSTATUS(_VF) (0x00508000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6505 #define VFPE_CCQPSTATUS_CCQP_DONE_S 0
6506 #define VFPE_CCQPSTATUS_CCQP_DONE_M BIT(0)
6508 #define VFPE_CCQPSTATUS_HMC_PROFILE_M MAKEMASK(0x7, 4)
6510 #define VFPE_CCQPSTATUS_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
6513 #define VFPE_CQACK(_VF) (0x00502400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6515 #define VFPE_CQACK_PECQID_S 0
6516 #define VFPE_CQACK_PECQID_M MAKEMASK(0x7FFFF, 0)
6517 #define VFPE_CQARM(_VF) (0x00502000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6519 #define VFPE_CQARM_PECQID_S 0
6520 #define VFPE_CQARM_PECQID_M MAKEMASK(0x7FFFF, 0)
6521 #define VFPE_CQPDB(_VF) (0x00500000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6523 #define VFPE_CQPDB_WQHEAD_S 0
6524 #define VFPE_CQPDB_WQHEAD_M MAKEMASK(0x7FF, 0)
6525 #define VFPE_CQPERRCODES(_VF) (0x00509000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6527 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_S 0
6528 #define VFPE_CQPERRCODES_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
6530 #define VFPE_CQPERRCODES_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
6531 #define VFPE_CQPTAIL(_VF) (0x00500400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6533 #define VFPE_CQPTAIL_WQTAIL_S 0
6534 #define VFPE_CQPTAIL_WQTAIL_M MAKEMASK(0x7FF, 0)
6537 #define VFPE_IPCONFIG0(_VF) (0x00508C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6539 #define VFPE_IPCONFIG0_PEIPID_S 0
6540 #define VFPE_IPCONFIG0_PEIPID_M MAKEMASK(0xFFFF, 0)
6545 #define E800_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6547 #define E800_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0
6548 #define E800_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
6549 #define VFPE_TCPNOWTIMER(_VF) (0x00509400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6551 #define VFPE_TCPNOWTIMER_TCP_NOW_S 0
6552 #define VFPE_TCPNOWTIMER_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
6553 #define VFPE_WQEALLOC(_VF) (0x00504000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
6555 #define VFPE_WQEALLOC_PEQPID_S 0
6556 #define VFPE_WQEALLOC_PEQPID_M MAKEMASK(0x3FFFF, 0)
6558 #define VFPE_WQEALLOC_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
6559 #define GLPES_PFIP4RXDISCARD(_i) (0x00541400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6561 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_S 0
6562 #define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0)
6563 #define GLPES_PFIP4RXFRAGSHI(_i) (0x00541C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6565 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S 0
6566 #define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6567 #define GLPES_PFIP4RXFRAGSLO(_i) (0x00541C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6569 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S 0
6570 #define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6571 #define GLPES_PFIP4RXMCOCTSHI(_i) (0x00542404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6573 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S 0
6574 #define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6575 #define GLPES_PFIP4RXMCOCTSLO(_i) (0x00542400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6577 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S 0
6578 #define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6579 #define GLPES_PFIP4RXMCPKTSHI(_i) (0x00542C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6581 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S 0
6582 #define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6583 #define GLPES_PFIP4RXMCPKTSLO(_i) (0x00542C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6585 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S 0
6586 #define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6587 #define GLPES_PFIP4RXOCTSHI(_i) (0x00540404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6589 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S 0
6590 #define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_M MAKEMASK(0xFFFF, 0)
6591 #define GLPES_PFIP4RXOCTSLO(_i) (0x00540400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6593 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S 0
6594 #define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6595 #define GLPES_PFIP4RXPKTSHI(_i) (0x00540C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6597 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S 0
6598 #define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_M MAKEMASK(0xFFFF, 0)
6599 #define GLPES_PFIP4RXPKTSLO(_i) (0x00540C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6601 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S 0
6602 #define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6603 #define GLPES_PFIP4RXTRUNC(_i) (0x00541800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6605 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_S 0
6606 #define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0)
6607 #define GLPES_PFIP4TXFRAGSHI(_i) (0x00547404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6609 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S 0
6610 #define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6611 #define GLPES_PFIP4TXFRAGSLO(_i) (0x00547400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6613 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S 0
6614 #define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6615 #define GLPES_PFIP4TXMCOCTSHI(_i) (0x00547C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6617 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S 0
6618 #define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6619 #define GLPES_PFIP4TXMCOCTSLO(_i) (0x00547C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6621 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S 0
6622 #define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6623 #define GLPES_PFIP4TXMCPKTSHI(_i) (0x00548404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6625 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S 0
6626 #define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6627 #define GLPES_PFIP4TXMCPKTSLO(_i) (0x00548400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6629 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S 0
6630 #define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6631 #define GLPES_PFIP4TXNOROUTE(_i) (0x0054B400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6633 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_S 0
6634 #define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_M MAKEMASK(0xFFFFFF, 0)
6635 #define GLPES_PFIP4TXOCTSHI(_i) (0x00546404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6637 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S 0
6638 #define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_M MAKEMASK(0xFFFF, 0)
6639 #define GLPES_PFIP4TXOCTSLO(_i) (0x00546400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6641 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S 0
6642 #define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6643 #define GLPES_PFIP4TXPKTSHI(_i) (0x00546C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6645 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S 0
6646 #define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_M MAKEMASK(0xFFFF, 0)
6647 #define GLPES_PFIP4TXPKTSLO(_i) (0x00546C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6649 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S 0
6650 #define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6651 #define GLPES_PFIP6RXDISCARD(_i) (0x00544400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6653 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_S 0
6654 #define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_M MAKEMASK(0xFFFFFFFF, 0)
6655 #define GLPES_PFIP6RXFRAGSHI(_i) (0x00544C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6657 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S 0
6658 #define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6659 #define GLPES_PFIP6RXFRAGSLO(_i) (0x00544C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6661 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S 0
6662 #define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6663 #define GLPES_PFIP6RXMCOCTSHI(_i) (0x00545404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6665 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S 0
6666 #define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6667 #define GLPES_PFIP6RXMCOCTSLO(_i) (0x00545400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6669 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S 0
6670 #define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6671 #define GLPES_PFIP6RXMCPKTSHI(_i) (0x00545C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6673 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S 0
6674 #define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6675 #define GLPES_PFIP6RXMCPKTSLO(_i) (0x00545C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6677 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S 0
6678 #define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6679 #define GLPES_PFIP6RXOCTSHI(_i) (0x00543404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6681 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S 0
6682 #define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_M MAKEMASK(0xFFFF, 0)
6683 #define GLPES_PFIP6RXOCTSLO(_i) (0x00543400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6685 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S 0
6686 #define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6687 #define GLPES_PFIP6RXPKTSHI(_i) (0x00543C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6689 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S 0
6690 #define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_M MAKEMASK(0xFFFF, 0)
6691 #define GLPES_PFIP6RXPKTSLO(_i) (0x00543C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6693 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S 0
6694 #define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6695 #define GLPES_PFIP6RXTRUNC(_i) (0x00544800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6697 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_S 0
6698 #define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_M MAKEMASK(0xFFFFFFFF, 0)
6699 #define GLPES_PFIP6TXFRAGSHI(_i) (0x00549C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6701 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S 0
6702 #define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_M MAKEMASK(0xFFFF, 0)
6703 #define GLPES_PFIP6TXFRAGSLO(_i) (0x00549C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6705 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S 0
6706 #define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6707 #define GLPES_PFIP6TXMCOCTSHI(_i) (0x0054A404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6709 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S 0
6710 #define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_M MAKEMASK(0xFFFF, 0)
6711 #define GLPES_PFIP6TXMCOCTSLO(_i) (0x0054A400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6713 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S 0
6714 #define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6715 #define GLPES_PFIP6TXMCPKTSHI(_i) (0x0054AC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6717 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S 0
6718 #define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_M MAKEMASK(0xFFFF, 0)
6719 #define GLPES_PFIP6TXMCPKTSLO(_i) (0x0054AC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6721 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S 0
6722 #define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6723 #define GLPES_PFIP6TXNOROUTE(_i) (0x0054B800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6725 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_S 0
6726 #define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_M MAKEMASK(0xFFFFFF, 0)
6727 #define GLPES_PFIP6TXOCTSHI(_i) (0x00548C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6729 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S 0
6730 #define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_M MAKEMASK(0xFFFF, 0)
6731 #define GLPES_PFIP6TXOCTSLO(_i) (0x00548C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6733 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S 0
6734 #define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6735 #define GLPES_PFIP6TXPKTSHI(_i) (0x00549404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6737 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S 0
6738 #define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_M MAKEMASK(0xFFFF, 0)
6739 #define GLPES_PFIP6TXPKTSLO(_i) (0x00549400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6741 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S 0
6742 #define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6743 #define GLPES_PFRDMARXRDSHI(_i) (0x0054EC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6745 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S 0
6746 #define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0)
6747 #define GLPES_PFRDMARXRDSLO(_i) (0x0054EC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6749 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S 0
6750 #define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6751 #define GLPES_PFRDMARXSNDSHI(_i) (0x0054F404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6753 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S 0
6754 #define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0)
6755 #define GLPES_PFRDMARXSNDSLO(_i) (0x0054F400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6757 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S 0
6758 #define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6759 #define GLPES_PFRDMARXWRSHI(_i) (0x0054E404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6761 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S 0
6762 #define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0)
6763 #define GLPES_PFRDMARXWRSLO(_i) (0x0054E400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6765 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S 0
6766 #define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0)
6767 #define GLPES_PFRDMATXRDSHI(_i) (0x00550404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6769 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S 0
6770 #define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_M MAKEMASK(0xFFFF, 0)
6771 #define GLPES_PFRDMATXRDSLO(_i) (0x00550400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6773 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S 0
6774 #define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6775 #define GLPES_PFRDMATXSNDSHI(_i) (0x00550C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6777 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S 0
6778 #define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_M MAKEMASK(0xFFFF, 0)
6779 #define GLPES_PFRDMATXSNDSLO(_i) (0x00550C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6781 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S 0
6782 #define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_M MAKEMASK(0xFFFFFFFF, 0)
6783 #define GLPES_PFRDMATXWRSHI(_i) (0x0054FC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6785 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S 0
6786 #define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_M MAKEMASK(0xFFFF, 0)
6787 #define GLPES_PFRDMATXWRSLO(_i) (0x0054FC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6789 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S 0
6790 #define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_M MAKEMASK(0xFFFFFFFF, 0)
6791 #define GLPES_PFRDMAVBNDHI(_i) (0x00551404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6793 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S 0
6794 #define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_M MAKEMASK(0xFFFF, 0)
6795 #define GLPES_PFRDMAVBNDLO(_i) (0x00551400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6797 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S 0
6798 #define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_M MAKEMASK(0xFFFFFFFF, 0)
6799 #define GLPES_PFRDMAVINVHI(_i) (0x00551C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6801 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_S 0
6802 #define GLPES_PFRDMAVINVHI_RDMAVINVHI_M MAKEMASK(0xFFFF, 0)
6803 #define GLPES_PFRDMAVINVLO(_i) (0x00551C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6805 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_S 0
6806 #define GLPES_PFRDMAVINVLO_RDMAVINVLO_M MAKEMASK(0xFFFFFFFF, 0)
6807 #define GLPES_PFRXVLANERR(_i) (0x00540000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6809 #define GLPES_PFRXVLANERR_RXVLANERR_S 0
6810 #define GLPES_PFRXVLANERR_RXVLANERR_M MAKEMASK(0xFFFFFF, 0)
6811 #define GLPES_PFTCPRTXSEG(_i) (0x00552400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6813 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_S 0
6814 #define GLPES_PFTCPRTXSEG_TCPRTXSEG_M MAKEMASK(0xFFFFFFFF, 0)
6815 #define GLPES_PFTCPRXOPTERR(_i) (0x0054C400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6817 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_S 0
6818 #define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_M MAKEMASK(0xFFFFFF, 0)
6819 #define GLPES_PFTCPRXPROTOERR(_i) (0x0054C800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
6821 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_S 0
6822 #define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_M MAKEMASK(0xFFFFFF, 0)
6823 #define GLPES_PFTCPRXSEGSHI(_i) (0x0054BC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6825 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S 0
6826 #define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_M MAKEMASK(0xFFFF, 0)
6827 #define GLPES_PFTCPRXSEGSLO(_i) (0x0054BC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6829 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S 0
6830 #define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_M MAKEMASK(0xFFFFFFFF, 0)
6831 #define GLPES_PFTCPTXSEGHI(_i) (0x0054CC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6833 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_S 0
6834 #define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_M MAKEMASK(0xFFFF, 0)
6835 #define GLPES_PFTCPTXSEGLO(_i) (0x0054CC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6837 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_S 0
6838 #define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_M MAKEMASK(0xFFFFFFFF, 0)
6839 #define GLPES_PFUDPRXPKTSHI(_i) (0x0054D404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6841 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S 0
6842 #define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_M MAKEMASK(0xFFFF, 0)
6843 #define GLPES_PFUDPRXPKTSLO(_i) (0x0054D400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6845 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S 0
6846 #define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6847 #define GLPES_PFUDPTXPKTSHI(_i) (0x0054DC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6849 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S 0
6850 #define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_M MAKEMASK(0xFFFF, 0)
6851 #define GLPES_PFUDPTXPKTSLO(_i) (0x0054DC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
6853 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S 0
6854 #define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6855 #define GLPES_RDMARXMULTFPDUSHI 0x0055E00C /* Reset Source: CORER */
6856 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S 0
6857 #define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_M MAKEMASK(0xFFFFFF, 0)
6858 #define GLPES_RDMARXMULTFPDUSLO 0x0055E008 /* Reset Source: CORER */
6859 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S 0
6860 #define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_M MAKEMASK(0xFFFFFFFF, 0)
6861 #define GLPES_RDMARXOOODDPHI 0x0055E014 /* Reset Source: CORER */
6862 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S 0
6863 #define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_M MAKEMASK(0xFFFFFF, 0)
6864 #define GLPES_RDMARXOOODDPLO 0x0055E010 /* Reset Source: CORER */
6865 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S 0
6866 #define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M MAKEMASK(0xFFFFFFFF, 0)
6867 #define GLPES_RDMARXOOONOMARK 0x0055E004 /* Reset Source: CORER */
6868 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S 0
6869 #define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M MAKEMASK(0xFFFFFFFF, 0)
6870 #define GLPES_RDMARXUNALIGN 0x0055E000 /* Reset Source: CORER */
6871 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0
6872 #define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0)
6873 #define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */
6874 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
6875 #define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6876 #define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */
6877 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
6878 #define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6879 #define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */
6880 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0
6881 #define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6882 #define GLPES_TCPRXONEHOLELO 0x0055E020 /* Reset Source: CORER */
6883 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0
6884 #define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6885 #define GLPES_TCPRXPUREACKHI 0x0055E01C /* Reset Source: CORER */
6886 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S 0
6887 #define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_M MAKEMASK(0xFFFFFF, 0)
6888 #define GLPES_TCPRXPUREACKSLO 0x0055E018 /* Reset Source: CORER */
6889 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S 0
6890 #define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_M MAKEMASK(0xFFFFFFFF, 0)
6891 #define GLPES_TCPRXTHREEHOLEHI 0x0055E034 /* Reset Source: CORER */
6892 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S 0
6893 #define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6894 #define GLPES_TCPRXTHREEHOLELO 0x0055E030 /* Reset Source: CORER */
6895 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S 0
6896 #define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6897 #define GLPES_TCPRXTWOHOLEHI 0x0055E02C /* Reset Source: CORER */
6898 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S 0
6899 #define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_M MAKEMASK(0xFFFFFF, 0)
6900 #define GLPES_TCPRXTWOHOLELO 0x0055E028 /* Reset Source: CORER */
6901 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S 0
6902 #define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
6903 #define GLPES_TCPTXRETRANSFASTHI 0x0055E044 /* Reset Source: CORER */
6904 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S 0
6905 #define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_M MAKEMASK(0xFFFFFF, 0)
6906 #define GLPES_TCPTXRETRANSFASTLO 0x0055E040 /* Reset Source: CORER */
6907 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S 0
6908 #define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)
6909 #define GLPES_TCPTXTOUTSFASTHI 0x0055E04C /* Reset Source: CORER */
6910 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S 0
6911 #define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_M MAKEMASK(0xFFFFFF, 0)
6912 #define GLPES_TCPTXTOUTSFASTLO 0x0055E048 /* Reset Source: CORER */
6913 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S 0
6914 #define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)
6915 #define GLPES_TCPTXTOUTSHI 0x0055E054 /* Reset Source: CORER */
6916 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S 0
6917 #define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_M MAKEMASK(0xFFFFFF, 0)
6918 #define GLPES_TCPTXTOUTSLO 0x0055E050 /* Reset Source: CORER */
6919 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S 0
6920 #define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_M MAKEMASK(0xFFFFFFFF, 0)
6921 #define GL_PWR_MODE_CTL 0x000B820C /* Reset Source: POR */
6922 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_S 0
6923 #define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_M BIT(0)
6929 #define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_M MAKEMASK(0x3, 3)
6931 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M MAKEMASK(0x3, 30)
6932 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT 0x000B825C /* Reset Source: POR */
6933 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6934 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6936 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6938 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6940 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6942 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6944 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6946 #define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6947 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT 0x000B8218 /* Reset Source: POR */
6948 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6949 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6951 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6953 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6955 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6957 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6959 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6961 #define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6962 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT 0x000B8260 /* Reset Source: POR */
6963 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0
6964 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)
6966 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)
6968 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)
6970 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)
6972 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)
6974 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)
6976 #define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)
6977 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK 0x000B8200 /* Reset Source: POR */
6978 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_S 0
6979 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6981 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6983 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6985 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6987 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6988 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK 0x000B81F0 /* Reset Source: POR */
6989 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_S 0
6990 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
6992 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
6994 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
6996 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
6998 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
6999 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM 0x000B81FC /* Reset Source: POR */
7000 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_S 0
7001 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7003 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7005 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7007 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7009 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7010 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL 0x000B81F8 /* Reset Source: POR */
7011 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_S 0
7012 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7014 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7016 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7018 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7020 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7021 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA 0x000B8208 /* Reset Source: POR */
7022 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_S 0
7023 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7025 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7027 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7029 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7031 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7032 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK 0x000B81F4 /* Reset Source: POR */
7033 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_S 0
7034 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7036 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7038 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7040 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7042 #define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7043 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK 0x000B8244 /* Reset Source: POR */
7044 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_S 0
7045 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7047 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7049 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7051 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7053 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7054 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK 0x000B8220 /* Reset Source: POR */
7055 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_S 0
7056 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7058 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7060 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7062 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7064 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7065 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM 0x000B8240 /* Reset Source: POR */
7066 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_S 0
7067 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7069 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7071 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7073 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7075 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7076 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL 0x000B823C /* Reset Source: POR */
7077 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_S 0
7078 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7080 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7082 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7084 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7086 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7087 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA 0x000B8248 /* Reset Source: POR */
7088 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_S 0
7089 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7091 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7093 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7095 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7097 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7098 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK 0x000B8238 /* Reset Source: POR */
7099 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_S 0
7100 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7102 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7104 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7106 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7108 #define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7109 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK 0x000B8230 /* Reset Source: POR */
7110 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_S 0
7111 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7113 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7115 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7117 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7119 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7120 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK 0x000B821C /* Reset Source: POR */
7121 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_S 0
7122 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7124 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7126 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7128 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7130 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7131 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM 0x000B822C /* Reset Source: POR */
7132 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_S 0
7133 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7135 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7137 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7139 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7141 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7142 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL 0x000B8228 /* Reset Source: POR */
7143 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_S 0
7144 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7146 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7148 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7150 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7152 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7153 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA 0x000B8234 /* Reset Source: POR */
7154 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_S 0
7155 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7157 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7159 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7161 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7163 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7164 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK 0x000B8224 /* Reset Source: POR */
7165 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_S 0
7166 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7168 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7170 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7172 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7174 #define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7175 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL 0x000B81EC /* Reset Source: POR */
7176 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_S 0
7177 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)
7179 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)
7181 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)
7183 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)
7185 #define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)
7186 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL 0x000B824C /* Reset Source: POR */
7187 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_S 0
7188 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)
7190 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)
7192 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)
7194 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)
7196 #define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)
7197 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL 0x000B8250 /* Reset Source: POR */
7198 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_S 0
7199 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)
7201 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)
7203 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)
7205 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)
7207 #define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)
7208 #define GL_S5_PWR_MODE_EXIT_CTL 0x000B8270 /* Reset Source: POR */
7209 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_S 0
7210 #define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_M BIT(0)
7215 #define GLGEN_PME_TO 0x000B81BC /* Reset Source: POR */
7216 #define GLGEN_PME_TO_PME_TO_FOR_PE_S 0
7217 #define GLGEN_PME_TO_PME_TO_FOR_PE_M BIT(0)
7218 #define PRTPM_EEE_STAT 0x001E4320 /* Reset Source: GLOBR */
7225 #define PRTPM_EEEC 0x001E4380 /* Reset Source: GLOBR */
7227 #define PRTPM_EEEC_TW_WAKE_MIN_M MAKEMASK(0x3F, 16)
7229 #define PRTPM_EEEC_TX_LU_LPI_DLY_M MAKEMASK(0x3, 24)
7231 #define PRTPM_EEEC_TEEE_DLY_M MAKEMASK(0x3F, 26)
7232 #define PRTPM_EEEFWD 0x001E4400 /* Reset Source: GLOBR */
7235 #define PRTPM_EEER 0x001E4360 /* Reset Source: GLOBR */
7236 #define PRTPM_EEER_TW_SYSTEM_S 0
7237 #define PRTPM_EEER_TW_SYSTEM_M MAKEMASK(0xFFFF, 0)
7240 #define PRTPM_EEETXC 0x001E43E0 /* Reset Source: GLOBR */
7241 #define PRTPM_EEETXC_TW_PHY_S 0
7242 #define PRTPM_EEETXC_TW_PHY_M MAKEMASK(0xFFFF, 0)
7243 #define PRTPM_RLPIC 0x001E43A0 /* Reset Source: GLOBR */
7244 #define PRTPM_RLPIC_ERLPIC_S 0
7245 #define PRTPM_RLPIC_ERLPIC_M MAKEMASK(0xFFFFFFFF, 0)
7246 #define PRTPM_TLPIC 0x001E43C0 /* Reset Source: GLOBR */
7247 #define PRTPM_TLPIC_ETLPIC_S 0
7248 #define PRTPM_TLPIC_ETLPIC_M MAKEMASK(0xFFFFFFFF, 0)
7249 #define GLRPB_DHW(_i) (0x000AC000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7251 #define GLRPB_DHW_DHW_TCN_S 0
7253 #define E800_GLRPB_DHW_DHW_TCN_M MAKEMASK(0xFFFFF, 0)
7254 #define E830_GLRPB_DHW_DHW_TCN_M MAKEMASK(0x3FFFFF, 0)
7255 #define GLRPB_DLW(_i) (0x000AC044 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7257 #define GLRPB_DLW_DLW_TCN_S 0
7259 #define E800_GLRPB_DLW_DLW_TCN_M MAKEMASK(0xFFFFF, 0)
7260 #define E830_GLRPB_DLW_DLW_TCN_M MAKEMASK(0x3FFFFF, 0)
7261 #define GLRPB_DPS(_i) (0x000AC084 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7263 #define GLRPB_DPS_DPS_TCN_S 0
7265 #define E800_GLRPB_DPS_DPS_TCN_M MAKEMASK(0xFFFFF, 0)
7266 #define E830_GLRPB_DPS_DPS_TCN_M MAKEMASK(0x3FFFFF, 0)
7267 #define GLRPB_DSI_EN 0x000AC324 /* Reset Source: CORER */
7268 #define GLRPB_DSI_EN_DSI_EN_S 0
7269 #define GLRPB_DSI_EN_DSI_EN_M BIT(0)
7272 #define GLRPB_SHW(_i) (0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7274 #define GLRPB_SHW_SHW_S 0
7276 #define E800_GLRPB_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
7277 #define E830_GLRPB_SHW_SHW_M MAKEMASK(0x3FFFFF, 0)
7278 #define GLRPB_SLW(_i) (0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7280 #define GLRPB_SLW_SLW_S 0
7282 #define E800_GLRPB_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
7283 #define E830_GLRPB_SLW_SLW_M MAKEMASK(0x3FFFFF, 0)
7284 #define GLRPB_SPS(_i) (0x000AC0C4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7286 #define GLRPB_SPS_SPS_TCN_S 0
7288 #define E800_GLRPB_SPS_SPS_TCN_M MAKEMASK(0xFFFFF, 0)
7289 #define E830_GLRPB_SPS_SPS_TCN_M MAKEMASK(0x3FFFFF, 0)
7290 #define GLRPB_TC_CFG(_i) (0x000AC2A4 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7292 #define GLRPB_TC_CFG_D_POOL_S 0
7293 #define GLRPB_TC_CFG_D_POOL_M MAKEMASK(0xFFFF, 0)
7295 #define GLRPB_TC_CFG_S_POOL_M MAKEMASK(0xFFFF, 16)
7296 #define GLRPB_TCHW(_i) (0x000AC330 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7298 #define GLRPB_TCHW_TCHW_S 0
7300 #define E800_GLRPB_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
7301 #define E830_GLRPB_TCHW_TCHW_M MAKEMASK(0x3FFFFF, 0)
7302 #define GLRPB_TCLW(_i) (0x000AC3B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7304 #define GLRPB_TCLW_TCLW_S 0
7306 #define E800_GLRPB_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
7307 #define E830_GLRPB_TCLW_TCLW_M MAKEMASK(0x3FFFFF, 0)
7308 #define GLQF_APBVT(_i) (0x00450000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
7310 #define GLQF_APBVT_APBVT_S 0
7311 #define GLQF_APBVT_APBVT_M MAKEMASK(0xFFFFFFFF, 0)
7312 #define GLQF_FD_CLSN_0 0x00460028 /* Reset Source: CORER */
7313 #define GLQF_FD_CLSN_0_HITSBCNT_S 0
7314 #define GLQF_FD_CLSN_0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7315 #define GLQF_FD_CLSN1 0x00460030 /* Reset Source: CORER */
7316 #define GLQF_FD_CLSN1_HITLBCNT_S 0
7317 #define GLQF_FD_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7318 #define GLQF_FD_CNT 0x00460018 /* Reset Source: CORER */
7319 #define GLQF_FD_CNT_FD_GCNT_S 0
7321 #define E800_GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7322 #define E830_GLQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
7325 #define E800_GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7326 #define E830_GLQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
7327 #define GLQF_FD_CTL 0x00460000 /* Reset Source: CORER */
7328 #define GLQF_FD_CTL_FDLONG_S 0
7329 #define GLQF_FD_CTL_FDLONG_M MAKEMASK(0xF, 0)
7334 #define GLQF_FD_SIZE 0x00460010 /* Reset Source: CORER */
7335 #define GLQF_FD_SIZE_FD_GSIZE_S 0
7337 #define E800_GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
7338 #define E830_GLQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0)
7341 #define E800_GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
7342 #define E830_GLQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16)
7343 #define GLQF_FDCNT_0 0x00460020 /* Reset Source: CORER */
7344 #define GLQF_FDCNT_0_BUCKETCNT_S 0
7346 #define E800_GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0x7FFF, 0)
7347 #define E830_GLQF_FDCNT_0_BUCKETCNT_M MAKEMASK(0xFFFF, 0)
7350 #define GLQF_FDEVICTENA(_i) (0x00452000 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
7352 #define GLQF_FDEVICTENA_FDEVICTENA_S 0
7353 #define GLQF_FDEVICTENA_FDEVICTENA_M MAKEMASK(0xFFFFFFFF, 0)
7354 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7356 #define GLQF_FDINSET_FV_WORD_INDX0_S 0
7357 #define GLQF_FDINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7361 #define GLQF_FDINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7365 #define GLQF_FDINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7369 #define GLQF_FDINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7372 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7374 #define GLQF_FDMASK_MSK_INDEX_S 0
7375 #define GLQF_FDMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7377 #define GLQF_FDMASK_MASK_M MAKEMASK(0xFFFF, 16)
7378 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
7380 #define GLQF_FDMASK_SEL_MASK_SEL_S 0
7381 #define GLQF_FDMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0)
7382 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7384 #define GLQF_FDSWAP_FV_WORD_INDX0_S 0
7385 #define GLQF_FDSWAP_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7389 #define GLQF_FDSWAP_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7393 #define GLQF_FDSWAP_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7397 #define GLQF_FDSWAP_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7400 #define GLQF_HINSET(_i, _j) (0x0040E000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7402 #define GLQF_HINSET_FV_WORD_INDX0_S 0
7403 #define GLQF_HINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7407 #define GLQF_HINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7411 #define GLQF_HINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7415 #define GLQF_HINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7418 #define GLQF_HKEY(_i) (0x00456000 + ((_i) * 4)) /* _i=0...12 */ /* Reset Source: CORER */
7420 #define GLQF_HKEY_KEY_0_S 0
7421 #define GLQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0)
7423 #define GLQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8)
7425 #define GLQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16)
7427 #define GLQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24)
7428 #define GLQF_HLUT(_i, _j) (0x00438000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...15 */ /* Reset Source: CORER */
7430 #define GLQF_HLUT_LUT0_S 0
7431 #define GLQF_HLUT_LUT0_M MAKEMASK(0x3F, 0)
7433 #define GLQF_HLUT_LUT1_M MAKEMASK(0x3F, 8)
7435 #define GLQF_HLUT_LUT2_M MAKEMASK(0x3F, 16)
7437 #define GLQF_HLUT_LUT3_M MAKEMASK(0x3F, 24)
7438 #define GLQF_HLUT_SIZE(_i) (0x00455400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7440 #define GLQF_HLUT_SIZE_HSIZE_S 0
7441 #define GLQF_HLUT_SIZE_HSIZE_M BIT(0)
7442 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7444 #define GLQF_HMASK_MSK_INDEX_S 0
7445 #define GLQF_HMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7447 #define GLQF_HMASK_MASK_M MAKEMASK(0xFFFF, 16)
7448 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
7450 #define GLQF_HMASK_SEL_MASK_SEL_S 0
7451 #define GLQF_HMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFFFFFF, 0)
7452 #define GLQF_HSYMM(_i, _j) (0x0040F000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */
7454 #define GLQF_HSYMM_FV_SYMM_INDX0_S 0
7455 #define GLQF_HSYMM_FV_SYMM_INDX0_M MAKEMASK(0x1F, 0)
7459 #define GLQF_HSYMM_FV_SYMM_INDX1_M MAKEMASK(0x1F, 8)
7463 #define GLQF_HSYMM_FV_SYMM_INDX2_M MAKEMASK(0x1F, 16)
7467 #define GLQF_HSYMM_FV_SYMM_INDX3_M MAKEMASK(0x1F, 24)
7470 #define GLQF_PE_APBVT_CNT 0x00455500 /* Reset Source: CORER */
7471 #define GLQF_PE_APBVT_CNT_APBVT_LAN_S 0
7472 #define GLQF_PE_APBVT_CNT_APBVT_LAN_M MAKEMASK(0xFFFFFFFF, 0)
7473 #define GLQF_PE_CMD 0x00471080 /* Reset Source: CORER */
7474 #define GLQF_PE_CMD_ADDREM_STS_S 0
7475 #define GLQF_PE_CMD_ADDREM_STS_M MAKEMASK(0xFFFFFF, 0)
7477 #define GLQF_PE_CMD_ADDREM_ID_M MAKEMASK(0xF, 28)
7478 #define GLQF_PE_CTL 0x004710C0 /* Reset Source: CORER */
7479 #define GLQF_PE_CTL_PELONG_S 0
7480 #define GLQF_PE_CTL_PELONG_M MAKEMASK(0xF, 0)
7481 #define GLQF_PE_CTL2(_i) (0x00455200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7483 #define GLQF_PE_CTL2_TO_QH_S 0
7484 #define GLQF_PE_CTL2_TO_QH_M MAKEMASK(0x3, 0)
7487 #define GLQF_PE_FVE 0x0020E514 /* Reset Source: CORER */
7488 #define GLQF_PE_FVE_W_ENA_S 0
7489 #define GLQF_PE_FVE_W_ENA_M MAKEMASK(0xFFFFFF, 0)
7490 #define GLQF_PE_OSR_STS 0x00471040 /* Reset Source: CORER */
7491 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_S 0
7492 #define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_M MAKEMASK(0x3FF, 0)
7494 #define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_M MAKEMASK(0x3FF, 16)
7495 #define GLQF_PEINSET(_i, _j) (0x00415000 + ((_i) * 4 + (_j) * 128)) /* _i=0...31, _j=0...5 */ /* Reset Source: CORER */
7497 #define GLQF_PEINSET_FV_WORD_INDX0_S 0
7498 #define GLQF_PEINSET_FV_WORD_INDX0_M MAKEMASK(0x1F, 0)
7502 #define GLQF_PEINSET_FV_WORD_INDX1_M MAKEMASK(0x1F, 8)
7506 #define GLQF_PEINSET_FV_WORD_INDX2_M MAKEMASK(0x1F, 16)
7510 #define GLQF_PEINSET_FV_WORD_INDX3_M MAKEMASK(0x1F, 24)
7513 #define GLQF_PEMASK(_i) (0x00415400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7515 #define GLQF_PEMASK_MSK_INDEX_S 0
7516 #define GLQF_PEMASK_MSK_INDEX_M MAKEMASK(0x1F, 0)
7518 #define GLQF_PEMASK_MASK_M MAKEMASK(0xFFFF, 16)
7519 #define GLQF_PEMASK_SEL(_i) (0x00415500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7521 #define GLQF_PEMASK_SEL_MASK_SEL_S 0
7522 #define GLQF_PEMASK_SEL_MASK_SEL_M MAKEMASK(0xFFFF, 0)
7523 #define GLQF_PETABLE_CLR(_i) (0x000AA078 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
7525 #define GLQF_PETABLE_CLR_VM_VF_NUM_S 0
7526 #define GLQF_PETABLE_CLR_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
7528 #define GLQF_PETABLE_CLR_VM_VF_TYPE_M MAKEMASK(0x3, 10)
7530 #define GLQF_PETABLE_CLR_PF_NUM_M MAKEMASK(0x7, 12)
7535 #define GLQF_PROF2TC(_i, _j) (0x0044D000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...3 */ /* Reset Source: CORER */
7537 #define GLQF_PROF2TC_OVERRIDE_ENA_0_S 0
7538 #define GLQF_PROF2TC_OVERRIDE_ENA_0_M BIT(0)
7540 #define GLQF_PROF2TC_REGION_0_M MAKEMASK(0x7, 1)
7544 #define GLQF_PROF2TC_REGION_1_M MAKEMASK(0x7, 5)
7548 #define GLQF_PROF2TC_REGION_2_M MAKEMASK(0x7, 9)
7552 #define GLQF_PROF2TC_REGION_3_M MAKEMASK(0x7, 13)
7556 #define GLQF_PROF2TC_REGION_4_M MAKEMASK(0x7, 17)
7560 #define GLQF_PROF2TC_REGION_5_M MAKEMASK(0x7, 21)
7564 #define GLQF_PROF2TC_REGION_6_M MAKEMASK(0x7, 25)
7568 #define GLQF_PROF2TC_REGION_7_M MAKEMASK(0x7, 29)
7569 #define PFQF_FD_CNT 0x00460180 /* Reset Source: CORER */
7570 #define PFQF_FD_CNT_FD_GCNT_S 0
7572 #define E800_PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7573 #define E830_PFQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
7576 #define E800_PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7577 #define E830_PFQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
7578 #define PFQF_FD_ENA 0x0043A000 /* Reset Source: CORER */
7579 #define PFQF_FD_ENA_FD_ENA_S 0
7580 #define PFQF_FD_ENA_FD_ENA_M BIT(0)
7581 #define PFQF_FD_SIZE 0x00460100 /* Reset Source: CORER */
7582 #define PFQF_FD_SIZE_FD_GSIZE_S 0
7584 #define E800_PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x7FFF, 0)
7585 #define E830_PFQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0)
7588 #define E800_PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x7FFF, 16)
7589 #define E830_PFQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16)
7590 #define PFQF_FD_SUBTRACT 0x00460200 /* Reset Source: CORER */
7591 #define PFQF_FD_SUBTRACT_FD_GCNT_S 0
7593 #define E800_PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0x7FFF, 0)
7594 #define E830_PFQF_FD_SUBTRACT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
7597 #define E800_PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0x7FFF, 16)
7598 #define E830_PFQF_FD_SUBTRACT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
7599 #define PFQF_HLUT(_i) (0x00430000 + ((_i) * 64)) /* _i=0...511 */ /* Reset Source: CORER */
7601 #define PFQF_HLUT_LUT0_S 0
7602 #define PFQF_HLUT_LUT0_M MAKEMASK(0xFF, 0)
7604 #define PFQF_HLUT_LUT1_M MAKEMASK(0xFF, 8)
7606 #define PFQF_HLUT_LUT2_M MAKEMASK(0xFF, 16)
7608 #define PFQF_HLUT_LUT3_M MAKEMASK(0xFF, 24)
7609 #define PFQF_HLUT_SIZE 0x00455480 /* Reset Source: CORER */
7610 #define PFQF_HLUT_SIZE_HSIZE_S 0
7611 #define PFQF_HLUT_SIZE_HSIZE_M MAKEMASK(0x3, 0)
7612 #define PFQF_PE_CLSN0 0x00470480 /* Reset Source: CORER */
7613 #define PFQF_PE_CLSN0_HITSBCNT_S 0
7614 #define PFQF_PE_CLSN0_HITSBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7615 #define PFQF_PE_CLSN1 0x00470500 /* Reset Source: CORER */
7616 #define PFQF_PE_CLSN1_HITLBCNT_S 0
7617 #define PFQF_PE_CLSN1_HITLBCNT_M MAKEMASK(0xFFFFFFFF, 0)
7618 #define PFQF_PE_CTL1 0x00470000 /* Reset Source: CORER */
7619 #define PFQF_PE_CTL1_PEHSIZE_S 0
7620 #define PFQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0)
7621 #define PFQF_PE_CTL2 0x00470040 /* Reset Source: CORER */
7622 #define PFQF_PE_CTL2_PEDSIZE_S 0
7623 #define PFQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0)
7624 #define PFQF_PE_FILTERING_ENA 0x0043A080 /* Reset Source: CORER */
7625 #define PFQF_PE_FILTERING_ENA_PE_ENA_S 0
7626 #define PFQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
7627 #define PFQF_PE_FLHD 0x00470100 /* Reset Source: CORER */
7628 #define PFQF_PE_FLHD_FLHD_S 0
7629 #define PFQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0)
7630 #define PFQF_PE_ST_CTL 0x00470400 /* Reset Source: CORER */
7631 #define PFQF_PE_ST_CTL_PF_CNT_EN_S 0
7632 #define PFQF_PE_ST_CTL_PF_CNT_EN_M BIT(0)
7638 #define PFQF_PE_ST_CTL_VF_NUM_M MAKEMASK(0xFF, 16)
7639 #define PFQF_PE_TC_CTL 0x00452080 /* Reset Source: CORER */
7640 #define PFQF_PE_TC_CTL_TC_EN_PF_S 0
7641 #define PFQF_PE_TC_CTL_TC_EN_PF_M MAKEMASK(0xFF, 0)
7643 #define PFQF_PE_TC_CTL_TC_EN_VF_M MAKEMASK(0xFF, 16)
7644 #define PFQF_PECNT_0 0x00470200 /* Reset Source: CORER */
7645 #define PFQF_PECNT_0_BUCKETCNT_S 0
7646 #define PFQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0)
7647 #define PFQF_PECNT_1 0x00470300 /* Reset Source: CORER */
7648 #define PFQF_PECNT_1_FLTCNT_S 0
7649 #define PFQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0)
7650 #define VPQF_PE_CTL1(_VF) (0x00474000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7652 #define VPQF_PE_CTL1_PEHSIZE_S 0
7653 #define VPQF_PE_CTL1_PEHSIZE_M MAKEMASK(0xF, 0)
7654 #define VPQF_PE_CTL2(_VF) (0x00474800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7656 #define VPQF_PE_CTL2_PEDSIZE_S 0
7657 #define VPQF_PE_CTL2_PEDSIZE_M MAKEMASK(0xF, 0)
7658 #define VPQF_PE_FILTERING_ENA(_VF) (0x00455800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7660 #define VPQF_PE_FILTERING_ENA_PE_ENA_S 0
7661 #define VPQF_PE_FILTERING_ENA_PE_ENA_M BIT(0)
7662 #define VPQF_PE_FLHD(_VF) (0x00472000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7664 #define VPQF_PE_FLHD_FLHD_S 0
7665 #define VPQF_PE_FLHD_FLHD_M MAKEMASK(0xFFFFFF, 0)
7666 #define VPQF_PECNT_0(_VF) (0x00472800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7668 #define VPQF_PECNT_0_BUCKETCNT_S 0
7669 #define VPQF_PECNT_0_BUCKETCNT_M MAKEMASK(0x3FFFF, 0)
7670 #define VPQF_PECNT_1(_VF) (0x00473000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
7672 #define VPQF_PECNT_1_FLTCNT_S 0
7673 #define VPQF_PECNT_1_FLTCNT_M MAKEMASK(0x3FFFF, 0)
7674 #define GLDCB_RMPMC 0x001223C8 /* Reset Source: CORER */
7675 #define GLDCB_RMPMC_RSPM_S 0
7676 #define GLDCB_RMPMC_RSPM_M MAKEMASK(0x3F, 0)
7678 #define GLDCB_RMPMC_MIQ_NODROP_MODE_M MAKEMASK(0x1F, 6)
7681 #define GLDCB_RMPMS 0x001223CC /* Reset Source: CORER */
7682 #define GLDCB_RMPMS_RMPM_S 0
7683 #define GLDCB_RMPMS_RMPM_M MAKEMASK(0xFFFF, 0)
7684 #define GLDCB_RPCC 0x00122260 /* Reset Source: CORER */
7685 #define GLDCB_RPCC_EN_S 0
7686 #define GLDCB_RPCC_EN_M BIT(0)
7688 #define GLDCB_RPCC_SCL_FACT_M MAKEMASK(0x1F, 4)
7690 #define GLDCB_RPCC_THRSH_M MAKEMASK(0xFFF, 16)
7691 #define GLDCB_RSPMC 0x001223C4 /* Reset Source: CORER */
7692 #define GLDCB_RSPMC_RSPM_S 0
7693 #define GLDCB_RSPMC_RSPM_M MAKEMASK(0xFF, 0)
7695 #define GLDCB_RSPMC_RPM_MODE_M MAKEMASK(0x3, 8)
7697 #define GLDCB_RSPMC_PRR_MAX_EXP_M MAKEMASK(0xF, 10)
7699 #define GLDCB_RSPMC_PFCTIMER_M MAKEMASK(0x3FFF, 14)
7702 #define GLDCB_RSPMS 0x001223C0 /* Reset Source: CORER */
7703 #define GLDCB_RSPMS_RSPM_S 0
7704 #define GLDCB_RSPMS_RSPM_M MAKEMASK(0x3FFFF, 0)
7705 #define GLDCB_RTCTI 0x001223D0 /* Reset Source: CORER */
7706 #define GLDCB_RTCTI_PFCTIMEOUT_TC_S 0
7707 #define GLDCB_RTCTI_PFCTIMEOUT_TC_M MAKEMASK(0xFFFFFFFF, 0)
7708 #define GLDCB_RTCTQ(_i) (0x001222C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7710 #define GLDCB_RTCTQ_RXQNUM_S 0
7711 #define GLDCB_RTCTQ_RXQNUM_M MAKEMASK(0x7FF, 0)
7714 #define GLDCB_RTCTS(_i) (0x00122340 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7716 #define GLDCB_RTCTS_PFCTIMER_S 0
7717 #define GLDCB_RTCTS_PFCTIMER_M MAKEMASK(0x3FFF, 0)
7718 #define GLRCB_CFG_COTF_CNT(_i) (0x001223D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7720 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_S 0
7721 #define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_M MAKEMASK(0x3F, 0)
7722 #define GLRCB_CFG_COTF_ST 0x001223F4 /* Reset Source: CORER */
7723 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_S 0
7724 #define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_M MAKEMASK(0xFF, 0)
7725 #define GLRPRS_PMCFG_DHW(_i) (0x00200388 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7727 #define GLRPRS_PMCFG_DHW_DHW_S 0
7728 #define GLRPRS_PMCFG_DHW_DHW_M MAKEMASK(0xFFFFF, 0)
7729 #define GLRPRS_PMCFG_DLW(_i) (0x002003C8 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7731 #define GLRPRS_PMCFG_DLW_DLW_S 0
7732 #define GLRPRS_PMCFG_DLW_DLW_M MAKEMASK(0xFFFFF, 0)
7733 #define GLRPRS_PMCFG_DPS(_i) (0x00200308 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */
7735 #define GLRPRS_PMCFG_DPS_DPS_S 0
7736 #define GLRPRS_PMCFG_DPS_DPS_M MAKEMASK(0xFFFFF, 0)
7737 #define GLRPRS_PMCFG_SHW(_i) (0x00200448 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7739 #define GLRPRS_PMCFG_SHW_SHW_S 0
7740 #define GLRPRS_PMCFG_SHW_SHW_M MAKEMASK(0xFFFFF, 0)
7741 #define GLRPRS_PMCFG_SLW(_i) (0x00200468 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7743 #define GLRPRS_PMCFG_SLW_SLW_S 0
7744 #define GLRPRS_PMCFG_SLW_SLW_M MAKEMASK(0xFFFFF, 0)
7745 #define GLRPRS_PMCFG_SPS(_i) (0x00200408 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
7747 #define GLRPRS_PMCFG_SPS_SPS_S 0
7748 #define GLRPRS_PMCFG_SPS_SPS_M MAKEMASK(0xFFFFF, 0)
7749 #define GLRPRS_PMCFG_TC_CFG(_i) (0x00200488 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7751 #define GLRPRS_PMCFG_TC_CFG_D_POOL_S 0
7752 #define GLRPRS_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0)
7754 #define GLRPRS_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16)
7755 #define GLRPRS_PMCFG_TCHW(_i) (0x00200588 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7757 #define GLRPRS_PMCFG_TCHW_TCHW_S 0
7758 #define GLRPRS_PMCFG_TCHW_TCHW_M MAKEMASK(0xFFFFF, 0)
7759 #define GLRPRS_PMCFG_TCLW(_i) (0x00200608 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7761 #define GLRPRS_PMCFG_TCLW_TCLW_S 0
7762 #define GLRPRS_PMCFG_TCLW_TCLW_M MAKEMASK(0xFFFFF, 0)
7763 #define GLSWT_PMCFG_TC_CFG(_i) (0x00204900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
7765 #define GLSWT_PMCFG_TC_CFG_D_POOL_S 0
7766 #define GLSWT_PMCFG_TC_CFG_D_POOL_M MAKEMASK(0xF, 0)
7768 #define GLSWT_PMCFG_TC_CFG_S_POOL_M MAKEMASK(0x7, 16)
7769 #define PRTDCB_RLANPMS 0x00122280 /* Reset Source: CORER */
7770 #define PRTDCB_RLANPMS_LANRPPM_S 0
7771 #define PRTDCB_RLANPMS_LANRPPM_M MAKEMASK(0x3FFFF, 0)
7772 #define PRTDCB_RPPMC 0x00122240 /* Reset Source: CORER */
7773 #define PRTDCB_RPPMC_LANRPPM_S 0
7774 #define PRTDCB_RPPMC_LANRPPM_M MAKEMASK(0xFF, 0)
7776 #define PRTDCB_RPPMC_RDMARPPM_M MAKEMASK(0xFF, 8)
7777 #define PRTDCB_RRDMAPMS 0x00122120 /* Reset Source: CORER */
7778 #define PRTDCB_RRDMAPMS_RDMARPPM_S 0
7779 #define PRTDCB_RRDMAPMS_RDMARPPM_M MAKEMASK(0x3FFFF, 0)
7780 #define GL_STAT_SWR_BPCH(_i) (0x00347804 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7782 #define GL_STAT_SWR_BPCH_VLBPCH_S 0
7783 #define GL_STAT_SWR_BPCH_VLBPCH_M MAKEMASK(0xFF, 0)
7784 #define GL_STAT_SWR_BPCL(_i) (0x00347800 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7786 #define GL_STAT_SWR_BPCL_VLBPCL_S 0
7787 #define GL_STAT_SWR_BPCL_VLBPCL_M MAKEMASK(0xFFFFFFFF, 0)
7788 #define GL_STAT_SWR_GORCH(_i) (0x00342004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7790 #define GL_STAT_SWR_GORCH_VLBCH_S 0
7791 #define GL_STAT_SWR_GORCH_VLBCH_M MAKEMASK(0xFF, 0)
7792 #define GL_STAT_SWR_GORCL(_i) (0x00342000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7794 #define GL_STAT_SWR_GORCL_VLBCL_S 0
7795 #define GL_STAT_SWR_GORCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0)
7796 #define GL_STAT_SWR_GOTCH(_i) (0x00304004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7798 #define GL_STAT_SWR_GOTCH_VLBCH_S 0
7799 #define GL_STAT_SWR_GOTCH_VLBCH_M MAKEMASK(0xFF, 0)
7800 #define GL_STAT_SWR_GOTCL(_i) (0x00304000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7802 #define GL_STAT_SWR_GOTCL_VLBCL_S 0
7803 #define GL_STAT_SWR_GOTCL_VLBCL_M MAKEMASK(0xFFFFFFFF, 0)
7804 #define GL_STAT_SWR_MPCH(_i) (0x00347404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7806 #define GL_STAT_SWR_MPCH_VLMPCH_S 0
7807 #define GL_STAT_SWR_MPCH_VLMPCH_M MAKEMASK(0xFF, 0)
7808 #define GL_STAT_SWR_MPCL(_i) (0x00347400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7810 #define GL_STAT_SWR_MPCL_VLMPCL_S 0
7811 #define GL_STAT_SWR_MPCL_VLMPCL_M MAKEMASK(0xFFFFFFFF, 0)
7812 #define GL_STAT_SWR_UPCH(_i) (0x00347004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7814 #define GL_STAT_SWR_UPCH_VLUPCH_S 0
7815 #define GL_STAT_SWR_UPCH_VLUPCH_M MAKEMASK(0xFF, 0)
7816 #define GL_STAT_SWR_UPCL(_i) (0x00347000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
7818 #define GL_STAT_SWR_UPCL_VLUPCL_S 0
7819 #define GL_STAT_SWR_UPCL_VLUPCL_M MAKEMASK(0xFFFFFFFF, 0)
7820 #define GLPRT_AORCL(_i) (0x003812C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7822 #define GLPRT_AORCL_AORCL_S 0
7823 #define GLPRT_AORCL_AORCL_M MAKEMASK(0xFFFFFFFF, 0)
7824 #define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7826 #define E800_GLPRT_BPRCH_UPRCH_S 0
7827 #define E800_GLPRT_BPRCH_UPRCH_M MAKEMASK(0xFF, 0)
7828 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7830 #define E800_GLPRT_BPRCL_UPRCH_S 0
7831 #define E800_GLPRT_BPRCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
7832 #define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7834 #define E800_GLPRT_BPTCH_UPRCH_S 0
7835 #define E800_GLPRT_BPTCH_UPRCH_M MAKEMASK(0xFF, 0)
7836 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7838 #define E800_GLPRT_BPTCL_UPRCH_S 0
7839 #define E800_GLPRT_BPTCL_UPRCH_M MAKEMASK(0xFFFFFFFF, 0)
7840 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7842 #define GLPRT_CRCERRS_CRCERRS_S 0
7843 #define GLPRT_CRCERRS_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
7844 #define GLPRT_CRCERRS_H(_i) (0x00380104 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7846 #define GLPRT_CRCERRS_H_CRCERRS_S 0
7847 #define GLPRT_CRCERRS_H_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
7848 #define GLPRT_GORCH(_i) (0x00380004 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7850 #define GLPRT_GORCH_GORCH_S 0
7851 #define GLPRT_GORCH_GORCH_M MAKEMASK(0xFF, 0)
7852 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7854 #define GLPRT_GORCL_GORCL_S 0
7855 #define GLPRT_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
7856 #define GLPRT_GOTCH(_i) (0x00380B44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7858 #define GLPRT_GOTCH_GOTCH_S 0
7859 #define GLPRT_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
7860 #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7862 #define GLPRT_GOTCL_GOTCL_S 0
7863 #define GLPRT_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
7864 #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7866 #define GLPRT_ILLERRC_ILLERRC_S 0
7867 #define GLPRT_ILLERRC_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0)
7868 #define GLPRT_ILLERRC_H(_i) (0x003801C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7870 #define GLPRT_ILLERRC_H_ILLERRC_S 0
7871 #define GLPRT_ILLERRC_H_ILLERRC_M MAKEMASK(0xFFFFFFFF, 0)
7872 #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7874 #define GLPRT_LXOFFRXC_LXOFFRXCNT_S 0
7875 #define GLPRT_LXOFFRXC_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7876 #define GLPRT_LXOFFRXC_H(_i) (0x003802C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7878 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_S 0
7879 #define GLPRT_LXOFFRXC_H_LXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7880 #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7882 #define GLPRT_LXOFFTXC_LXOFFTXC_S 0
7883 #define GLPRT_LXOFFTXC_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0)
7884 #define GLPRT_LXOFFTXC_H(_i) (0x00381184 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7886 #define GLPRT_LXOFFTXC_H_LXOFFTXC_S 0
7887 #define GLPRT_LXOFFTXC_H_LXOFFTXC_M MAKEMASK(0xFFFFFFFF, 0)
7888 #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7890 #define GLPRT_LXONRXC_LXONRXCNT_S 0
7891 #define GLPRT_LXONRXC_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7892 #define GLPRT_LXONRXC_H(_i) (0x00380284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7894 #define GLPRT_LXONRXC_H_LXONRXCNT_S 0
7895 #define GLPRT_LXONRXC_H_LXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
7896 #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7898 #define GLPRT_LXONTXC_LXONTXC_S 0
7899 #define GLPRT_LXONTXC_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7900 #define GLPRT_LXONTXC_H(_i) (0x00381144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7902 #define GLPRT_LXONTXC_H_LXONTXC_S 0
7903 #define GLPRT_LXONTXC_H_LXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
7904 #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7906 #define GLPRT_MLFC_MLFC_S 0
7907 #define GLPRT_MLFC_MLFC_M MAKEMASK(0xFFFFFFFF, 0)
7908 #define GLPRT_MLFC_H(_i) (0x00380044 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7910 #define GLPRT_MLFC_H_MLFC_S 0
7911 #define GLPRT_MLFC_H_MLFC_M MAKEMASK(0xFFFFFFFF, 0)
7912 #define GLPRT_MPRCH(_i) (0x00381344 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7914 #define GLPRT_MPRCH_MPRCH_S 0
7915 #define GLPRT_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
7916 #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7918 #define GLPRT_MPRCL_MPRCL_S 0
7919 #define GLPRT_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
7920 #define GLPRT_MPTCH(_i) (0x00381204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7922 #define GLPRT_MPTCH_MPTCH_S 0
7923 #define GLPRT_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
7924 #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7926 #define GLPRT_MPTCL_MPTCL_S 0
7927 #define GLPRT_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
7928 #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7930 #define GLPRT_MRFC_MRFC_S 0
7931 #define GLPRT_MRFC_MRFC_M MAKEMASK(0xFFFFFFFF, 0)
7932 #define GLPRT_MRFC_H(_i) (0x00380084 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7934 #define GLPRT_MRFC_H_MRFC_S 0
7935 #define GLPRT_MRFC_H_MRFC_M MAKEMASK(0xFFFFFFFF, 0)
7936 #define GLPRT_PRC1023H(_i) (0x00380A04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7938 #define GLPRT_PRC1023H_PRC1023H_S 0
7939 #define GLPRT_PRC1023H_PRC1023H_M MAKEMASK(0xFF, 0)
7940 #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7942 #define GLPRT_PRC1023L_PRC1023L_S 0
7943 #define GLPRT_PRC1023L_PRC1023L_M MAKEMASK(0xFFFFFFFF, 0)
7944 #define GLPRT_PRC127H(_i) (0x00380944 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7946 #define GLPRT_PRC127H_PRC127H_S 0
7947 #define GLPRT_PRC127H_PRC127H_M MAKEMASK(0xFF, 0)
7948 #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7950 #define GLPRT_PRC127L_PRC127L_S 0
7951 #define GLPRT_PRC127L_PRC127L_M MAKEMASK(0xFFFFFFFF, 0)
7952 #define GLPRT_PRC1522H(_i) (0x00380A44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7954 #define GLPRT_PRC1522H_PRC1522H_S 0
7955 #define GLPRT_PRC1522H_PRC1522H_M MAKEMASK(0xFF, 0)
7956 #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7958 #define GLPRT_PRC1522L_PRC1522L_S 0
7959 #define GLPRT_PRC1522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7960 #define GLPRT_PRC255H(_i) (0x00380984 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7962 #define GLPRT_PRC255H_PRTPRC255H_S 0
7963 #define GLPRT_PRC255H_PRTPRC255H_M MAKEMASK(0xFF, 0)
7964 #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7966 #define GLPRT_PRC255L_PRC255L_S 0
7967 #define GLPRT_PRC255L_PRC255L_M MAKEMASK(0xFFFFFFFF, 0)
7968 #define GLPRT_PRC511H(_i) (0x003809C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7970 #define GLPRT_PRC511H_PRC511H_S 0
7971 #define GLPRT_PRC511H_PRC511H_M MAKEMASK(0xFF, 0)
7972 #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7974 #define GLPRT_PRC511L_PRC511L_S 0
7975 #define GLPRT_PRC511L_PRC511L_M MAKEMASK(0xFFFFFFFF, 0)
7976 #define GLPRT_PRC64H(_i) (0x00380904 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7978 #define GLPRT_PRC64H_PRC64H_S 0
7979 #define GLPRT_PRC64H_PRC64H_M MAKEMASK(0xFF, 0)
7980 #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7982 #define GLPRT_PRC64L_PRC64L_S 0
7983 #define GLPRT_PRC64L_PRC64L_M MAKEMASK(0xFFFFFFFF, 0)
7984 #define GLPRT_PRC9522H(_i) (0x00380A84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7986 #define GLPRT_PRC9522H_PRC1522H_S 0
7987 #define GLPRT_PRC9522H_PRC1522H_M MAKEMASK(0xFF, 0)
7988 #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7990 #define GLPRT_PRC9522L_PRC1522L_S 0
7991 #define GLPRT_PRC9522L_PRC1522L_M MAKEMASK(0xFFFFFFFF, 0)
7992 #define GLPRT_PTC1023H(_i) (0x00380C84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7994 #define GLPRT_PTC1023H_PTC1023H_S 0
7995 #define GLPRT_PTC1023H_PTC1023H_M MAKEMASK(0xFF, 0)
7996 #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
7998 #define GLPRT_PTC1023L_PTC1023L_S 0
7999 #define GLPRT_PTC1023L_PTC1023L_M MAKEMASK(0xFFFFFFFF, 0)
8000 #define GLPRT_PTC127H(_i) (0x00380BC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8002 #define GLPRT_PTC127H_PTC127H_S 0
8003 #define GLPRT_PTC127H_PTC127H_M MAKEMASK(0xFF, 0)
8004 #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8006 #define GLPRT_PTC127L_PTC127L_S 0
8007 #define GLPRT_PTC127L_PTC127L_M MAKEMASK(0xFFFFFFFF, 0)
8008 #define GLPRT_PTC1522H(_i) (0x00380CC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8010 #define GLPRT_PTC1522H_PTC1522H_S 0
8011 #define GLPRT_PTC1522H_PTC1522H_M MAKEMASK(0xFF, 0)
8012 #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8014 #define GLPRT_PTC1522L_PTC1522L_S 0
8015 #define GLPRT_PTC1522L_PTC1522L_M MAKEMASK(0xFFFFFFFF, 0)
8016 #define GLPRT_PTC255H(_i) (0x00380C04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8018 #define GLPRT_PTC255H_PTC255H_S 0
8019 #define GLPRT_PTC255H_PTC255H_M MAKEMASK(0xFF, 0)
8020 #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8022 #define GLPRT_PTC255L_PTC255L_S 0
8023 #define GLPRT_PTC255L_PTC255L_M MAKEMASK(0xFFFFFFFF, 0)
8024 #define GLPRT_PTC511H(_i) (0x00380C44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8026 #define GLPRT_PTC511H_PTC511H_S 0
8027 #define GLPRT_PTC511H_PTC511H_M MAKEMASK(0xFF, 0)
8028 #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8030 #define GLPRT_PTC511L_PTC511L_S 0
8031 #define GLPRT_PTC511L_PTC511L_M MAKEMASK(0xFFFFFFFF, 0)
8032 #define GLPRT_PTC64H(_i) (0x00380B84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8034 #define GLPRT_PTC64H_PTC64H_S 0
8035 #define GLPRT_PTC64H_PTC64H_M MAKEMASK(0xFF, 0)
8036 #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8038 #define GLPRT_PTC64L_PTC64L_S 0
8039 #define GLPRT_PTC64L_PTC64L_M MAKEMASK(0xFFFFFFFF, 0)
8040 #define GLPRT_PTC9522H(_i) (0x00380D04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8042 #define GLPRT_PTC9522H_PTC9522H_S 0
8043 #define GLPRT_PTC9522H_PTC9522H_M MAKEMASK(0xFF, 0)
8044 #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8046 #define GLPRT_PTC9522L_PTC9522L_S 0
8047 #define GLPRT_PTC9522L_PTC9522L_M MAKEMASK(0xFFFFFFFF, 0)
8048 #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8050 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_S 0
8051 #define GLPRT_PXOFFRXC_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
8052 #define GLPRT_PXOFFRXC_H(_i, _j) (0x00380504 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8054 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_S 0
8055 #define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
8056 #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8058 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_S 0
8059 #define GLPRT_PXOFFTXC_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0)
8060 #define GLPRT_PXOFFTXC_H(_i, _j) (0x00380F44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8062 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_S 0
8063 #define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_M MAKEMASK(0xFFFFFFFF, 0)
8064 #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8066 #define GLPRT_PXONRXC_PRPXONRXCNT_S 0
8067 #define GLPRT_PXONRXC_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
8068 #define GLPRT_PXONRXC_H(_i, _j) (0x00380304 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8070 #define GLPRT_PXONRXC_H_PRPXONRXCNT_S 0
8071 #define GLPRT_PXONRXC_H_PRPXONRXCNT_M MAKEMASK(0xFFFFFFFF, 0)
8072 #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8074 #define GLPRT_PXONTXC_PRPXONTXC_S 0
8075 #define GLPRT_PXONTXC_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
8076 #define GLPRT_PXONTXC_H(_i, _j) (0x00380D44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8078 #define GLPRT_PXONTXC_H_PRPXONTXC_S 0
8079 #define GLPRT_PXONTXC_H_PRPXONTXC_M MAKEMASK(0xFFFFFFFF, 0)
8080 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8082 #define GLPRT_RFC_RFC_S 0
8083 #define GLPRT_RFC_RFC_M MAKEMASK(0xFFFFFFFF, 0)
8084 #define GLPRT_RFC_H(_i) (0x00380AC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8086 #define GLPRT_RFC_H_RFC_S 0
8087 #define GLPRT_RFC_H_RFC_M MAKEMASK(0xFFFFFFFF, 0)
8088 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8090 #define GLPRT_RJC_RJC_S 0
8091 #define GLPRT_RJC_RJC_M MAKEMASK(0xFFFFFFFF, 0)
8092 #define GLPRT_RJC_H(_i) (0x00380B04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8094 #define GLPRT_RJC_H_RJC_S 0
8095 #define GLPRT_RJC_H_RJC_M MAKEMASK(0xFFFFFFFF, 0)
8096 #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8098 #define GLPRT_RLEC_RLEC_S 0
8099 #define GLPRT_RLEC_RLEC_M MAKEMASK(0xFFFFFFFF, 0)
8100 #define GLPRT_RLEC_H(_i) (0x00380144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8102 #define GLPRT_RLEC_H_RLEC_S 0
8103 #define GLPRT_RLEC_H_RLEC_M MAKEMASK(0xFFFFFFFF, 0)
8104 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8106 #define GLPRT_ROC_ROC_S 0
8107 #define GLPRT_ROC_ROC_M MAKEMASK(0xFFFFFFFF, 0)
8108 #define GLPRT_ROC_H(_i) (0x00380244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8110 #define GLPRT_ROC_H_ROC_S 0
8111 #define GLPRT_ROC_H_ROC_M MAKEMASK(0xFFFFFFFF, 0)
8112 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8114 #define GLPRT_RUC_RUC_S 0
8115 #define GLPRT_RUC_RUC_M MAKEMASK(0xFFFFFFFF, 0)
8116 #define GLPRT_RUC_H(_i) (0x00380204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8118 #define GLPRT_RUC_H_RUC_S 0
8119 #define GLPRT_RUC_H_RUC_M MAKEMASK(0xFFFFFFFF, 0)
8120 #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8122 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_S 0
8123 #define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0)
8124 #define GLPRT_RXON2OFFCNT_H(_i, _j) (0x00380704 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */
8126 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_S 0
8127 #define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_M MAKEMASK(0xFFFFFFFF, 0)
8128 #define GLPRT_STDC(_i) (0x00340000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
8130 #define GLPRT_STDC_STDC_S 0
8131 #define GLPRT_STDC_STDC_M MAKEMASK(0xFFFFFFFF, 0)
8132 #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8134 #define GLPRT_TDOLD_GLPRT_TDOLD_S 0
8135 #define GLPRT_TDOLD_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0)
8136 #define GLPRT_TDOLD_H(_i) (0x00381284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8138 #define GLPRT_TDOLD_H_GLPRT_TDOLD_S 0
8139 #define GLPRT_TDOLD_H_GLPRT_TDOLD_M MAKEMASK(0xFFFFFFFF, 0)
8140 #define GLPRT_UPRCH(_i) (0x00381304 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8142 #define GLPRT_UPRCH_UPRCH_S 0
8143 #define GLPRT_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8144 #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8146 #define GLPRT_UPRCL_UPRCL_S 0
8147 #define GLPRT_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8148 #define GLPRT_UPTCH(_i) (0x003811C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8150 #define GLPRT_UPTCH_UPTCH_S 0
8151 #define GLPRT_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
8152 #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */
8154 #define E800_GLPRT_UPTCL_VUPTCH_S 0
8155 #define E800_GLPRT_UPTCL_VUPTCH_M MAKEMASK(0xFFFFFFFF, 0)
8156 #define GLSTAT_ACL_CNT_0_H(_i) (0x00388004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8158 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_S 0
8159 #define GLSTAT_ACL_CNT_0_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8160 #define GLSTAT_ACL_CNT_0_L(_i) (0x00388000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8162 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_S 0
8163 #define GLSTAT_ACL_CNT_0_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8164 #define GLSTAT_ACL_CNT_1_H(_i) (0x00389004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8166 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_S 0
8167 #define GLSTAT_ACL_CNT_1_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8168 #define GLSTAT_ACL_CNT_1_L(_i) (0x00389000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8170 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_S 0
8171 #define GLSTAT_ACL_CNT_1_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8172 #define GLSTAT_ACL_CNT_2_H(_i) (0x0038A004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8174 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_S 0
8175 #define GLSTAT_ACL_CNT_2_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8176 #define GLSTAT_ACL_CNT_2_L(_i) (0x0038A000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8178 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_S 0
8179 #define GLSTAT_ACL_CNT_2_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8180 #define GLSTAT_ACL_CNT_3_H(_i) (0x0038B004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8182 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_S 0
8183 #define GLSTAT_ACL_CNT_3_H_CNT_MSB_M MAKEMASK(0xFF, 0)
8184 #define GLSTAT_ACL_CNT_3_L(_i) (0x0038B000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */
8186 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_S 0
8187 #define GLSTAT_ACL_CNT_3_L_CNT_LSB_M MAKEMASK(0xFFFFFFFF, 0)
8188 #define GLSTAT_FD_CNT0H(_i) (0x003A0004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8190 #define GLSTAT_FD_CNT0H_FD0_CNT_H_S 0
8191 #define GLSTAT_FD_CNT0H_FD0_CNT_H_M MAKEMASK(0xFF, 0)
8192 #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8194 #define GLSTAT_FD_CNT0L_FD0_CNT_L_S 0
8195 #define GLSTAT_FD_CNT0L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8196 #define GLSTAT_FD_CNT1H(_i) (0x003A8004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8198 #define GLSTAT_FD_CNT1H_FD0_CNT_H_S 0
8199 #define GLSTAT_FD_CNT1H_FD0_CNT_H_M MAKEMASK(0xFF, 0)
8200 #define GLSTAT_FD_CNT1L(_i) (0x003A8000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */
8202 #define GLSTAT_FD_CNT1L_FD0_CNT_L_S 0
8203 #define GLSTAT_FD_CNT1L_FD0_CNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8204 #define GLSW_BPRCH(_i) (0x00346204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8206 #define GLSW_BPRCH_BPRCH_S 0
8207 #define GLSW_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
8208 #define GLSW_BPRCL(_i) (0x00346200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8210 #define GLSW_BPRCL_BPRCL_S 0
8211 #define GLSW_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8212 #define GLSW_BPTCH(_i) (0x00310204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8214 #define GLSW_BPTCH_BPTCH_S 0
8215 #define GLSW_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
8216 #define GLSW_BPTCL(_i) (0x00310200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8218 #define GLSW_BPTCL_BPTCL_S 0
8219 #define GLSW_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8220 #define GLSW_GORCH(_i) (0x00341004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8222 #define GLSW_GORCH_GORCH_S 0
8223 #define GLSW_GORCH_GORCH_M MAKEMASK(0xFF, 0)
8224 #define GLSW_GORCL(_i) (0x00341000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8226 #define GLSW_GORCL_GORCL_S 0
8227 #define GLSW_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
8228 #define GLSW_GOTCH(_i) (0x00302004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8230 #define GLSW_GOTCH_GOTCH_S 0
8231 #define GLSW_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
8232 #define GLSW_GOTCL(_i) (0x00302000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8234 #define GLSW_GOTCL_GOTCL_S 0
8235 #define GLSW_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
8236 #define GLSW_MPRCH(_i) (0x00346104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8238 #define GLSW_MPRCH_MPRCH_S 0
8239 #define GLSW_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
8240 #define GLSW_MPRCL(_i) (0x00346100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8242 #define GLSW_MPRCL_MPRCL_S 0
8243 #define GLSW_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8244 #define GLSW_MPTCH(_i) (0x00310104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8246 #define GLSW_MPTCH_MPTCH_S 0
8247 #define GLSW_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
8248 #define GLSW_MPTCL(_i) (0x00310100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8250 #define GLSW_MPTCL_MPTCL_S 0
8251 #define GLSW_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8252 #define GLSW_UPRCH(_i) (0x00346004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8254 #define GLSW_UPRCH_UPRCH_S 0
8255 #define GLSW_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8256 #define GLSW_UPRCL(_i) (0x00346000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8258 #define GLSW_UPRCL_UPRCL_S 0
8259 #define GLSW_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8260 #define GLSW_UPTCH(_i) (0x00310004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8262 #define GLSW_UPTCH_UPTCH_S 0
8263 #define GLSW_UPTCH_UPTCH_M MAKEMASK(0xFF, 0)
8264 #define GLSW_UPTCL(_i) (0x00310000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */
8266 #define GLSW_UPTCL_UPTCL_S 0
8267 #define GLSW_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8268 #define GLSWID_RUPP(_i) (0x00345000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
8270 #define GLSWID_RUPP_RUPP_S 0
8271 #define GLSWID_RUPP_RUPP_M MAKEMASK(0xFFFFFFFF, 0)
8272 #define GLV_BPRCH(_i) (0x003B6004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8274 #define GLV_BPRCH_BPRCH_S 0
8275 #define GLV_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
8276 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8278 #define GLV_BPRCL_BPRCL_S 0
8279 #define GLV_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8280 #define GLV_BPTCH(_i) (0x0030E004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8282 #define GLV_BPTCH_BPTCH_S 0
8283 #define GLV_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
8284 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8286 #define GLV_BPTCL_BPTCL_S 0
8287 #define GLV_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8288 #define GLV_GORCH(_i) (0x003B0004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8290 #define GLV_GORCH_GORCH_S 0
8291 #define GLV_GORCH_GORCH_M MAKEMASK(0xFF, 0)
8292 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8294 #define GLV_GORCL_GORCL_S 0
8295 #define GLV_GORCL_GORCL_M MAKEMASK(0xFFFFFFFF, 0)
8296 #define GLV_GOTCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8298 #define GLV_GOTCH_GOTCH_S 0
8299 #define GLV_GOTCH_GOTCH_M MAKEMASK(0xFF, 0)
8300 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8302 #define GLV_GOTCL_GOTCL_S 0
8303 #define GLV_GOTCL_GOTCL_M MAKEMASK(0xFFFFFFFF, 0)
8304 #define GLV_MPRCH(_i) (0x003B4004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8306 #define GLV_MPRCH_MPRCH_S 0
8307 #define GLV_MPRCH_MPRCH_M MAKEMASK(0xFF, 0)
8308 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8310 #define GLV_MPRCL_MPRCL_S 0
8311 #define GLV_MPRCL_MPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8312 #define GLV_MPTCH(_i) (0x0030C004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8314 #define GLV_MPTCH_MPTCH_S 0
8315 #define GLV_MPTCH_MPTCH_M MAKEMASK(0xFF, 0)
8316 #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8318 #define GLV_MPTCL_MPTCL_S 0
8319 #define GLV_MPTCL_MPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8320 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8322 #define GLV_RDPC_RDPC_S 0
8323 #define GLV_RDPC_RDPC_M MAKEMASK(0xFFFFFFFF, 0)
8324 #define GLV_REPC(_i) (0x00295804 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8326 #define GLV_REPC_NO_DESC_CNT_S 0
8327 #define GLV_REPC_NO_DESC_CNT_M MAKEMASK(0xFFFF, 0)
8329 #define GLV_REPC_ERROR_CNT_M MAKEMASK(0xFFFF, 16)
8330 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8332 #define GLV_TEPC_TEPC_S 0
8333 #define GLV_TEPC_TEPC_M MAKEMASK(0xFFFFFFFF, 0)
8334 #define GLV_UPRCH(_i) (0x003B2004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8336 #define GLV_UPRCH_UPRCH_S 0
8337 #define GLV_UPRCH_UPRCH_M MAKEMASK(0xFF, 0)
8338 #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8340 #define GLV_UPRCL_UPRCL_S 0
8341 #define GLV_UPRCL_UPRCL_M MAKEMASK(0xFFFFFFFF, 0)
8342 #define GLV_UPTCH(_i) (0x0030A004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8344 #define GLV_UPTCH_GLVUPTCH_S 0
8345 #define GLV_UPTCH_GLVUPTCH_M MAKEMASK(0xFF, 0)
8346 #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */
8348 #define GLV_UPTCL_UPTCL_S 0
8349 #define GLV_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
8350 #define GLVEBUP_RBCH(_i, _j) (0x00343004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8352 #define GLVEBUP_RBCH_UPBCH_S 0
8353 #define GLVEBUP_RBCH_UPBCH_M MAKEMASK(0xFF, 0)
8354 #define GLVEBUP_RBCL(_i, _j) (0x00343000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8356 #define GLVEBUP_RBCL_UPBCL_S 0
8357 #define GLVEBUP_RBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0)
8358 #define GLVEBUP_RPCH(_i, _j) (0x00344004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8360 #define GLVEBUP_RPCH_UPPCH_S 0
8361 #define GLVEBUP_RPCH_UPPCH_M MAKEMASK(0xFF, 0)
8362 #define GLVEBUP_RPCL(_i, _j) (0x00344000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8364 #define GLVEBUP_RPCL_UPPCL_S 0
8365 #define GLVEBUP_RPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0)
8366 #define GLVEBUP_TBCH(_i, _j) (0x00306004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8368 #define GLVEBUP_TBCH_UPBCH_S 0
8369 #define GLVEBUP_TBCH_UPBCH_M MAKEMASK(0xFF, 0)
8370 #define GLVEBUP_TBCL(_i, _j) (0x00306000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8372 #define GLVEBUP_TBCL_UPBCL_S 0
8373 #define GLVEBUP_TBCL_UPBCL_M MAKEMASK(0xFFFFFFFF, 0)
8374 #define GLVEBUP_TPCH(_i, _j) (0x00308004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8376 #define GLVEBUP_TPCH_UPPCH_S 0
8377 #define GLVEBUP_TPCH_UPPCH_M MAKEMASK(0xFF, 0)
8378 #define GLVEBUP_TPCL(_i, _j) (0x00308000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */
8380 #define GLVEBUP_TPCL_UPPCL_S 0
8381 #define GLVEBUP_TPCL_UPPCL_M MAKEMASK(0xFFFFFFFF, 0)
8382 #define PRTRPB_LDPC 0x000AC280 /* Reset Source: CORER */
8383 #define PRTRPB_LDPC_CRCERRS_S 0
8384 #define PRTRPB_LDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
8385 #define PRTRPB_RDPC 0x000AC260 /* Reset Source: CORER */
8386 #define PRTRPB_RDPC_CRCERRS_S 0
8387 #define PRTRPB_RDPC_CRCERRS_M MAKEMASK(0xFFFFFFFF, 0)
8388 #define PRTTPB_STAT_TC_BYTES_SENTL(_i) (0x00098200 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8390 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S 0
8391 #define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
8392 #define TPB_PRTTPB_STAT_PKT_SENT(_i) (0x00099470 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
8394 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0
8395 #define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0)
8396 #define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8398 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0
8399 #define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
8400 #define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */
8401 #define EMP_SWT_PRUNIND_OPCODE_S 0
8402 #define EMP_SWT_PRUNIND_OPCODE_M MAKEMASK(0xF, 0)
8404 #define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M MAKEMASK(0x3FF, 4)
8406 #define EMP_SWT_PRUNIND_VSI_NUM_M MAKEMASK(0x3FF, 16)
8409 #define EMP_SWT_REPIND 0x0020401C /* Reset Source: CORER */
8410 #define EMP_SWT_REPIND_OPCODE_S 0
8411 #define EMP_SWT_REPIND_OPCODE_M MAKEMASK(0xF, 0)
8413 #define EMP_SWT_REPIND_LIST_INDEX_NUMBER_M MAKEMASK(0x3FF, 4)
8415 #define EMP_SWT_REPIND_VSI_NUM_M MAKEMASK(0x3FF, 16)
8418 #define GL_OVERRIDEC 0x002040A4 /* Reset Source: CORER */
8419 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_S 0
8420 #define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_M MAKEMASK(0xFFFF, 0)
8422 #define GL_OVERRIDEC_LAST_VSI_M MAKEMASK(0x3FF, 16)
8423 #define GL_PLG_AVG_CALC_CFG 0x0020A5AC /* Reset Source: CORER */
8424 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_S 0
8425 #define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_M MAKEMASK(0x7FFFFFFF, 0)
8428 #define GL_PLG_AVG_CALC_ST 0x0020A5B0 /* Reset Source: CORER */
8429 #define GL_PLG_AVG_CALC_ST_IN_DATA_S 0
8430 #define GL_PLG_AVG_CALC_ST_IN_DATA_M MAKEMASK(0x7FFF, 0)
8432 #define GL_PLG_AVG_CALC_ST_OUT_DATA_M MAKEMASK(0x7FFF, 16)
8435 #define GL_PRE_CFG_CMD 0x00214090 /* Reset Source: CORER */
8436 #define GL_PRE_CFG_CMD_ADDR_S 0
8437 #define GL_PRE_CFG_CMD_ADDR_M MAKEMASK(0x1FFF, 0)
8439 #define GL_PRE_CFG_CMD_TBLIDX_M MAKEMASK(0x7, 16)
8444 #define GL_PRE_CFG_DATA(_i) (0x00214074 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
8446 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_S 0
8447 #define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_M MAKEMASK(0xFFFFFFFF, 0)
8448 #define GL_SWT_FUNCFILT 0x001D2698 /* Reset Source: CORER */
8449 #define GL_SWT_FUNCFILT_FUNCFILT_S 0
8450 #define GL_SWT_FUNCFILT_FUNCFILT_M BIT(0)
8451 #define GL_SWT_FW_STS(_i) (0x00216000 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */
8453 #define GL_SWT_FW_STS_GL_SWT_FW_STS_S 0
8454 #define GL_SWT_FW_STS_GL_SWT_FW_STS_M MAKEMASK(0xFFFFFFFF, 0)
8455 #define GL_SWT_LAT_DOUBLE 0x00204004 /* Reset Source: CORER */
8456 #define GL_SWT_LAT_DOUBLE_BASE_S 0
8457 #define GL_SWT_LAT_DOUBLE_BASE_M MAKEMASK(0x7FF, 0)
8459 #define GL_SWT_LAT_DOUBLE_SIZE_M MAKEMASK(0x7FF, 16)
8460 #define GL_SWT_LAT_QUAD 0x00204008 /* Reset Source: CORER */
8461 #define GL_SWT_LAT_QUAD_BASE_S 0
8462 #define GL_SWT_LAT_QUAD_BASE_M MAKEMASK(0x7FF, 0)
8464 #define GL_SWT_LAT_QUAD_SIZE_M MAKEMASK(0x7FF, 16)
8465 #define GL_SWT_LAT_SINGLE 0x00204000 /* Reset Source: CORER */
8466 #define GL_SWT_LAT_SINGLE_BASE_S 0
8467 #define GL_SWT_LAT_SINGLE_BASE_M MAKEMASK(0x7FF, 0)
8469 #define GL_SWT_LAT_SINGLE_SIZE_M MAKEMASK(0x7FF, 16)
8470 #define GL_SWT_MD_PRI 0x002040AC /* Reset Source: CORER */
8471 #define GL_SWT_MD_PRI_VSI_PRI_S 0
8472 #define GL_SWT_MD_PRI_VSI_PRI_M MAKEMASK(0x7, 0)
8474 #define GL_SWT_MD_PRI_LB_PRI_M MAKEMASK(0x7, 4)
8476 #define GL_SWT_MD_PRI_LAN_EN_PRI_M MAKEMASK(0x7, 8)
8478 #define GL_SWT_MD_PRI_QH_PRI_M MAKEMASK(0x7, 12)
8480 #define GL_SWT_MD_PRI_QL_PRI_M MAKEMASK(0x7, 16)
8481 #define GL_SWT_MIRTARVSI(_i) (0x00204500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
8483 #define GL_SWT_MIRTARVSI_VFVMNUMBER_S 0
8484 #define GL_SWT_MIRTARVSI_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
8486 #define GL_SWT_MIRTARVSI_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
8488 #define GL_SWT_MIRTARVSI_PFNUMBER_M MAKEMASK(0x7, 12)
8490 #define GL_SWT_MIRTARVSI_TARGETVSI_M MAKEMASK(0x3FF, 20)
8493 #define GL_SWT_SWIDFVIDX 0x00214114 /* Reset Source: CORER */
8494 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_S 0
8495 #define GL_SWT_SWIDFVIDX_SWIDFVIDX_M MAKEMASK(0x3F, 0)
8498 #define GL_VP_SWITCHID(_i) (0x00214094 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
8500 #define GL_VP_SWITCHID_SWITCHID_S 0
8501 #define GL_VP_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0)
8502 #define GLSWID_STAT_BLOCK(_i) (0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
8504 #define GLSWID_STAT_BLOCK_VEBID_S 0
8505 #define GLSWID_STAT_BLOCK_VEBID_M MAKEMASK(0x1F, 0)
8508 #define GLSWT_ACT_RESP_0 0x0020A5A4 /* Reset Source: CORER */
8509 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_S 0
8510 #define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0)
8511 #define GLSWT_ACT_RESP_1 0x0020A5A8 /* Reset Source: CORER */
8512 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_S 0
8513 #define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_M MAKEMASK(0xFFFFFFFF, 0)
8514 #define GLSWT_ARB_MODE 0x0020A674 /* Reset Source: CORER */
8515 #define GLSWT_ARB_MODE_FLU_PRI_SHM_S 0
8516 #define GLSWT_ARB_MODE_FLU_PRI_SHM_M BIT(0)
8519 #define PRT_SBPVSI 0x00204120 /* Reset Source: CORER */
8520 #define PRT_SBPVSI_BAD_FRAMES_VSI_S 0
8521 #define PRT_SBPVSI_BAD_FRAMES_VSI_M MAKEMASK(0x3FF, 0)
8524 #define PRT_SCSTS 0x00204140 /* Reset Source: CORER */
8525 #define PRT_SCSTS_BSCA_S 0
8526 #define PRT_SCSTS_BSCA_M BIT(0)
8533 #define PRT_SWT_BSCCNT 0x00204160 /* Reset Source: CORER */
8534 #define PRT_SWT_BSCCNT_CCOUNT_S 0
8535 #define PRT_SWT_BSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0)
8536 #define PRT_SWT_BSCTRH 0x00204180 /* Reset Source: CORER */
8537 #define PRT_SWT_BSCTRH_UTRESH_S 0
8538 #define PRT_SWT_BSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0)
8539 #define PRT_SWT_MIREG 0x002042A0 /* Reset Source: CORER */
8540 #define PRT_SWT_MIREG_MIRRULE_S 0
8541 #define PRT_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0)
8544 #define PRT_SWT_MIRIG 0x00204280 /* Reset Source: CORER */
8545 #define PRT_SWT_MIRIG_MIRRULE_S 0
8546 #define PRT_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0)
8549 #define PRT_SWT_MSCCNT 0x00204100 /* Reset Source: CORER */
8550 #define PRT_SWT_MSCCNT_CCOUNT_S 0
8551 #define PRT_SWT_MSCCNT_CCOUNT_M MAKEMASK(0x1FFFFFF, 0)
8552 #define PRT_SWT_MSCTRH 0x002041C0 /* Reset Source: CORER */
8553 #define PRT_SWT_MSCTRH_UTRESH_S 0
8554 #define PRT_SWT_MSCTRH_UTRESH_M MAKEMASK(0x7FFFF, 0)
8555 #define PRT_SWT_SCBI 0x002041E0 /* Reset Source: CORER */
8556 #define PRT_SWT_SCBI_BI_S 0
8557 #define PRT_SWT_SCBI_BI_M MAKEMASK(0x1FFFFFF, 0)
8558 #define PRT_SWT_SCCRL 0x00204200 /* Reset Source: CORER */
8559 #define PRT_SWT_SCCRL_MDIPW_S 0
8560 #define PRT_SWT_SCCRL_MDIPW_M BIT(0)
8568 #define PRT_SWT_SCCRL_INTERVAL_M MAKEMASK(0xFFFFF, 8)
8569 #define PRT_TCTUPR(_i) (0x00040840 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
8571 #define PRT_TCTUPR_UP0_S 0
8572 #define PRT_TCTUPR_UP0_M MAKEMASK(0x7, 0)
8574 #define PRT_TCTUPR_UP1_M MAKEMASK(0x7, 4)
8576 #define PRT_TCTUPR_UP2_M MAKEMASK(0x7, 8)
8578 #define PRT_TCTUPR_UP3_M MAKEMASK(0x7, 12)
8580 #define PRT_TCTUPR_UP4_M MAKEMASK(0x7, 16)
8582 #define PRT_TCTUPR_UP5_M MAKEMASK(0x7, 20)
8584 #define PRT_TCTUPR_UP6_M MAKEMASK(0x7, 24)
8586 #define PRT_TCTUPR_UP7_M MAKEMASK(0x7, 28)
8587 #define GLHH_ART_CTL 0x000A41D4 /* Reset Source: POR */
8588 #define GLHH_ART_CTL_ACTIVE_S 0
8589 #define GLHH_ART_CTL_ACTIVE_M BIT(0)
8596 #define GLHH_ART_DATA 0x000A41E0 /* Reset Source: POR */
8597 #define GLHH_ART_DATA_AGENT_TYPE_S 0
8598 #define GLHH_ART_DATA_AGENT_TYPE_M MAKEMASK(0x7, 0)
8602 #define GLHH_ART_DATA_MAX_DELAY_M MAKEMASK(0xF, 4)
8604 #define GLHH_ART_DATA_TIME_BASE_M MAKEMASK(0xF, 8)
8606 #define GLHH_ART_DATA_RSV_DATA_M MAKEMASK(0xFFFFF, 12)
8607 #define GLHH_ART_TIME_H 0x000A41D8 /* Reset Source: POR */
8608 #define GLHH_ART_TIME_H_ART_TIME_H_S 0
8609 #define GLHH_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8610 #define GLHH_ART_TIME_L 0x000A41DC /* Reset Source: POR */
8611 #define GLHH_ART_TIME_L_ART_TIME_L_S 0
8612 #define GLHH_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8613 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8615 #define GLTSYN_AUX_IN_0_EVNTLVL_S 0
8616 #define GLTSYN_AUX_IN_0_EVNTLVL_M MAKEMASK(0x3, 0)
8619 #define GLTSYN_AUX_IN_1(_i) (0x000889E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8621 #define GLTSYN_AUX_IN_1_EVNTLVL_S 0
8622 #define GLTSYN_AUX_IN_1_EVNTLVL_M MAKEMASK(0x3, 0)
8625 #define GLTSYN_AUX_IN_2(_i) (0x000889E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8627 #define GLTSYN_AUX_IN_2_EVNTLVL_S 0
8628 #define GLTSYN_AUX_IN_2_EVNTLVL_M MAKEMASK(0x3, 0)
8631 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8633 #define GLTSYN_AUX_OUT_0_OUT_ENA_S 0
8634 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
8636 #define GLTSYN_AUX_OUT_0_OUTMOD_M MAKEMASK(0x3, 1)
8642 #define GLTSYN_AUX_OUT_0_PULSEW_M MAKEMASK(0xF, 8)
8643 #define GLTSYN_AUX_OUT_1(_i) (0x000889A0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8645 #define GLTSYN_AUX_OUT_1_OUT_ENA_S 0
8646 #define GLTSYN_AUX_OUT_1_OUT_ENA_M BIT(0)
8648 #define GLTSYN_AUX_OUT_1_OUTMOD_M MAKEMASK(0x3, 1)
8654 #define GLTSYN_AUX_OUT_1_PULSEW_M MAKEMASK(0xF, 8)
8655 #define GLTSYN_AUX_OUT_2(_i) (0x000889A8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8657 #define GLTSYN_AUX_OUT_2_OUT_ENA_S 0
8658 #define GLTSYN_AUX_OUT_2_OUT_ENA_M BIT(0)
8660 #define GLTSYN_AUX_OUT_2_OUTMOD_M MAKEMASK(0x3, 1)
8666 #define GLTSYN_AUX_OUT_2_PULSEW_M MAKEMASK(0xF, 8)
8667 #define GLTSYN_AUX_OUT_3(_i) (0x000889B0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8669 #define GLTSYN_AUX_OUT_3_OUT_ENA_S 0
8670 #define GLTSYN_AUX_OUT_3_OUT_ENA_M BIT(0)
8672 #define GLTSYN_AUX_OUT_3_OUTMOD_M MAKEMASK(0x3, 1)
8678 #define GLTSYN_AUX_OUT_3_PULSEW_M MAKEMASK(0xF, 8)
8679 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8681 #define GLTSYN_CLKO_0_TSYNCLKO_S 0
8682 #define GLTSYN_CLKO_0_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8683 #define GLTSYN_CLKO_1(_i) (0x000889C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8685 #define GLTSYN_CLKO_1_TSYNCLKO_S 0
8686 #define GLTSYN_CLKO_1_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8687 #define GLTSYN_CLKO_2(_i) (0x000889C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8689 #define GLTSYN_CLKO_2_TSYNCLKO_S 0
8690 #define GLTSYN_CLKO_2_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8691 #define GLTSYN_CLKO_3(_i) (0x000889D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8693 #define GLTSYN_CLKO_3_TSYNCLKO_S 0
8694 #define GLTSYN_CLKO_3_TSYNCLKO_M MAKEMASK(0xFFFFFFFF, 0)
8695 #define GLTSYN_CMD 0x00088810 /* Reset Source: CORER */
8696 #define GLTSYN_CMD_CMD_S 0
8697 #define GLTSYN_CMD_CMD_M MAKEMASK(0xFF, 0)
8700 #define GLTSYN_CMD_SYNC 0x00088814 /* Reset Source: CORER */
8701 #define GLTSYN_CMD_SYNC_SYNC_S 0
8702 #define GLTSYN_CMD_SYNC_SYNC_M MAKEMASK(0x3, 0)
8703 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8705 #define GLTSYN_ENA_TSYN_ENA_S 0
8706 #define GLTSYN_ENA_TSYN_ENA_M BIT(0)
8707 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8709 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_S 0
8710 #define GLTSYN_EVNT_H_0_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8711 #define GLTSYN_EVNT_H_1(_i) (0x00088980 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8713 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_S 0
8714 #define GLTSYN_EVNT_H_1_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8715 #define GLTSYN_EVNT_H_2(_i) (0x00088990 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8717 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_S 0
8718 #define GLTSYN_EVNT_H_2_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8719 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8721 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_S 0
8722 #define GLTSYN_EVNT_L_0_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8723 #define GLTSYN_EVNT_L_1(_i) (0x00088978 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8725 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_S 0
8726 #define GLTSYN_EVNT_L_1_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8727 #define GLTSYN_EVNT_L_2(_i) (0x00088988 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8729 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_S 0
8730 #define GLTSYN_EVNT_L_2_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8731 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8733 #define GLTSYN_HHTIME_H_TSYNEVNT_H_S 0
8734 #define GLTSYN_HHTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
8735 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8737 #define GLTSYN_HHTIME_L_TSYNEVNT_L_S 0
8738 #define GLTSYN_HHTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
8739 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8741 #define GLTSYN_INCVAL_H_INCVAL_H_S 0
8742 #define GLTSYN_INCVAL_H_INCVAL_H_M MAKEMASK(0xFF, 0)
8743 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8745 #define GLTSYN_INCVAL_L_INCVAL_L_S 0
8746 #define GLTSYN_INCVAL_L_INCVAL_L_M MAKEMASK(0xFFFFFFFF, 0)
8747 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8749 #define GLTSYN_SHADJ_H_ADJUST_H_S 0
8750 #define GLTSYN_SHADJ_H_ADJUST_H_M MAKEMASK(0xFFFFFFFF, 0)
8751 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8753 #define GLTSYN_SHADJ_L_ADJUST_L_S 0
8754 #define GLTSYN_SHADJ_L_ADJUST_L_M MAKEMASK(0xFFFFFFFF, 0)
8755 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8757 #define GLTSYN_SHTIME_0_TSYNTIME_0_S 0
8758 #define GLTSYN_SHTIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0)
8759 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8761 #define GLTSYN_SHTIME_H_TSYNTIME_H_S 0
8762 #define GLTSYN_SHTIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8763 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8765 #define GLTSYN_SHTIME_L_TSYNTIME_L_S 0
8766 #define GLTSYN_SHTIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8767 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8769 #define GLTSYN_STAT_EVENT0_S 0
8770 #define GLTSYN_STAT_EVENT0_M BIT(0)
8783 #define GLTSYN_SYNC_DLAY 0x00088818 /* Reset Source: CORER */
8784 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_S 0
8785 #define GLTSYN_SYNC_DLAY_SYNC_DELAY_M MAKEMASK(0x1F, 0)
8786 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8788 #define GLTSYN_TGT_H_0_TSYNTGTT_H_S 0
8789 #define GLTSYN_TGT_H_0_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8790 #define GLTSYN_TGT_H_1(_i) (0x00088940 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8792 #define GLTSYN_TGT_H_1_TSYNTGTT_H_S 0
8793 #define GLTSYN_TGT_H_1_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8794 #define GLTSYN_TGT_H_2(_i) (0x00088950 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8796 #define GLTSYN_TGT_H_2_TSYNTGTT_H_S 0
8797 #define GLTSYN_TGT_H_2_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8798 #define GLTSYN_TGT_H_3(_i) (0x00088960 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8800 #define GLTSYN_TGT_H_3_TSYNTGTT_H_S 0
8801 #define GLTSYN_TGT_H_3_TSYNTGTT_H_M MAKEMASK(0xFFFFFFFF, 0)
8802 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8804 #define GLTSYN_TGT_L_0_TSYNTGTT_L_S 0
8805 #define GLTSYN_TGT_L_0_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8806 #define GLTSYN_TGT_L_1(_i) (0x00088938 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8808 #define GLTSYN_TGT_L_1_TSYNTGTT_L_S 0
8809 #define GLTSYN_TGT_L_1_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8810 #define GLTSYN_TGT_L_2(_i) (0x00088948 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8812 #define GLTSYN_TGT_L_2_TSYNTGTT_L_S 0
8813 #define GLTSYN_TGT_L_2_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8814 #define GLTSYN_TGT_L_3(_i) (0x00088958 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8816 #define GLTSYN_TGT_L_3_TSYNTGTT_L_S 0
8817 #define GLTSYN_TGT_L_3_TSYNTGTT_L_M MAKEMASK(0xFFFFFFFF, 0)
8818 #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8820 #define GLTSYN_TIME_0_TSYNTIME_0_S 0
8821 #define GLTSYN_TIME_0_TSYNTIME_0_M MAKEMASK(0xFFFFFFFF, 0)
8822 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8824 #define GLTSYN_TIME_H_TSYNTIME_H_S 0
8825 #define GLTSYN_TIME_H_TSYNTIME_H_M MAKEMASK(0xFFFFFFFF, 0)
8826 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
8828 #define GLTSYN_TIME_L_TSYNTIME_L_S 0
8829 #define GLTSYN_TIME_L_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
8830 #define PFHH_SEM 0x000A4200 /* Reset Source: PFR */
8831 #define PFHH_SEM_BUSY_S 0
8832 #define PFHH_SEM_BUSY_M BIT(0)
8834 #define PFHH_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
8835 #define PFTSYN_SEM 0x00088880 /* Reset Source: PFR */
8836 #define PFTSYN_SEM_BUSY_S 0
8837 #define PFTSYN_SEM_BUSY_M BIT(0)
8839 #define PFTSYN_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
8840 #define GLPE_TSCD_FLR(_i) (0x0051E24C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
8842 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_S 0
8843 #define GLPE_TSCD_FLR_DRAIN_VCTR_ID_M MAKEMASK(0x3, 0)
8845 #define GLPE_TSCD_FLR_PORT_M MAKEMASK(0x7, 2)
8847 #define GLPE_TSCD_FLR_PF_NUM_M MAKEMASK(0x7, 5)
8849 #define GLPE_TSCD_FLR_VM_VF_TYPE_M MAKEMASK(0x3, 8)
8851 #define GLPE_TSCD_FLR_VM_VF_NUM_M MAKEMASK(0x3FF, 16)
8854 #define GLPE_TSCD_PEPM 0x0051E228 /* Reset Source: CORER */
8855 #define GLPE_TSCD_PEPM_MDQ_CREDITS_S 0
8856 #define GLPE_TSCD_PEPM_MDQ_CREDITS_M MAKEMASK(0xFF, 0)
8857 #define PF_VIRT_VSTATUS 0x0009E680 /* Reset Source: PFR */
8858 #define PF_VIRT_VSTATUS_NUM_VFS_S 0
8859 #define PF_VIRT_VSTATUS_NUM_VFS_M MAKEMASK(0xFF, 0)
8861 #define PF_VIRT_VSTATUS_TOTAL_VFS_M MAKEMASK(0xFF, 8)
8864 #define PF_VT_PFALLOC 0x001D2480 /* Reset Source: CORER */
8865 #define PF_VT_PFALLOC_FIRSTVF_S 0
8866 #define PF_VT_PFALLOC_FIRSTVF_M MAKEMASK(0xFF, 0)
8868 #define PF_VT_PFALLOC_LASTVF_M MAKEMASK(0xFF, 8)
8871 #define PF_VT_PFALLOC_HIF 0x0009DD80 /* Reset Source: PCIR */
8872 #define PF_VT_PFALLOC_HIF_FIRSTVF_S 0
8873 #define PF_VT_PFALLOC_HIF_FIRSTVF_M MAKEMASK(0xFF, 0)
8875 #define PF_VT_PFALLOC_HIF_LASTVF_M MAKEMASK(0xFF, 8)
8878 #define PF_VT_PFALLOC_PCIE 0x000BE080 /* Reset Source: PCIR */
8879 #define PF_VT_PFALLOC_PCIE_FIRSTVF_S 0
8880 #define PF_VT_PFALLOC_PCIE_FIRSTVF_M MAKEMASK(0xFF, 0)
8882 #define PF_VT_PFALLOC_PCIE_LASTVF_M MAKEMASK(0xFF, 8)
8885 #define VSI_L2TAGSTXVALID(_VSI) (0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8887 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_S 0
8888 #define VSI_L2TAGSTXVALID_L2TAG1INSERTID_M MAKEMASK(0x7, 0)
8892 #define VSI_L2TAGSTXVALID_L2TAG2INSERTID_M MAKEMASK(0x7, 4)
8896 #define VSI_L2TAGSTXVALID_TIR0INSERTID_M MAKEMASK(0x7, 16)
8900 #define VSI_L2TAGSTXVALID_TIR1INSERTID_M MAKEMASK(0x7, 20)
8904 #define VSI_L2TAGSTXVALID_TIR2INSERTID_M MAKEMASK(0x7, 24)
8907 #define VSI_PASID(_VSI) (0x0009C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8909 #define VSI_PASID_PASID_S 0
8910 #define VSI_PASID_PASID_M MAKEMASK(0xFFFFF, 0)
8913 #define VSI_RUPR(_VSI) (0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8915 #define VSI_RUPR_UP0_S 0
8916 #define VSI_RUPR_UP0_M MAKEMASK(0x7, 0)
8918 #define VSI_RUPR_UP1_M MAKEMASK(0x7, 3)
8920 #define VSI_RUPR_UP2_M MAKEMASK(0x7, 6)
8922 #define VSI_RUPR_UP3_M MAKEMASK(0x7, 9)
8924 #define VSI_RUPR_UP4_M MAKEMASK(0x7, 12)
8926 #define VSI_RUPR_UP5_M MAKEMASK(0x7, 15)
8928 #define VSI_RUPR_UP6_M MAKEMASK(0x7, 18)
8930 #define VSI_RUPR_UP7_M MAKEMASK(0x7, 21)
8931 #define VSI_RXSWCTRL(_VSI) (0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8936 #define VSI_RXSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 9)
8939 #define VSI_SRCSWCTRL(_VSI) (0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8941 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_S 0
8942 #define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M BIT(0)
8950 #define VSI_SRCSWCTRL_PRUNEENABLE_M MAKEMASK(0xF, 4)
8951 #define VSI_SWITCHID(_VSI) (0x00215000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8953 #define VSI_SWITCHID_SWITCHID_S 0
8954 #define VSI_SWITCHID_SWITCHID_M MAKEMASK(0xFF, 0)
8955 #define VSI_SWT_MIREG(_VSI) (0x00207000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8957 #define VSI_SWT_MIREG_MIRRULE_S 0
8958 #define VSI_SWT_MIREG_MIRRULE_M MAKEMASK(0x3F, 0)
8961 #define VSI_SWT_MIRIG(_VSI) (0x00208000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8963 #define VSI_SWT_MIRIG_MIRRULE_S 0
8964 #define VSI_SWT_MIRIG_MIRRULE_M MAKEMASK(0x3F, 0)
8967 #define VSI_TAIR(_VSI) (0x00044000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
8969 #define VSI_TAIR_PORT_TAG_ID_S 0
8970 #define VSI_TAIR_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8971 #define VSI_TAR(_VSI) (0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8973 #define VSI_TAR_ACCEPTTAGGED_S 0
8974 #define VSI_TAR_ACCEPTTAGGED_M MAKEMASK(0x3FF, 0)
8976 #define VSI_TAR_ACCEPTUNTAGGED_M MAKEMASK(0x3FF, 16)
8977 #define VSI_TIR_0(_VSI) (0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8979 #define VSI_TIR_0_PORT_TAG_ID_S 0
8980 #define VSI_TIR_0_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8981 #define VSI_TIR_1(_VSI) (0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8983 #define VSI_TIR_1_PORT_TAG_ID_S 0
8984 #define VSI_TIR_1_PORT_TAG_ID_M MAKEMASK(0xFFFFFFFF, 0)
8985 #define VSI_TIR_2(_VSI) (0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8987 #define VSI_TIR_2_PORT_TAG_ID_S 0
8988 #define VSI_TIR_2_PORT_TAG_ID_M MAKEMASK(0xFFFF, 0)
8989 #define VSI_TSR(_VSI) (0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8991 #define VSI_TSR_STRIPTAG_S 0
8992 #define VSI_TSR_STRIPTAG_M MAKEMASK(0x3FF, 0)
8994 #define VSI_TSR_SHOWTAG_M MAKEMASK(0x3FF, 10)
8996 #define VSI_TSR_SHOWPRIONLY_M MAKEMASK(0x3FF, 20)
8997 #define VSI_TUPIOM(_VSI) (0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
8999 #define VSI_TUPIOM_UP0_S 0
9000 #define VSI_TUPIOM_UP0_M MAKEMASK(0x7, 0)
9002 #define VSI_TUPIOM_UP1_M MAKEMASK(0x7, 3)
9004 #define VSI_TUPIOM_UP2_M MAKEMASK(0x7, 6)
9006 #define VSI_TUPIOM_UP3_M MAKEMASK(0x7, 9)
9008 #define VSI_TUPIOM_UP4_M MAKEMASK(0x7, 12)
9010 #define VSI_TUPIOM_UP5_M MAKEMASK(0x7, 15)
9012 #define VSI_TUPIOM_UP6_M MAKEMASK(0x7, 18)
9014 #define VSI_TUPIOM_UP7_M MAKEMASK(0x7, 21)
9015 #define VSI_TUPR(_VSI) (0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
9017 #define VSI_TUPR_UP0_S 0
9018 #define VSI_TUPR_UP0_M MAKEMASK(0x7, 0)
9020 #define VSI_TUPR_UP1_M MAKEMASK(0x7, 3)
9022 #define VSI_TUPR_UP2_M MAKEMASK(0x7, 6)
9024 #define VSI_TUPR_UP3_M MAKEMASK(0x7, 9)
9026 #define VSI_TUPR_UP4_M MAKEMASK(0x7, 12)
9028 #define VSI_TUPR_UP5_M MAKEMASK(0x7, 15)
9030 #define VSI_TUPR_UP6_M MAKEMASK(0x7, 18)
9032 #define VSI_TUPR_UP7_M MAKEMASK(0x7, 21)
9033 #define VSI_VSI2F(_VSI) (0x001D0000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
9035 #define VSI_VSI2F_VFVMNUMBER_S 0
9036 #define VSI_VSI2F_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
9038 #define VSI_VSI2F_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
9040 #define VSI_VSI2F_PFNUMBER_M MAKEMASK(0x7, 12)
9042 #define VSI_VSI2F_BUFFERNUMBER_M MAKEMASK(0x7, 16)
9044 #define VSI_VSI2F_VSI_NUMBER_M MAKEMASK(0x3FF, 20)
9047 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
9049 #define VSIQF_FD_CNT_FD_GCNT_S 0
9051 #define E800_VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0x3FFF, 0)
9052 #define E830_VSIQF_FD_CNT_FD_GCNT_M MAKEMASK(0xFFFF, 0)
9055 #define E800_VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0x3FFF, 16)
9056 #define E830_VSIQF_FD_CNT_FD_BCNT_M MAKEMASK(0xFFFF, 16)
9057 #define VSIQF_FD_CTL1(_VSI) (0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
9059 #define VSIQF_FD_CTL1_FLT_ENA_S 0
9060 #define VSIQF_FD_CTL1_FLT_ENA_M BIT(0)
9065 #define VSIQF_FD_DFLT(_VSI) (0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
9067 #define VSIQF_FD_DFLT_DEFLT_QINDX_S 0
9068 #define VSIQF_FD_DFLT_DEFLT_QINDX_M MAKEMASK(0x7FF, 0)
9070 #define VSIQF_FD_DFLT_DEFLT_TOQUEUE_M MAKEMASK(0x7, 12)
9072 #define VSIQF_FD_DFLT_COMP_QINDX_M MAKEMASK(0x7FF, 16)
9074 #define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_M MAKEMASK(0x7, 28)
9077 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
9079 #define VSIQF_FD_SIZE_FD_GSIZE_S 0
9081 #define E800_VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0x3FFF, 0)
9082 #define E830_VSIQF_FD_SIZE_FD_GSIZE_M MAKEMASK(0xFFFF, 0)
9085 #define E800_VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0x3FFF, 16)
9086 #define E830_VSIQF_FD_SIZE_FD_BSIZE_M MAKEMASK(0xFFFF, 16)
9087 #define VSIQF_HASH_CTL(_VSI) (0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
9089 #define VSIQF_HASH_CTL_HASH_LUT_SEL_S 0
9090 #define VSIQF_HASH_CTL_HASH_LUT_SEL_M MAKEMASK(0x3, 0)
9092 #define VSIQF_HASH_CTL_GLOB_LUT_M MAKEMASK(0xF, 2)
9094 #define VSIQF_HASH_CTL_HASH_SCHEME_M MAKEMASK(0x3, 6)
9096 #define VSIQF_HASH_CTL_TC_OVER_SEL_M MAKEMASK(0x1F, 8)
9099 #define VSIQF_HKEY(_i, _VSI) (0x00400000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...12, _VSI=0...767 */ /* Reset Source: PFR */
9101 #define VSIQF_HKEY_KEY_0_S 0
9102 #define VSIQF_HKEY_KEY_0_M MAKEMASK(0xFF, 0)
9104 #define VSIQF_HKEY_KEY_1_M MAKEMASK(0xFF, 8)
9106 #define VSIQF_HKEY_KEY_2_M MAKEMASK(0xFF, 16)
9108 #define VSIQF_HKEY_KEY_3_M MAKEMASK(0xFF, 24)
9109 #define VSIQF_HLUT(_i, _VSI) (0x00420000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...15, _VSI=0...767 */ /* Reset Source: PFR */
9111 #define VSIQF_HLUT_LUT0_S 0
9112 #define VSIQF_HLUT_LUT0_M MAKEMASK(0xF, 0)
9114 #define VSIQF_HLUT_LUT1_M MAKEMASK(0xF, 8)
9116 #define VSIQF_HLUT_LUT2_M MAKEMASK(0xF, 16)
9118 #define VSIQF_HLUT_LUT3_M MAKEMASK(0xF, 24)
9119 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
9121 #define VSIQF_PE_CTL1_PE_FLTENA_S 0
9122 #define VSIQF_PE_CTL1_PE_FLTENA_M BIT(0)
9123 #define VSIQF_TC_REGION(_i, _VSI) (0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: CORER */
9125 #define VSIQF_TC_REGION_TC_BASE0_S 0
9126 #define VSIQF_TC_REGION_TC_BASE0_M MAKEMASK(0x7FF, 0)
9128 #define VSIQF_TC_REGION_TC_SIZE0_M MAKEMASK(0xF, 11)
9130 #define VSIQF_TC_REGION_TC_BASE1_M MAKEMASK(0x7FF, 16)
9132 #define VSIQF_TC_REGION_TC_SIZE1_M MAKEMASK(0xF, 27)
9133 #define GLPM_WUMC 0x0009DEE4 /* Reset Source: POR */
9135 #define GLPM_WUMC_MNG_WU_PF_M MAKEMASK(0xFF, 16)
9136 #define PFPM_APM 0x000B8080 /* Reset Source: POR */
9137 #define PFPM_APM_APME_S 0
9138 #define PFPM_APM_APME_M BIT(0)
9139 #define PFPM_WUC 0x0009DC80 /* Reset Source: POR */
9142 #define PFPM_WUFC 0x0009DC00 /* Reset Source: POR */
9143 #define PFPM_WUFC_LNKC_S 0
9144 #define PFPM_WUFC_LNKC_M BIT(0)
9183 #define PFPM_WUS 0x0009DB80 /* Reset Source: POR */
9184 #define PFPM_WUS_LNKC_S 0
9185 #define PFPM_WUS_LNKC_M BIT(0)
9211 #define E800_PRTPM_SAH(_i) (0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9212 #define E830_PRTPM_SAH(_i) (0x001E2380 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9214 #define PRTPM_SAH_PFPM_SAH_S 0
9215 #define PRTPM_SAH_PFPM_SAH_M MAKEMASK(0xFFFF, 0)
9217 #define PRTPM_SAH_PF_NUM_M MAKEMASK(0xF, 26)
9223 #define E800_PRTPM_SAL(_i) (0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9224 #define E830_PRTPM_SAL(_i) (0x001E2300 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */
9226 #define PRTPM_SAL_PFPM_SAL_S 0
9227 #define PRTPM_SAL_PFPM_SAL_M MAKEMASK(0xFFFFFFFF, 0)
9228 #define GLPE_CQM_FUNC_INVALIDATE 0x00503300 /* Reset Source: CORER */
9229 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_S 0
9230 #define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_M MAKEMASK(0x7, 0)
9232 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_M MAKEMASK(0x3FF, 3)
9234 #define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_M MAKEMASK(0x3, 13)
9238 #define E800_VFPE_MRTEIDXMASK 0x00009000 /* Reset Source: PFR */
9239 #define E830_VFPE_MRTEIDXMASK(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
9240 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S 0
9241 #define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
9242 #define GLTSYN_HH_DLAY 0x0008881C /* Reset Source: CORER */
9243 #define GLTSYN_HH_DLAY_SYNC_DELAY_S 0
9244 #define GLTSYN_HH_DLAY_SYNC_DELAY_M MAKEMASK(0xF, 0)
9245 #define VF_MBX_ARQBAH1 0x00006000 /* Reset Source: CORER */
9246 #define VF_MBX_ARQBAH1_ARQBAH_S 0
9247 #define VF_MBX_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9248 #define VF_MBX_ARQBAL1 0x00006C00 /* Reset Source: CORER */
9249 #define VF_MBX_ARQBAL1_ARQBAL_LSB_S 0
9250 #define VF_MBX_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9252 #define VF_MBX_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9253 #define VF_MBX_ARQH1 0x00007400 /* Reset Source: CORER */
9254 #define VF_MBX_ARQH1_ARQH_S 0
9255 #define VF_MBX_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9256 #define VF_MBX_ARQLEN1 0x00008000 /* Reset Source: PFR */
9257 #define VF_MBX_ARQLEN1_ARQLEN_S 0
9258 #define VF_MBX_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9267 #define VF_MBX_ARQT1 0x00007000 /* Reset Source: CORER */
9268 #define VF_MBX_ARQT1_ARQT_S 0
9269 #define VF_MBX_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9270 #define VF_MBX_ATQBAH1 0x00007800 /* Reset Source: CORER */
9271 #define VF_MBX_ATQBAH1_ATQBAH_S 0
9272 #define VF_MBX_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9273 #define VF_MBX_ATQBAL1 0x00007C00 /* Reset Source: CORER */
9275 #define VF_MBX_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9276 #define VF_MBX_ATQH1 0x00006400 /* Reset Source: CORER */
9277 #define VF_MBX_ATQH1_ATQH_S 0
9278 #define VF_MBX_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9279 #define VF_MBX_ATQLEN1 0x00006800 /* Reset Source: PFR */
9280 #define VF_MBX_ATQLEN1_ATQLEN_S 0
9281 #define VF_MBX_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9290 #define VF_MBX_ATQT1 0x00008400 /* Reset Source: CORER */
9291 #define VF_MBX_ATQT1_ATQT_S 0
9292 #define VF_MBX_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9293 #define PFPCI_VF_FLUSH_DONE1 0x0000E400 /* Reset Source: PCIR */
9294 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_S 0
9295 #define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_M BIT(0)
9296 #define VFGEN_RSTAT1 0x00008800 /* Reset Source: VFR */
9297 #define VFGEN_RSTAT1_VFR_STATE_S 0
9298 #define VFGEN_RSTAT1_VFR_STATE_M MAKEMASK(0x3, 0)
9299 #define VFINT_DYN_CTL0 0x00005C00 /* Reset Source: CORER */
9300 #define VFINT_DYN_CTL0_INTENA_S 0
9301 #define VFINT_DYN_CTL0_INTENA_M BIT(0)
9307 #define VFINT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, 3)
9309 #define VFINT_DYN_CTL0_INTERVAL_M MAKEMASK(0xFFF, 5)
9313 #define VFINT_DYN_CTL0_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9318 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
9320 #define VFINT_DYN_CTLN_INTENA_S 0
9321 #define VFINT_DYN_CTLN_INTENA_M BIT(0)
9327 #define VFINT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, 3)
9329 #define VFINT_DYN_CTLN_INTERVAL_M MAKEMASK(0xFFF, 5)
9333 #define VFINT_DYN_CTLN_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9338 #define VFINT_ITR0(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */
9340 #define VFINT_ITR0_INTERVAL_S 0
9341 #define VFINT_ITR0_INTERVAL_M MAKEMASK(0xFFF, 0)
9343 #define E800_VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: CORER */
9344 #define E830_VFINT_ITRN(_i, _j) (0x00002800 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...2 */ /* Reset Source: CORER */
9348 #define VFINT_ITRN_INTERVAL_S 0
9349 #define VFINT_ITRN_INTERVAL_M MAKEMASK(0xFFF, 0)
9350 #define QRX_TAIL1(_QRX) (0x00002000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9352 #define QRX_TAIL1_TAIL_S 0
9353 #define QRX_TAIL1_TAIL_M MAKEMASK(0x1FFF, 0)
9354 #define QTX_TAIL(_DBQM) (0x00000000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9356 #define QTX_TAIL_QTX_COMM_DBELL_S 0
9357 #define QTX_TAIL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9358 #define VF_MBX_CPM_ARQBAH1 0x0000F060 /* Reset Source: CORER */
9359 #define VF_MBX_CPM_ARQBAH1_ARQBAH_S 0
9360 #define VF_MBX_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9361 #define VF_MBX_CPM_ARQBAL1 0x0000F050 /* Reset Source: CORER */
9362 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_S 0
9363 #define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9365 #define VF_MBX_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9366 #define VF_MBX_CPM_ARQH1 0x0000F080 /* Reset Source: CORER */
9367 #define VF_MBX_CPM_ARQH1_ARQH_S 0
9368 #define VF_MBX_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9369 #define VF_MBX_CPM_ARQLEN1 0x0000F070 /* Reset Source: PFR */
9370 #define VF_MBX_CPM_ARQLEN1_ARQLEN_S 0
9371 #define VF_MBX_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9380 #define VF_MBX_CPM_ARQT1 0x0000F090 /* Reset Source: CORER */
9381 #define VF_MBX_CPM_ARQT1_ARQT_S 0
9382 #define VF_MBX_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9383 #define VF_MBX_CPM_ATQBAH1 0x0000F010 /* Reset Source: CORER */
9384 #define VF_MBX_CPM_ATQBAH1_ATQBAH_S 0
9385 #define VF_MBX_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9386 #define VF_MBX_CPM_ATQBAL1 0x0000F000 /* Reset Source: CORER */
9388 #define VF_MBX_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9389 #define VF_MBX_CPM_ATQH1 0x0000F030 /* Reset Source: CORER */
9390 #define VF_MBX_CPM_ATQH1_ATQH_S 0
9391 #define VF_MBX_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9392 #define VF_MBX_CPM_ATQLEN1 0x0000F020 /* Reset Source: PFR */
9393 #define VF_MBX_CPM_ATQLEN1_ATQLEN_S 0
9394 #define VF_MBX_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9403 #define VF_MBX_CPM_ATQT1 0x0000F040 /* Reset Source: CORER */
9404 #define VF_MBX_CPM_ATQT1_ATQT_S 0
9405 #define VF_MBX_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9406 #define VF_MBX_HLP_ARQBAH1 0x00020060 /* Reset Source: CORER */
9407 #define VF_MBX_HLP_ARQBAH1_ARQBAH_S 0
9408 #define VF_MBX_HLP_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9409 #define VF_MBX_HLP_ARQBAL1 0x00020050 /* Reset Source: CORER */
9410 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_S 0
9411 #define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9413 #define VF_MBX_HLP_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9414 #define VF_MBX_HLP_ARQH1 0x00020080 /* Reset Source: CORER */
9415 #define VF_MBX_HLP_ARQH1_ARQH_S 0
9416 #define VF_MBX_HLP_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9417 #define VF_MBX_HLP_ARQLEN1 0x00020070 /* Reset Source: PFR */
9418 #define VF_MBX_HLP_ARQLEN1_ARQLEN_S 0
9419 #define VF_MBX_HLP_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9428 #define VF_MBX_HLP_ARQT1 0x00020090 /* Reset Source: CORER */
9429 #define VF_MBX_HLP_ARQT1_ARQT_S 0
9430 #define VF_MBX_HLP_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9431 #define VF_MBX_HLP_ATQBAH1 0x00020010 /* Reset Source: CORER */
9432 #define VF_MBX_HLP_ATQBAH1_ATQBAH_S 0
9433 #define VF_MBX_HLP_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9434 #define VF_MBX_HLP_ATQBAL1 0x00020000 /* Reset Source: CORER */
9436 #define VF_MBX_HLP_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9437 #define VF_MBX_HLP_ATQH1 0x00020030 /* Reset Source: CORER */
9438 #define VF_MBX_HLP_ATQH1_ATQH_S 0
9439 #define VF_MBX_HLP_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9440 #define VF_MBX_HLP_ATQLEN1 0x00020020 /* Reset Source: PFR */
9441 #define VF_MBX_HLP_ATQLEN1_ATQLEN_S 0
9442 #define VF_MBX_HLP_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9451 #define VF_MBX_HLP_ATQT1 0x00020040 /* Reset Source: CORER */
9452 #define VF_MBX_HLP_ATQT1_ATQT_S 0
9453 #define VF_MBX_HLP_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9454 #define VF_MBX_PSM_ARQBAH1 0x00021060 /* Reset Source: CORER */
9455 #define VF_MBX_PSM_ARQBAH1_ARQBAH_S 0
9456 #define VF_MBX_PSM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9457 #define VF_MBX_PSM_ARQBAL1 0x00021050 /* Reset Source: CORER */
9458 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_S 0
9459 #define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9461 #define VF_MBX_PSM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9462 #define VF_MBX_PSM_ARQH1 0x00021080 /* Reset Source: CORER */
9463 #define VF_MBX_PSM_ARQH1_ARQH_S 0
9464 #define VF_MBX_PSM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9465 #define VF_MBX_PSM_ARQLEN1 0x00021070 /* Reset Source: PFR */
9466 #define VF_MBX_PSM_ARQLEN1_ARQLEN_S 0
9467 #define VF_MBX_PSM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9476 #define VF_MBX_PSM_ARQT1 0x00021090 /* Reset Source: CORER */
9477 #define VF_MBX_PSM_ARQT1_ARQT_S 0
9478 #define VF_MBX_PSM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9479 #define VF_MBX_PSM_ATQBAH1 0x00021010 /* Reset Source: CORER */
9480 #define VF_MBX_PSM_ATQBAH1_ATQBAH_S 0
9481 #define VF_MBX_PSM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9482 #define VF_MBX_PSM_ATQBAL1 0x00021000 /* Reset Source: CORER */
9484 #define VF_MBX_PSM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9485 #define VF_MBX_PSM_ATQH1 0x00021030 /* Reset Source: CORER */
9486 #define VF_MBX_PSM_ATQH1_ATQH_S 0
9487 #define VF_MBX_PSM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9488 #define VF_MBX_PSM_ATQLEN1 0x00021020 /* Reset Source: PFR */
9489 #define VF_MBX_PSM_ATQLEN1_ATQLEN_S 0
9490 #define VF_MBX_PSM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9499 #define VF_MBX_PSM_ATQT1 0x00021040 /* Reset Source: CORER */
9500 #define VF_MBX_PSM_ATQT1_ATQT_S 0
9501 #define VF_MBX_PSM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9502 #define VF_SB_CPM_ARQBAH1 0x0000F160 /* Reset Source: CORER */
9503 #define VF_SB_CPM_ARQBAH1_ARQBAH_S 0
9504 #define VF_SB_CPM_ARQBAH1_ARQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9505 #define VF_SB_CPM_ARQBAL1 0x0000F150 /* Reset Source: CORER */
9506 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_S 0
9507 #define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_M MAKEMASK(0x3F, 0)
9509 #define VF_SB_CPM_ARQBAL1_ARQBAL_M MAKEMASK(0x3FFFFFF, 6)
9510 #define VF_SB_CPM_ARQH1 0x0000F180 /* Reset Source: CORER */
9511 #define VF_SB_CPM_ARQH1_ARQH_S 0
9512 #define VF_SB_CPM_ARQH1_ARQH_M MAKEMASK(0x3FF, 0)
9513 #define VF_SB_CPM_ARQLEN1 0x0000F170 /* Reset Source: PFR */
9514 #define VF_SB_CPM_ARQLEN1_ARQLEN_S 0
9515 #define VF_SB_CPM_ARQLEN1_ARQLEN_M MAKEMASK(0x3FF, 0)
9524 #define VF_SB_CPM_ARQT1 0x0000F190 /* Reset Source: CORER */
9525 #define VF_SB_CPM_ARQT1_ARQT_S 0
9526 #define VF_SB_CPM_ARQT1_ARQT_M MAKEMASK(0x3FF, 0)
9527 #define VF_SB_CPM_ATQBAH1 0x0000F110 /* Reset Source: CORER */
9528 #define VF_SB_CPM_ATQBAH1_ATQBAH_S 0
9529 #define VF_SB_CPM_ATQBAH1_ATQBAH_M MAKEMASK(0xFFFFFFFF, 0)
9530 #define VF_SB_CPM_ATQBAL1 0x0000F100 /* Reset Source: CORER */
9532 #define VF_SB_CPM_ATQBAL1_ATQBAL_M MAKEMASK(0x3FFFFFF, 6)
9533 #define VF_SB_CPM_ATQH1 0x0000F130 /* Reset Source: CORER */
9534 #define VF_SB_CPM_ATQH1_ATQH_S 0
9535 #define VF_SB_CPM_ATQH1_ATQH_M MAKEMASK(0x3FF, 0)
9536 #define VF_SB_CPM_ATQLEN1 0x0000F120 /* Reset Source: PFR */
9537 #define VF_SB_CPM_ATQLEN1_ATQLEN_S 0
9538 #define VF_SB_CPM_ATQLEN1_ATQLEN_M MAKEMASK(0x3FF, 0)
9547 #define VF_SB_CPM_ATQT1 0x0000F140 /* Reset Source: CORER */
9548 #define VF_SB_CPM_ATQT1_ATQT_S 0
9549 #define VF_SB_CPM_ATQT1_ATQT_M MAKEMASK(0x3FF, 0)
9550 #define VFINT_DYN_CTL(_i) (0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9552 #define VFINT_DYN_CTL_INTENA_S 0
9553 #define VFINT_DYN_CTL_INTENA_M BIT(0)
9559 #define VFINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, 3)
9561 #define VFINT_DYN_CTL_INTERVAL_M MAKEMASK(0xFFF, 5)
9565 #define VFINT_DYN_CTL_SW_ITR_INDX_M MAKEMASK(0x3, 25)
9570 #define VFINT_ITR_0(_i) (0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9572 #define VFINT_ITR_0_INTERVAL_S 0
9573 #define VFINT_ITR_0_INTERVAL_M MAKEMASK(0xFFF, 0)
9574 #define VFINT_ITR_1(_i) (0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9576 #define VFINT_ITR_1_INTERVAL_S 0
9577 #define VFINT_ITR_1_INTERVAL_M MAKEMASK(0xFFF, 0)
9578 #define VFINT_ITR_2(_i) (0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: CORER */
9580 #define VFINT_ITR_2_INTERVAL_S 0
9581 #define VFINT_ITR_2_INTERVAL_M MAKEMASK(0xFFF, 0)
9582 #define VFQRX_TAIL(_QRX) (0x0002E000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9584 #define VFQRX_TAIL_TAIL_S 0
9585 #define VFQRX_TAIL_TAIL_M MAKEMASK(0x1FFF, 0)
9586 #define VFQTX_COMM_DBELL(_DBQM) (0x00030000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9588 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_S 0
9589 #define VFQTX_COMM_DBELL_QTX_COMM_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9590 #define VFQTX_COMM_DBLQ_DBELL(_DBLQ) (0x00022000 + ((_DBLQ) * 4)) /* _i=0...3 */ /* Reset Source: CORER */
9592 #define VFQTX_COMM_DBLQ_DBELL_TAIL_S 0
9593 #define VFQTX_COMM_DBLQ_DBELL_TAIL_M MAKEMASK(0x1FFF, 0)
9594 #define MSIX_TMSG1(_i) (0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */
9596 #define MSIX_TMSG1_MSIXTMSG_S 0
9597 #define MSIX_TMSG1_MSIXTMSG_M MAKEMASK(0xFFFFFFFF, 0)
9598 #define VFPE_AEQALLOC1 0x0000A400 /* Reset Source: VFR */
9599 #define VFPE_AEQALLOC1_AECOUNT_S 0
9600 #define VFPE_AEQALLOC1_AECOUNT_M MAKEMASK(0xFFFFFFFF, 0)
9601 #define VFPE_CCQPHIGH1 0x00009800 /* Reset Source: VFR */
9602 #define VFPE_CCQPHIGH1_PECCQPHIGH_S 0
9603 #define VFPE_CCQPHIGH1_PECCQPHIGH_M MAKEMASK(0xFFFFFFFF, 0)
9604 #define VFPE_CCQPLOW1 0x0000AC00 /* Reset Source: VFR */
9605 #define VFPE_CCQPLOW1_PECCQPLOW_S 0
9606 #define VFPE_CCQPLOW1_PECCQPLOW_M MAKEMASK(0xFFFFFFFF, 0)
9607 #define VFPE_CCQPSTATUS1 0x0000B800 /* Reset Source: VFR */
9608 #define VFPE_CCQPSTATUS1_CCQP_DONE_S 0
9609 #define VFPE_CCQPSTATUS1_CCQP_DONE_M BIT(0)
9611 #define VFPE_CCQPSTATUS1_HMC_PROFILE_M MAKEMASK(0x7, 4)
9613 #define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M MAKEMASK(0x3F, 16)
9616 #define VFPE_CQACK1 0x0000B000 /* Reset Source: VFR */
9617 #define VFPE_CQACK1_PECQID_S 0
9618 #define VFPE_CQACK1_PECQID_M MAKEMASK(0x7FFFF, 0)
9619 #define VFPE_CQARM1 0x0000B400 /* Reset Source: VFR */
9620 #define VFPE_CQARM1_PECQID_S 0
9621 #define VFPE_CQARM1_PECQID_M MAKEMASK(0x7FFFF, 0)
9622 #define VFPE_CQPDB1 0x0000BC00 /* Reset Source: VFR */
9623 #define VFPE_CQPDB1_WQHEAD_S 0
9624 #define VFPE_CQPDB1_WQHEAD_M MAKEMASK(0x7FF, 0)
9625 #define VFPE_CQPERRCODES1 0x00009C00 /* Reset Source: VFR */
9626 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S 0
9627 #define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M MAKEMASK(0xFFFF, 0)
9629 #define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M MAKEMASK(0xFFFF, 16)
9630 #define VFPE_CQPTAIL1 0x0000A000 /* Reset Source: VFR */
9631 #define VFPE_CQPTAIL1_WQTAIL_S 0
9632 #define VFPE_CQPTAIL1_WQTAIL_M MAKEMASK(0x7FF, 0)
9635 #define VFPE_IPCONFIG01 0x00008C00 /* Reset Source: VFR */
9636 #define VFPE_IPCONFIG01_PEIPID_S 0
9637 #define VFPE_IPCONFIG01_PEIPID_M MAKEMASK(0xFFFF, 0)
9642 #define E800_VFPE_MRTEIDXMASK1(_VF) (0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */
9644 #define E800_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S 0
9645 #define E800_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M MAKEMASK(0x1F, 0)
9646 #define E800_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset Source: VFR */
9647 #define E800_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0
9648 #define E800_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)
9649 #define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */
9650 #define VFPE_TCPNOWTIMER1_TCP_NOW_S 0
9651 #define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
9652 #define VFPE_WQEALLOC1 0x0000C000 /* Reset Source: VFR */
9653 #define VFPE_WQEALLOC1_PEQPID_S 0
9654 #define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)
9656 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
9657 #define E830_GL_QRX_CONTEXT_CTL 0x00296640 /* Reset Source: CORER */
9658 #define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_S 0
9659 #define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_M MAKEMASK(0xFFF, 0)
9661 #define E830_GL_QRX_CONTEXT_CTL_CMD_M MAKEMASK(0x7, 16)
9664 #define E830_GL_QRX_CONTEXT_DATA(_i) (0x00296620 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9666 #define E830_GL_QRX_CONTEXT_DATA_DATA_S 0
9667 #define E830_GL_QRX_CONTEXT_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
9668 #define E830_GL_QRX_CONTEXT_STAT 0x00296644 /* Reset Source: CORER */
9669 #define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_S 0
9670 #define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_M BIT(0)
9671 #define E830_GL_RCB_INTERNAL(_i) (0x00122600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
9673 #define E830_GL_RCB_INTERNAL_INTERNAL_S 0
9674 #define E830_GL_RCB_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0)
9675 #define E830_GL_RLAN_INTERNAL(_i) (0x00296700 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
9677 #define E830_GL_RLAN_INTERNAL_INTERNAL_S 0
9678 #define E830_GL_RLAN_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0)
9679 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS 0x002D30F0 /* Reset Source: CORER */
9680 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_DBLQ_S 0
9681 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_DBLQ_M MAKEMASK(0xFF, 0)
9683 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_FDBL_M MAKEMASK(0xFF, 8)
9685 #define E830_GLPQMDBL_PQMDBL_IN_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 16)
9686 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS 0x002D30F4 /* Reset Source: CORER */
9687 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_DBLQ_S 0
9688 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_DBLQ_M MAKEMASK(0x3F, 0)
9690 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_FDBL_M MAKEMASK(0x3F, 6)
9692 #define E830_GLPQMDBL_PQMDBL_IN_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 12)
9693 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS 0x002D30F8 /* Reset Source: CORER */
9694 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_S 0
9695 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_M MAKEMASK(0xFF, 0)
9697 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 8)
9698 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS 0x002D30FC /* Reset Source: CORER */
9699 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_S 0
9700 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_M MAKEMASK(0x3F, 0)
9702 #define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 6)
9703 #define E830_GLQTX_TXTIME_DBELL_LSB(_DBQM) (0x002E0000 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */
9705 #define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_S 0
9706 #define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9707 #define E830_GLQTX_TXTIME_DBELL_MSB(_DBQM) (0x002E0004 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */
9709 #define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_S 0
9710 #define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
9712 #define E830_GLTCLAN_CQ_CNTX2_SRC_VSI_M MAKEMASK(0x3FF, 18)
9713 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS 0x002D320C /* Reset Source: CORER */
9714 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_S 0
9715 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_M MAKEMASK(0xFF, 0)
9717 #define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_M MAKEMASK(0xFF, 8)
9718 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS 0x002D3210 /* Reset Source: CORER */
9719 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_S 0
9720 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_M MAKEMASK(0x3F, 0)
9722 #define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_M MAKEMASK(0x3F, 6)
9723 #define E830_GLTXTIME_FETCH_PROFILE(_i, _j) (0x002D3500 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...15 */ /* Reset Source: CORER */
9725 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_S 0
9726 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M MAKEMASK(0x1FF, 0)
9728 #define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_M MAKEMASK(0x7F, 9)
9729 #define E830_GLTXTIME_OUTST_REQ_CNTL 0x002D3214 /* Reset Source: CORER */
9730 #define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_S 0
9731 #define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_M MAKEMASK(0x3FF, 0)
9733 #define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_M MAKEMASK(0x3FF, 10)
9734 #define E830_GLTXTIME_QTX_CNTX_CTL 0x002D3204 /* Reset Source: CORER */
9735 #define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_S 0
9736 #define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x7FF, 0)
9738 #define E830_GLTXTIME_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16)
9741 #define E830_GLTXTIME_QTX_CNTX_DATA(_i) (0x002D3104 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */
9743 #define E830_GLTXTIME_QTX_CNTX_DATA_DATA_S 0
9744 #define E830_GLTXTIME_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0)
9745 #define E830_GLTXTIME_QTX_CNTX_STAT 0x002D3208 /* Reset Source: CORER */
9746 #define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_S 0
9747 #define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)
9748 #define E830_GLTXTIME_TS_CFG 0x002D3100 /* Reset Source: CORER */
9749 #define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_S 0
9750 #define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_M BIT(0)
9752 #define E830_GLTXTIME_TS_CFG_STORAGE_MODE_M MAKEMASK(0x7, 2)
9754 #define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_M MAKEMASK(0x1FFF, 5)
9755 #define E830_MBX_PF_DEC_ERR 0x00234100 /* Reset Source: CORER */
9756 #define E830_MBX_PF_DEC_ERR_DEC_ERR_S 0
9757 #define E830_MBX_PF_DEC_ERR_DEC_ERR_M BIT(0)
9758 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH 0x00234000 /* Reset Source: CORER */
9759 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_S 0
9760 #define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_M MAKEMASK(0x3FF, 0)
9761 #define E830_MBX_VF_DEC_TRIG(_VF) (0x00233800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9763 #define E830_MBX_VF_DEC_TRIG_DEC_S 0
9764 #define E830_MBX_VF_DEC_TRIG_DEC_M MAKEMASK(0x3FF, 0)
9765 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(_VF) (0x00233000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9767 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_S 0
9768 #define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_M MAKEMASK(0x3FF, 0)
9769 #define E830_GLRCB_AG_ARBITER_CONFIG 0x00122500 /* Reset Source: CORER */
9770 #define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_S 0
9771 #define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0xFFFFF, 0)
9772 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG 0x00122518 /* Reset Source: CORER */
9773 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_S 0
9774 #define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0x7F, 0)
9777 #define E830_GLRCB_AG_DCB_NODE_CONFIG(_i) (0x00122510 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
9779 #define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_S 0
9780 #define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_M MAKEMASK(0xF, 0)
9781 #define E830_GLRCB_AG_DCB_NODE_STATE(_i) (0x00122508 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
9783 #define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_S 0
9784 #define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_M MAKEMASK(0xFF, 0)
9785 #define E830_GLRCB_AG_NODE_CONFIG(_i) (0x001224E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9787 #define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_S 0
9788 #define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_M MAKEMASK(0x7F, 0)
9789 #define E830_GLRCB_AG_NODE_STATE(_i) (0x001224C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9791 #define E830_GLRCB_AG_NODE_STATE_CREDITS_S 0
9792 #define E830_GLRCB_AG_NODE_STATE_CREDITS_M MAKEMASK(0xFFFFF, 0)
9793 #define E830_PRT_AG_PORT_FC_MAP 0x00122520 /* Reset Source: CORER */
9794 #define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_S 0
9795 #define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_M MAKEMASK(0xFF, 0)
9796 #define E830_GL_FW_LOGS_CTL 0x000827F8 /* Reset Source: POR */
9797 #define E830_GL_FW_LOGS_CTL_PAGE_SELECT_S 0
9798 #define E830_GL_FW_LOGS_CTL_PAGE_SELECT_M MAKEMASK(0x3FF, 0)
9799 #define E830_GL_FW_LOGS_STS 0x000827FC /* Reset Source: POR */
9800 #define E830_GL_FW_LOGS_STS_MAX_PAGE_S 0
9801 #define E830_GL_FW_LOGS_STS_MAX_PAGE_M MAKEMASK(0x3FF, 0)
9804 #define E830_GL_RTCTL 0x000827F0 /* Reset Source: POR */
9805 #define E830_GL_RTCTL_RTCTL_S 0
9806 #define E830_GL_RTCTL_RTCTL_M MAKEMASK(0xFFFFFFFF, 0)
9807 #define E830_GL_RTCTM 0x000827F4 /* Reset Source: POR */
9808 #define E830_GL_RTCTM_RTCTM_S 0
9809 #define E830_GL_RTCTM_RTCTM_M MAKEMASK(0xFFFF, 0)
9812 #define E830_GLPE_TSCD_NUM_PQS 0x0051E2FC /* Reset Source: CORER */
9813 #define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_S 0
9814 #define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_M MAKEMASK(0xFFFFFFFF, 0)
9815 #define E830_GLTPB_100G_RPB_FC_THRESH2 0x0009972C /* Reset Source: CORER */
9816 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_S 0
9817 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_M MAKEMASK(0xFFFF, 0)
9819 #define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_M MAKEMASK(0xFFFF, 16)
9820 #define E830_GLTPB_100G_RPB_FC_THRESH3 0x00099730 /* Reset Source: CORER */
9821 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_S 0
9822 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_M MAKEMASK(0xFFFF, 0)
9824 #define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_M MAKEMASK(0xFFFF, 16)
9825 #define E830_PORT_TIMER_SEL(_i) (0x00088BE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9827 #define E830_PORT_TIMER_SEL_TIMER_SEL_S 0
9828 #define E830_PORT_TIMER_SEL_TIMER_SEL_M BIT(0)
9831 #define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT 0x001E2280 /* Reset Source: GLOBR */
9832 #define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_S 0
9833 #define E830_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_PRTMAC_SHORT_PAC_DROP_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0)
9834 #define E830_PRTTSYN_TXTIME_H(_i) (0x001E5800 + ((_i) * 32)) /* _i=0...63 */ /* Reset Source: GLOBR */
9836 #define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_S 0
9837 #define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_M MAKEMASK(0xFF, 0)
9838 #define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 32)) /* _i=0...63 */ /* Reset Source: GLOBR */
9840 #define E830_PRTTSYN_TXTIME_L_TX_VALID_S 0
9841 #define E830_PRTTSYN_TXTIME_L_TX_VALID_M BIT(0)
9843 #define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_M MAKEMASK(0x7FFFFFFF, 1)
9844 #define E830_GL_MDCK_TDAT_TCLAN_TSYN 0x000FD200 /* Reset Source: CORER */
9845 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_FROM_Q_NOT_ALLOWED_S 0
9846 #define E830_GL_MDCK_TDAT_TCLAN_TSYN_PF_TSYN_PKT_FROM_Q_NOT_ALLOWED_M BIT(0)
9849 #define E830_GL_MDET_RX_FIFO 0x00296840 /* Reset Source: CORER */
9850 #define E830_GL_MDET_RX_FIFO_FUNC_NUM_S 0
9851 #define E830_GL_MDET_RX_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
9853 #define E830_GL_MDET_RX_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
9855 #define E830_GL_MDET_RX_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
9857 #define E830_GL_MDET_RX_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
9863 #define E830_GL_MDET_RX_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
9864 #define E830_GL_MDET_RX_PF_CNT(_i) (0x00296800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9866 #define E830_GL_MDET_RX_PF_CNT_CNT_S 0
9867 #define E830_GL_MDET_RX_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
9868 #define E830_GL_MDET_RX_VF(_i) (0x00296820 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9870 #define E830_GL_MDET_RX_VF_VF_MAL_EVENT_S 0
9871 #define E830_GL_MDET_RX_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
9872 #define E830_GL_MDET_TX_PQM_FIFO 0x002D4B00 /* Reset Source: CORER */
9873 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_S 0
9874 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
9876 #define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
9878 #define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
9880 #define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
9886 #define E830_GL_MDET_TX_PQM_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
9887 #define E830_GL_MDET_TX_PQM_PF_CNT(_i) (0x002D4AC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9889 #define E830_GL_MDET_TX_PQM_PF_CNT_CNT_S 0
9890 #define E830_GL_MDET_TX_PQM_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
9891 #define E830_GL_MDET_TX_PQM_VF(_i) (0x002D4AE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9893 #define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_S 0
9894 #define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
9895 #define E830_GL_MDET_TX_TCLAN_FIFO 0x000FCFD0 /* Reset Source: CORER */
9896 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_S 0
9897 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
9899 #define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
9901 #define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
9903 #define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
9909 #define E830_GL_MDET_TX_TCLAN_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
9910 #define E830_GL_MDET_TX_TCLAN_PF_CNT(_i) (0x000FCF90 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9912 #define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_S 0
9913 #define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
9914 #define E830_GL_MDET_TX_TCLAN_VF(_i) (0x000FCFB0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9916 #define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_S 0
9917 #define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
9918 #define E830_GL_MDET_TX_TDPU_FIFO 0x00049D80 /* Reset Source: CORER */
9919 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_S 0
9920 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
9922 #define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
9924 #define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
9926 #define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
9932 #define E830_GL_MDET_TX_TDPU_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
9933 #define E830_GL_MDET_TX_TDPU_PF_CNT(_i) (0x00049D40 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9935 #define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_S 0
9936 #define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
9937 #define E830_GL_MDET_TX_TDPU_VF(_i) (0x00049D60 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
9939 #define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_S 0
9940 #define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
9941 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH(_i) (0x00083400 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
9943 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH_GL_MNG_ECDSA_PUBKEY_S 0
9944 #define E830_GL_MNG_ECDSA_PUBKEY_HIGH_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0)
9945 #define E830_GL_MNG_ECDSA_PUBKEY_LOW(_i) (0x00083300 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */
9947 #define E830_GL_MNG_ECDSA_PUBKEY_LOW_GL_MNG_ECDSA_PUBKEY_S 0
9948 #define E830_GL_MNG_ECDSA_PUBKEY_LOW_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0)
9949 #define E830_GL_PPRS_RX_SIZE_CTRL_0(_i) (0x00084900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
9952 #define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
9953 #define E830_GL_PPRS_RX_SIZE_CTRL_1(_i) (0x00085900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
9956 #define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
9957 #define E830_GL_PPRS_RX_SIZE_CTRL_2(_i) (0x00086900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
9960 #define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
9961 #define E830_GL_PPRS_RX_SIZE_CTRL_3(_i) (0x00087900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
9964 #define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
9965 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP 0x00200740 /* Reset Source: CORER */
9966 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0
9967 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0)
9969 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8)
9971 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16)
9973 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24)
9974 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00200744 /* Reset Source: CORER */
9975 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0
9976 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0)
9978 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8)
9980 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16)
9982 #define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24)
9983 #define E830_GL_RPRS_PROT_ID_MAP(_i) (0x00200800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
9985 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_S 0
9986 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0)
9988 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8)
9990 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16)
9992 #define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24)
9993 #define E830_GL_RPRS_PROT_ID_MAP_PRFL(_i) (0x00201000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
9995 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0
9996 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0)
9998 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2)
10000 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4)
10002 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6)
10004 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8)
10006 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10)
10008 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12)
10010 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14)
10012 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16)
10014 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18)
10016 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20)
10018 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22)
10020 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24)
10022 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26)
10024 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28)
10026 #define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30)
10027 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL 0x00200748 /* Reset Source: CORER */
10028 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0
10029 #define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0)
10040 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP 0x00203A04 /* Reset Source: CORER */
10041 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0
10042 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0)
10044 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8)
10046 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16)
10048 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24)
10049 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00203A08 /* Reset Source: CORER */
10050 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0
10051 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0)
10053 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8)
10055 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16)
10057 #define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24)
10058 #define E830_GL_TPRS_PROT_ID_MAP(_i) (0x00202200 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
10060 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_S 0
10061 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0)
10063 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8)
10065 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16)
10067 #define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24)
10068 #define E830_GL_TPRS_PROT_ID_MAP_PRFL(_i) (0x00202A00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
10070 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0
10071 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0)
10073 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2)
10075 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4)
10077 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6)
10079 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8)
10081 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10)
10083 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12)
10085 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14)
10087 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16)
10089 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18)
10091 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20)
10093 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22)
10095 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24)
10097 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26)
10099 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28)
10101 #define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30)
10102 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL 0x00203A00 /* Reset Source: CORER */
10103 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0
10104 #define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0)
10115 #define E830_PRT_TDPU_TX_SIZE_CTRL 0x00049D20 /* Reset Source: CORER */
10117 #define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
10118 #define E830_PRT_TPB_RX_LB_SIZE_CTRL 0x00099740 /* Reset Source: CORER */
10120 #define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)
10121 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE(_DBQM) (0x04000008 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
10123 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_S 0
10124 #define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
10125 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE(_DBQM) (0x0400000C + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */
10127 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_S 0
10128 #define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
10135 #define E830_GL_HIBA(_i) (0x00081000 + ((_i) * 4)) /* _i=0...1023 */ /* Reset Source: EMPR */
10137 #define E830_GL_HIBA_GL_HIBA_S 0
10138 #define E830_GL_HIBA_GL_HIBA_M MAKEMASK(0xFFFFFFFF, 0)
10139 #define E830_GL_HICR 0x00082040 /* Reset Source: EMPR */
10146 #define E830_GL_HICR_EN 0x00082044 /* Reset Source: EMPR */
10147 #define E830_GL_HICR_EN_EN_S 0
10148 #define E830_GL_HICR_EN_EN_M BIT(0)
10149 #define E830_GL_HIDA(_i) (0x00082000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: EMPR */
10151 #define E830_GL_HIDA_GL_HIDB_S 0
10152 #define E830_GL_HIDA_GL_HIDB_M MAKEMASK(0xFFFFFFFF, 0)
10154 #define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_M MAKEMASK(0xF, 18)
10156 #define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_M MAKEMASK(0xF, 18)
10158 #define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_M MAKEMASK(0xF, 18)
10160 #define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_M MAKEMASK(0xF, 18)
10162 #define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_M MAKEMASK(0xF, 18)
10164 #define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_M MAKEMASK(0xF, 18)
10165 #define E830_GLFLXP_RXDID_FLX_WRD_6(_i) (0x0045CE00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
10167 #define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_S 0
10168 #define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_M MAKEMASK(0xFF, 0)
10170 #define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
10174 #define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_M MAKEMASK(0x7, 19)
10176 #define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_M MAKEMASK(0x3, 30)
10177 #define E830_GLFLXP_RXDID_FLX_WRD_7(_i) (0x0045CF00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
10179 #define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_S 0
10180 #define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_M MAKEMASK(0xFF, 0)
10182 #define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
10186 #define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_M MAKEMASK(0x7, 19)
10188 #define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_M MAKEMASK(0x3, 30)
10189 #define E830_GLFLXP_RXDID_FLX_WRD_8(_i) (0x0045D500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */
10191 #define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_S 0
10192 #define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_M MAKEMASK(0xFF, 0)
10194 #define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)
10198 #define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_M MAKEMASK(0x7, 19)
10200 #define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_M MAKEMASK(0x3, 30)
10201 #define E830_GL_FW_LOGS(_i) (0x00082800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: POR */
10203 #define E830_GL_FW_LOGS_GL_FW_LOGS_S 0
10204 #define E830_GL_FW_LOGS_GL_FW_LOGS_M MAKEMASK(0xFFFFFFFF, 0)
10206 #define E830_GL_FWSTS_FWABS_M MAKEMASK(0x3, 10)
10210 #define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_M MAKEMASK(0x3, 19)
10213 #define E830_GLPCI_PLATFORM_INFO 0x0009DDC4 /* Reset Source: POR */
10214 #define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_S 0
10215 #define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_M MAKEMASK(0xFF, 0)
10222 #define E830_GL_TPB_LOCAL_TOPO 0x000996F4 /* Reset Source: CORER */
10223 #define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_S 0
10224 #define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_M BIT(0)
10226 #define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_M MAKEMASK(0x3, 1)
10227 #define E830_GL_TPB_PM_RESET 0x000996F0 /* Reset Source: CORER */
10228 #define E830_GL_TPB_PM_RESET_MAC_PM_RESET_S 0
10229 #define E830_GL_TPB_PM_RESET_MAC_PM_RESET_M BIT(0)
10232 #define E830_GLTPB_100G_MAC_FC_THRESH1 0x00099724 /* Reset Source: CORER */
10233 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_S 0
10234 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0)
10236 #define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16)
10237 #define E830_GLTPB_100G_RPB_FC_THRESH0 0x0009963C /* Reset Source: CORER */
10238 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_S 0
10239 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)
10241 #define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)
10242 #define E830_GLTPB_100G_RPB_FC_THRESH1 0x00099728 /* Reset Source: CORER */
10243 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_S 0
10244 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0)
10246 #define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16)
10248 #define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_M MAKEMASK(0xFFFF, 12)
10263 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA 0x001E3854 /* Reset Source: GLOBR */
10264 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0
10265 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10267 #define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10268 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH 0x001E3864 /* Reset Source: GLOBR */
10269 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0
10270 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10272 #define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10273 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA 0x001E3858 /* Reset Source: GLOBR */
10274 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0
10275 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10277 #define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10278 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH 0x001E3868 /* Reset Source: GLOBR */
10279 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0
10280 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10282 #define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10283 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA 0x001E385C /* Reset Source: GLOBR */
10284 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0
10285 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10287 #define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10288 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH 0x001E386C /* Reset Source: GLOBR */
10289 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0
10290 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10292 #define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10293 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA 0x001E3860 /* Reset Source: GLOBR */
10294 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0
10295 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10297 #define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10298 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH 0x001E3870 /* Reset Source: GLOBR */
10299 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0
10300 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10302 #define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10303 #define E830_PRTMAC_200G_COMMAND_CONFIG 0x001E3808 /* Reset Source: GLOBR */
10304 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_S 0
10305 #define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_M BIT(0)
10352 #define E830_PRTMAC_200G_CRC_INV_M 0x001E384C /* Reset Source: GLOBR */
10353 #define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_S 0
10354 #define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0)
10355 #define E830_PRTMAC_200G_FRM_LENGTH 0x001E3814 /* Reset Source: GLOBR */
10356 #define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_S 0
10357 #define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0)
10359 #define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16)
10360 #define E830_PRTMAC_200G_HASHTABLE_LOAD 0x001E382C /* Reset Source: GLOBR */
10361 #define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_S 0
10362 #define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_M MAKEMASK(0x3F, 0)
10365 #define E830_PRTMAC_200G_MAC_ADDR_0 0x001E380C /* Reset Source: GLOBR */
10366 #define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_S 0
10367 #define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0)
10368 #define E830_PRTMAC_200G_MAC_ADDR_1 0x001E3810 /* Reset Source: GLOBR */
10369 #define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_S 0
10370 #define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0)
10371 #define E830_PRTMAC_200G_MDIO_CFG_STATUS 0x001E3830 /* Reset Source: GLOBR */
10372 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_S 0
10373 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0)
10377 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2)
10383 #define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7)
10384 #define E830_PRTMAC_200G_MDIO_COMMAND 0x001E3834 /* Reset Source: GLOBR */
10385 #define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_S 0
10386 #define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFF, 0)
10388 #define E830_PRTMAC_200G_MDIO_COMMAND_RESERVED_2_M MAKEMASK(0x7FFF, 16)
10391 #define E830_PRTMAC_200G_MDIO_DATA 0x001E3838 /* Reset Source: GLOBR */
10392 #define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_S 0
10393 #define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFF, 0)
10395 #define E830_PRTMAC_200G_MDIO_DATA_RESERVED_2_M MAKEMASK(0x7FFF, 16)
10398 #define E830_PRTMAC_200G_MDIO_REGADDR 0x001E383C /* Reset Source: GLOBR */
10399 #define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_S 0
10400 #define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0)
10401 #define E830_PRTMAC_200G_REVISION 0x001E3800 /* Reset Source: GLOBR */
10402 #define E830_PRTMAC_200G_REVISION_CORE_REVISION_S 0
10403 #define E830_PRTMAC_200G_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0)
10405 #define E830_PRTMAC_200G_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8)
10407 #define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16)
10408 #define E830_PRTMAC_200G_RX_PAUSE_STATUS 0x001E3874 /* Reset Source: GLOBR */
10409 #define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0
10410 #define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0)
10411 #define E830_PRTMAC_200G_SCRATCH 0x001E3804 /* Reset Source: GLOBR */
10412 #define E830_PRTMAC_200G_SCRATCH_SCRATCH_S 0
10413 #define E830_PRTMAC_200G_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0)
10414 #define E830_PRTMAC_200G_STATUS 0x001E3840 /* Reset Source: GLOBR */
10415 #define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_S 0
10416 #define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_M BIT(0)
10434 #define E830_PRTMAC_200G_STATUS_RESERVED2_M MAKEMASK(0x7FFFFF, 9)
10435 #define E830_PRTMAC_200G_TS_TIMESTAMP 0x001E387C /* Reset Source: GLOBR */
10436 #define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_S 0
10437 #define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0)
10438 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS 0x001E3820 /* Reset Source: GLOBR */
10439 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0
10440 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0)
10442 #define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16)
10443 #define E830_PRTMAC_200G_TX_IPG_LENGTH 0x001E3844 /* Reset Source: GLOBR */
10444 #define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_S 0
10445 #define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x7F, 0)
10447 #define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_M MAKEMASK(0x1FFF, 19)
10448 #define E830_PRTMAC_200G_XIF_MODE 0x001E3880 /* Reset Source: GLOBR */
10449 #define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_S 0
10450 #define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_M MAKEMASK(0x1F, 0)
10459 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0 0x001E3C00 /* Reset Source: GLOBR */
10460 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0_APPROVED_SW_ADDR_MAC_100G_0_S 0
10461 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_0_APPROVED_SW_ADDR_MAC_100G_0_M MAKEMASK(0x3F, 0)
10462 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1 0x001E3C20 /* Reset Source: GLOBR */
10463 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1_APPROVED_SW_ADDR_MAC_100G_1_S 0
10464 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_1_APPROVED_SW_ADDR_MAC_100G_1_M MAKEMASK(0x3F, 0)
10465 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2 0x001E3C40 /* Reset Source: GLOBR */
10466 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2_APPROVED_SW_ADDR_MAC_100G_2_S 0
10467 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_2_APPROVED_SW_ADDR_MAC_100G_2_M MAKEMASK(0x3F, 0)
10468 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3 0x001E3C60 /* Reset Source: GLOBR */
10469 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3_APPROVED_SW_ADDR_MAC_100G_3_S 0
10470 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_100G_3_APPROVED_SW_ADDR_MAC_100G_3_M MAKEMASK(0x3F, 0)
10471 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0 0x001E3C80 /* Reset Source: GLOBR */
10472 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0_APPROVED_SW_ADDR_MAC_200G_0_S 0
10473 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_0_APPROVED_SW_ADDR_MAC_200G_0_M MAKEMASK(0xFF, 0)
10474 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1 0x001E3CA0 /* Reset Source: GLOBR */
10475 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1_APPROVED_SW_ADDR_MAC_200G_1_S 0
10476 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_1_APPROVED_SW_ADDR_MAC_200G_1_M MAKEMASK(0xFF, 0)
10477 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2 0x001E3CC0 /* Reset Source: GLOBR */
10478 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2_APPROVED_SW_ADDR_MAC_200G_2_S 0
10479 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_2_APPROVED_SW_ADDR_MAC_200G_2_M MAKEMASK(0xFF, 0)
10480 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3 0x001E3CE0 /* Reset Source: GLOBR */
10481 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3_APPROVED_SW_ADDR_MAC_200G_3_S 0
10482 #define E830_PRTMAC_APPROVED_SW_ADDR_MAC_200G_3_APPROVED_SW_ADDR_MAC_200G_3_M MAKEMASK(0xFF, 0)
10483 #define E830_PRTMAC_CF_GEN_STATUS 0x001E33C0 /* Reset Source: GLOBR */
10484 #define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_S 0
10485 #define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_M BIT(0)
10486 #define E830_PRTMAC_CL01_PAUSE_QUANTA 0x001E32A0 /* Reset Source: GLOBR */
10487 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0
10488 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10490 #define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10491 #define E830_PRTMAC_CL01_QUANTA_THRESH 0x001E3320 /* Reset Source: GLOBR */
10492 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0
10493 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10495 #define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10496 #define E830_PRTMAC_CL23_PAUSE_QUANTA 0x001E32C0 /* Reset Source: GLOBR */
10497 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0
10498 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10500 #define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10501 #define E830_PRTMAC_CL23_QUANTA_THRESH 0x001E3340 /* Reset Source: GLOBR */
10502 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0
10503 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10505 #define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10506 #define E830_PRTMAC_CL45_PAUSE_QUANTA 0x001E32E0 /* Reset Source: GLOBR */
10507 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0
10508 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10510 #define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10511 #define E830_PRTMAC_CL45_QUANTA_THRESH 0x001E3360 /* Reset Source: GLOBR */
10512 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0
10513 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10515 #define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10516 #define E830_PRTMAC_CL67_PAUSE_QUANTA 0x001E3300 /* Reset Source: GLOBR */
10517 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0
10518 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
10520 #define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)
10521 #define E830_PRTMAC_CL67_QUANTA_THRESH 0x001E3380 /* Reset Source: GLOBR */
10522 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0
10523 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)
10525 #define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)
10526 #define E830_PRTMAC_COMMAND_CONFIG 0x001E3040 /* Reset Source: GLOBR */
10527 #define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_S 0
10528 #define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_M BIT(0)
10589 #define E830_PRTMAC_CRC_INV_M 0x001E3260 /* Reset Source: GLOBR */
10590 #define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_S 0
10591 #define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0)
10592 #define E830_PRTMAC_CRC_MODE 0x001E3240 /* Reset Source: GLOBR */
10601 #define E830_PRTMAC_CSR_TIMEOUT_CFG 0x001E3D00 /* Reset Source: GLOBR */
10602 #define E830_PRTMAC_CSR_TIMEOUT_CFG_CSR_TIMEOUT_EN_S 0
10603 #define E830_PRTMAC_CSR_TIMEOUT_CFG_CSR_TIMEOUT_EN_M BIT(0)
10604 #define E830_PRTMAC_CTL_RX_CFG 0x001E2160 /* Reset Source: GLOBR */
10605 #define E830_PRTMAC_CTL_RX_CFG_SUB_CRC_STAT_S 0
10606 #define E830_PRTMAC_CTL_RX_CFG_SUB_CRC_STAT_M BIT(0)
10608 #define E830_PRTMAC_CTL_RX_CFG_FRM_DROP_FOR_STAT_MODE_M MAKEMASK(0x3, 1)
10610 #define E830_PRTMAC_CTL_RX_CFG_MAC_PAC_AFULL_TRSH_M MAKEMASK(0x7, 3)
10611 #define E830_PRTMAC_CTL_RX_PAUSE_ENABLE 0x001E2180 /* Reset Source: GLOBR */
10612 #define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S 0
10613 #define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
10614 #define E830_PRTMAC_CTL_TX_PAUSE_ENABLE 0x001E21A0 /* Reset Source: GLOBR */
10615 #define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S 0
10616 #define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
10617 #define E830_PRTMAC_FRM_LENGTH 0x001E30A0 /* Reset Source: GLOBR */
10618 #define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_S 0
10619 #define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0)
10621 #define E830_PRTMAC_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16)
10622 #define E830_PRTMAC_MAC_ADDR_0 0x001E3060 /* Reset Source: GLOBR */
10623 #define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_S 0
10624 #define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0)
10625 #define E830_PRTMAC_MAC_ADDR_1 0x001E3080 /* Reset Source: GLOBR */
10626 #define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_S 0
10627 #define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0)
10628 #define E830_PRTMAC_MDIO_CFG_STATUS 0x001E3180 /* Reset Source: GLOBR */
10629 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_S 0
10630 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0)
10634 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2)
10640 #define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7)
10641 #define E830_PRTMAC_MDIO_COMMAND 0x001E31A0 /* Reset Source: GLOBR */
10642 #define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_S 0
10643 #define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFF, 0)
10645 #define E830_PRTMAC_MDIO_COMMAND_RESERVED_2_M MAKEMASK(0x7FFF, 16)
10648 #define E830_PRTMAC_MDIO_DATA 0x001E31C0 /* Reset Source: GLOBR */
10649 #define E830_PRTMAC_MDIO_DATA_MDIO_DATA_S 0
10650 #define E830_PRTMAC_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFF, 0)
10652 #define E830_PRTMAC_MDIO_DATA_RESERVED_2_M MAKEMASK(0x7FFF, 16)
10655 #define E830_PRTMAC_MDIO_REGADDR 0x001E31E0 /* Reset Source: GLOBR */
10656 #define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_S 0
10657 #define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0)
10658 #define E830_PRTMAC_REVISION 0x001E3000 /* Reset Source: GLOBR */
10659 #define E830_PRTMAC_REVISION_CORE_REVISION_S 0
10660 #define E830_PRTMAC_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0)
10662 #define E830_PRTMAC_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8)
10664 #define E830_PRTMAC_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16)
10665 #define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT 0x001E24C0 /* Reset Source: GLOBR */
10666 #define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT_RX_OFLOW_PKT_DRP_BSOP_CNT_S 0
10667 #define E830_PRTMAC_RX_OFLOW_PKT_DRP_BSOP_CNT_RX_OFLOW_PKT_DRP_BSOP_CNT_M MAKEMASK(0xFFFF, 0)
10668 #define E830_PRTMAC_RX_PAUSE_STATUS 0x001E33A0 /* Reset Source: GLOBR */
10669 #define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0
10670 #define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0)
10672 #define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 12)
10673 #define E830_PRTMAC_SCRATCH 0x001E3020 /* Reset Source: GLOBR */
10674 #define E830_PRTMAC_SCRATCH_SCRATCH_S 0
10675 #define E830_PRTMAC_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0)
10676 #define E830_PRTMAC_STATUS 0x001E3200 /* Reset Source: GLOBR */
10677 #define E830_PRTMAC_STATUS_RX_LOC_FAULT_S 0
10678 #define E830_PRTMAC_STATUS_RX_LOC_FAULT_M BIT(0)
10696 #define E830_PRTMAC_STATUS_RESERVED_10_M MAKEMASK(0x7FFFFF, 9)
10697 #define E830_PRTMAC_STATUS_SPARE 0x001E2740 /* Reset Source: GLOBR */
10698 #define E830_PRTMAC_STATUS_SPARE_DFD_STATUS_SPARE_S 0
10699 #define E830_PRTMAC_STATUS_SPARE_DFD_STATUS_SPARE_M MAKEMASK(0xFFFFFFFF, 0)
10700 #define E830_PRTMAC_TS_RX_PCS_LATENCY 0x001E2220 /* Reset Source: GLOBR */
10701 #define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_S 0
10702 #define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0)
10703 #define E830_PRTMAC_TS_TIMESTAMP 0x001E33E0 /* Reset Source: GLOBR */
10704 #define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_S 0
10705 #define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0)
10706 #define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020 /* Reset Source: GLOBR */
10707 #define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_S 0
10708 #define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_M MAKEMASK(0xFFFFFFFF, 0)
10709 #define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000 /* Reset Source: GLOBR */
10710 #define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_S 0
10711 #define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_M MAKEMASK(0xFFFFFFFF, 0)
10712 #define E830_PRTMAC_TS_TX_PCS_LATENCY 0x001E2200 /* Reset Source: GLOBR */
10713 #define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_S 0
10714 #define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0)
10715 #define E830_PRTMAC_TX_FIFO_SECTIONS 0x001E3100 /* Reset Source: GLOBR */
10716 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0
10717 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0)
10719 #define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16)
10720 #define E830_PRTMAC_TX_IPG_LENGTH 0x001E3220 /* Reset Source: GLOBR */
10721 #define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_S 0
10722 #define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x3F, 0)
10724 #define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_M MAKEMASK(0xFF, 8)
10726 #define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_M MAKEMASK(0xFFFF, 16)
10727 #define E830_PRTMAC_USER_TX_PAUSE_CNT 0x001E2760 /* Reset Source: GLOBR */
10728 #define E830_PRTMAC_USER_TX_PAUSE_CNT_USER_TX_PAUSE_CNT_S 0
10729 #define E830_PRTMAC_USER_TX_PAUSE_CNT_USER_TX_PAUSE_CNT_M MAKEMASK(0xFFFF, 0)
10730 #define E830_PRTMAC_XIF_MODE 0x001E3400 /* Reset Source: GLOBR */
10731 #define E830_PRTMAC_XIF_MODE_XGMII_ENA_S 0
10732 #define E830_PRTMAC_XIF_MODE_XGMII_ENA_M BIT(0)
10734 #define E830_PRTMAC_XIF_MODE_RESERVED_2_M MAKEMASK(0x7, 1)
10754 #define E830_PRTMAC_XIF_MODE_RESERVED2_M MAKEMASK(0x7, 13)
10766 #define E830_PRTMAC_XIF_MODE_RESERVED3_M MAKEMASK(0x7FF, 21)
10767 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF 0x001E2700 /* Reset Source: GLOBR */
10768 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF0_S 0
10769 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF0_M MAKEMASK(0xF, 0)
10771 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF1_M MAKEMASK(0xF, 4)
10773 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF2_M MAKEMASK(0xF, 8)
10775 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF3_M MAKEMASK(0xF, 12)
10777 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF4_M MAKEMASK(0xF, 16)
10779 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF5_M MAKEMASK(0xF, 20)
10781 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF6_M MAKEMASK(0xF, 24)
10783 #define E830_PRTPM_DFD_WOL_CNTR_PER_PF_PF7_M MAKEMASK(0xF, 28)
10792 #define E830_GL_MDET_HIF_UR_FIFO 0x00096844 /* Reset Source: CORER */
10793 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_NUM_S 0
10794 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0)
10796 #define E830_GL_MDET_HIF_UR_FIFO_PF_NUM_M MAKEMASK(0x7, 10)
10798 #define E830_GL_MDET_HIF_UR_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13)
10800 #define E830_GL_MDET_HIF_UR_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15)
10806 #define E830_GL_MDET_HIF_UR_FIFO_EVENT_CNT_M MAKEMASK(0xFF, 24)
10807 #define E830_GL_MDET_HIF_UR_PF_CNT(_i) (0x00096804 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
10809 #define E830_GL_MDET_HIF_UR_PF_CNT_CNT_S 0
10810 #define E830_GL_MDET_HIF_UR_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0)
10811 #define E830_GL_MDET_HIF_UR_VF(_i) (0x00096824 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
10813 #define E830_GL_MDET_HIF_UR_VF_VF_MAL_EVENT_S 0
10814 #define E830_GL_MDET_HIF_UR_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0)
10815 #define E830_PF_MDET_HIF_UR 0x00096880 /* Reset Source: CORER */
10816 #define E830_PF_MDET_HIF_UR_VALID_S 0
10817 #define E830_PF_MDET_HIF_UR_VALID_M BIT(0)
10818 #define E830_VM_MDET_TX_TCLAN(_i) (0x000FC348 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
10820 #define E830_VM_MDET_TX_TCLAN_VALID_S 0
10821 #define E830_VM_MDET_TX_TCLAN_VALID_M BIT(0)
10822 #define E830_VP_MDET_HIF_UR(_VF) (0x00096C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */
10824 #define E830_VP_MDET_HIF_UR_VALID_S 0
10825 #define E830_VP_MDET_HIF_UR_VALID_M BIT(0)
10828 #define E830_DMA_AGENT_AT0 0x000BE268 /* Reset Source: PCIR */
10829 #define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_S 0
10830 #define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0)
10832 #define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2)
10834 #define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4)
10836 #define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6)
10838 #define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8)
10840 #define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10)
10842 #define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12)
10844 #define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14)
10846 #define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16)
10848 #define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18)
10850 #define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20)
10852 #define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22)
10854 #define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24)
10856 #define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26)
10857 #define E830_DMA_AGENT_AT1 0x000BE26C /* Reset Source: PCIR */
10858 #define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_S 0
10859 #define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0)
10861 #define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2)
10863 #define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4)
10865 #define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6)
10867 #define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8)
10869 #define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10)
10871 #define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12)
10873 #define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14)
10875 #define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16)
10877 #define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18)
10879 #define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20)
10881 #define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22)
10883 #define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24)
10885 #define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26)
10900 #define E830_GLPCI_DOE_BUSY_STATUS 0x0009DF70 /* Reset Source: PCIR */
10901 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_S 0
10902 #define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_M BIT(0)
10913 #define E830_GLPCI_DOE_CFG 0x0009DF54 /* Reset Source: PCIR */
10914 #define E830_GLPCI_DOE_CFG_ENABLE_S 0
10915 #define E830_GLPCI_DOE_CFG_ENABLE_M BIT(0)
10923 #define E830_GLPCI_DOE_CFG_MSIX_VECTOR_M MAKEMASK(0x7FF, 8)
10924 #define E830_GLPCI_DOE_CTRL 0x0009DF60 /* Reset Source: PCIR */
10925 #define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_S 0
10926 #define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_M BIT(0)
10929 #define E830_GLPCI_DOE_DBG 0x0009DF6C /* Reset Source: PCIR */
10930 #define E830_GLPCI_DOE_DBG_CFG_BUSY_S 0
10931 #define E830_GLPCI_DOE_DBG_CFG_BUSY_M BIT(0)
10941 #define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_M MAKEMASK(0x1FF, 8)
10943 #define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_M MAKEMASK(0x1FF, 20)
10944 #define E830_GLPCI_DOE_ERR_EN 0x0009DF64 /* Reset Source: PCIR */
10945 #define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_S 0
10946 #define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_M BIT(0)
10975 #define E830_GLPCI_DOE_ERR_STATUS 0x0009DF68 /* Reset Source: PCIR */
10976 #define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_S 0
10977 #define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_M BIT(0)
11007 #define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_M MAKEMASK(0x1F, 24)
11008 #define E830_GLPCI_DOE_REQ_MSG_NUM_DWS 0x0009DF58 /* Reset Source: PCIR */
11009 #define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_S 0
11010 #define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0)
11011 #define E830_GLPCI_DOE_RESP 0x0009DF5C /* Reset Source: PCIR */
11012 #define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_S 0
11013 #define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0)
11016 #define E830_GLPCI_ERR_DBG 0x0009DF84 /* Reset Source: PCIR */
11017 #define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_S 0
11018 #define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_M MAKEMASK(0x3, 0)
11022 #define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_M MAKEMASK(0x7, 3)
11024 #define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_M MAKEMASK(0xF, 6)
11029 #define E830_GLPCI_PUSH_PQM_CTRL 0x0009DF74 /* Reset Source: POR */
11030 #define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_S 0
11031 #define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_M BIT(0)
11041 #define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_M MAKEMASK(0xF, 8)
11048 #define E830_GLPCI_PUSH_PQM_DBG 0x0009DF7C /* Reset Source: PCIR */
11049 #define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_S 0
11050 #define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_M MAKEMASK(0xFF, 0)
11052 #define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_M MAKEMASK(0xFF, 8)
11054 #define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_M MAKEMASK(0xF, 16)
11056 #define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_M MAKEMASK(0x1F, 20)
11059 #define E830_GLPCI_PUSH_PQM_IF_TO_STATUS 0x0009DF78 /* Reset Source: PCIR */
11060 #define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_S 0
11061 #define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_M BIT(0)
11062 #define E830_GLPCI_RDPU_CMD_DBG 0x000BE264 /* Reset Source: PCIR */
11063 #define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_S 0
11064 #define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_M MAKEMASK(0xFF, 0)
11066 #define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_M MAKEMASK(0xFF, 8)
11068 #define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_M MAKEMASK(0xFF, 16)
11070 #define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_M MAKEMASK(0xFF, 24)
11071 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0 0x000BE25C /* Reset Source: PCIR */
11072 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_S 0
11073 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0)
11075 #define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16)
11076 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1 0x000BE260 /* Reset Source: PCIR */
11077 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_S 0
11078 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0)
11080 #define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16)
11081 #define E830_GLPCI_RDPU_TAG 0x000BE258 /* Reset Source: PCIR */
11082 #define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_S 0
11083 #define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_M MAKEMASK(0xFF, 0)
11085 #define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_M MAKEMASK(0x3FF, 8)
11086 #define E830_GLPCI_SB_AER_MSG_OUT 0x0009DF80 /* Reset Source: PCIR */
11087 #define E830_GLPCI_SB_AER_MSG_OUT_EN_S 0
11088 #define E830_GLPCI_SB_AER_MSG_OUT_EN_M BIT(0)
11092 #define E830_PF_FUNC_RID_HOST_M MAKEMASK(0x3, 16)
11093 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI(_i) (0x00553004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
11095 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_S 0
11096 #define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_M MAKEMASK(0xFFFFFF, 0)
11097 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO(_i) (0x00553000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */
11099 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S 0
11100 #define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)
11101 #define E830_GLPES_PFRXRPCNPHANDLED(_i) (0x00552C00 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
11103 #define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_S 0
11104 #define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_M MAKEMASK(0xFFFFFFFF, 0)
11105 #define E830_GLPES_PFRXRPCNPIGNORED(_i) (0x00552800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
11107 #define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_S 0
11108 #define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_M MAKEMASK(0xFFFFFF, 0)
11109 #define E830_GLPES_PFTXNPCNPSENT(_i) (0x00553800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */
11111 #define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_S 0
11112 #define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_M MAKEMASK(0xFFFFFF, 0)
11113 #define E830_GLQF_FLAT_HLUT(_i) (0x004C0000 + ((_i) * 4)) /* _i=0...8191 */ /* Reset Source: CORER */
11115 #define E830_GLQF_FLAT_HLUT_LUT0_S 0
11116 #define E830_GLQF_FLAT_HLUT_LUT0_M MAKEMASK(0xFF, 0)
11118 #define E830_GLQF_FLAT_HLUT_LUT1_M MAKEMASK(0xFF, 8)
11120 #define E830_GLQF_FLAT_HLUT_LUT2_M MAKEMASK(0xFF, 16)
11122 #define E830_GLQF_FLAT_HLUT_LUT3_M MAKEMASK(0xFF, 24)
11123 #define E830_GLQF_QGRP_CNTX(_i) (0x00490000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
11125 #define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_S 0
11126 #define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_M MAKEMASK(0x7FFF, 0)
11128 #define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_M MAKEMASK(0xF, 16)
11130 #define E830_GLQF_QGRP_CNTX_VSI_M MAKEMASK(0x3FF, 20)
11131 #define E830_GLQF_QGRP_PF_OWNER(_i) (0x00484000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */
11133 #define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_S 0
11134 #define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_M MAKEMASK(0x7, 0)
11135 #define E830_PFQF_LUT_ALLOC 0x0048E000 /* Reset Source: CORER */
11136 #define E830_PFQF_LUT_ALLOC_LUT_BASE_S 0
11137 #define E830_PFQF_LUT_ALLOC_LUT_BASE_M MAKEMASK(0x7FFF, 0)
11139 #define E830_PFQF_LUT_ALLOC_LUT_SIZE_M MAKEMASK(0xF, 16)
11140 #define E830_VSIQF_DEF_QGRP(_VSI) (0x00486000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
11142 #define E830_VSIQF_DEF_QGRP_DEF_QGRP_S 0
11143 #define E830_VSIQF_DEF_QGRP_DEF_QGRP_M MAKEMASK(0x7FF, 0)
11144 #define E830_GLPRT_BPRCH_BPRCH_S 0
11145 #define E830_GLPRT_BPRCH_BPRCH_M MAKEMASK(0xFF, 0)
11146 #define E830_GLPRT_BPRCL_BPRCL_S 0
11147 #define E830_GLPRT_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0)
11148 #define E830_GLPRT_BPTCH_BPTCH_S 0
11149 #define E830_GLPRT_BPTCH_BPTCH_M MAKEMASK(0xFF, 0)
11150 #define E830_GLPRT_BPTCL_BPTCL_S 0
11151 #define E830_GLPRT_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0)
11152 #define E830_GLPRT_UPTCL_UPTCL_S 0
11153 #define E830_GLPRT_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0)
11154 #define E830_GLPTM_ART_CTL 0x00088B50 /* Reset Source: POR */
11155 #define E830_GLPTM_ART_CTL_ACTIVE_S 0
11156 #define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0)
11169 #define E830_GLPTM_ART_TIME_H 0x00088B54 /* Reset Source: POR */
11170 #define E830_GLPTM_ART_TIME_H_ART_TIME_H_S 0
11171 #define E830_GLPTM_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0)
11172 #define E830_GLPTM_ART_TIME_L 0x00088B58 /* Reset Source: POR */
11173 #define E830_GLPTM_ART_TIME_L_ART_TIME_L_S 0
11174 #define E830_GLPTM_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11175 #define E830_GLTSYN_PTMTIME_H(_i) (0x00088B48 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
11177 #define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_S 0
11178 #define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0)
11179 #define E830_GLTSYN_PTMTIME_L(_i) (0x00088B40 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */
11181 #define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_S 0
11182 #define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0)
11183 #define E830_GLTSYN_TIME_H_0_AL 0x0008A004 /* Reset Source: CORER */
11184 #define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_S 0
11185 #define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11186 #define E830_GLTSYN_TIME_H_1_AL 0x0008B004 /* Reset Source: CORER */
11187 #define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_S 0
11188 #define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11189 #define E830_GLTSYN_TIME_L_0_AL 0x0008A000 /* Reset Source: CORER */
11190 #define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_S 0
11191 #define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11192 #define E830_GLTSYN_TIME_L_1_AL 0x0008B000 /* Reset Source: CORER */
11193 #define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_S 0
11194 #define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11195 #define E830_PFPTM_SEM 0x00088B00 /* Reset Source: PFR */
11196 #define E830_PFPTM_SEM_BUSY_S 0
11197 #define E830_PFPTM_SEM_BUSY_M BIT(0)
11199 #define E830_PFPTM_SEM_PF_OWNER_M MAKEMASK(0x7, 4)
11200 #define E830_VSI_PASID_1(_VSI) (0x00094000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
11202 #define E830_VSI_PASID_1_PASID_S 0
11203 #define E830_VSI_PASID_1_PASID_M MAKEMASK(0xFFFFF, 0)
11206 #define E830_VSI_PASID_2(_VSI) (0x00095000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
11208 #define E830_VSI_PASID_2_PASID_S 0
11209 #define E830_VSI_PASID_2_PASID_M MAKEMASK(0xFFFFF, 0)
11213 #define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_M MAKEMASK(0x3F, 15)
11215 #define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_M MAKEMASK(0x3, 29)
11217 #define E830_VSIQF_QGRP_CFG(_VSI) (0x00492000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */
11219 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_ENABLE_S 0
11220 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_ENABLE_M BIT(0)
11222 #define E830_VSIQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_M MAKEMASK(0x7, 1)
11223 #define E830_GLDCB_RTC_BLOCKED 0x0012274C /* Reset Source: CORER */
11224 #define E830_GLDCB_RTC_BLOCKED_BLOCKED_S 0
11225 #define E830_GLDCB_RTC_BLOCKED_BLOCKED_M MAKEMASK(0xFFFFFFFF, 0)
11226 #define E830_GLDCB_RTCID 0x00122900 /* Reset Source: CORER */
11227 #define E830_GLDCB_RTCID_IMM_DROP_TC_S 0
11228 #define E830_GLDCB_RTCID_IMM_DROP_TC_M MAKEMASK(0xFFFFFFFF, 0)
11229 #define E830_GLDCB_RTCTI_CDS_SET 0x00122748 /* Reset Source: CORER */
11230 #define E830_GLDCB_RTCTI_CDS_SET_CDS_SET_S 0
11231 #define E830_GLDCB_RTCTI_CDS_SET_CDS_SET_M MAKEMASK(0xFFFFFFFF, 0)
11232 #define E830_GLDCB_RTCTQ_PD(_i) (0x00122700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
11234 #define E830_GLDCB_RTCTQ_PD_RXQNUM_S 0
11235 #define E830_GLDCB_RTCTQ_PD_RXQNUM_M MAKEMASK(0x7FF, 0)
11238 #define E830_GLDCB_RTCTQ_SET 0x00122750 /* Reset Source: CORER */
11239 #define E830_GLDCB_RTCTQ_SET_RTCTQ_VALID_S 0
11240 #define E830_GLDCB_RTCTQ_SET_RTCTQ_VALID_M MAKEMASK(0xFFFFFFFF, 0)
11241 #define E830_GLDCB_RTCTQ_STICKY_EN 0x00122754 /* Reset Source: CORER */
11242 #define E830_GLDCB_RTCTQ_STICKY_EN_EN_S 0
11243 #define E830_GLDCB_RTCTQ_STICKY_EN_EN_M BIT(0)
11244 #define E830_GLDCB_RTCTS_PD(_i) (0x00122720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */
11246 #define E830_GLDCB_RTCTS_PD_PFCTIMER_S 0
11247 #define E830_GLDCB_RTCTS_PD_PFCTIMER_M MAKEMASK(0x3FFF, 0)
11248 #define E830_GLRPB_TC_TOTAL_PC(_i) (0x000ACD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */
11250 #define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_S 0
11251 #define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0)
11252 #define E830_VFINT_ITRN_64(_i, _j) (0x00002C00 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...2 */ /* Reset Source: CORER */
11254 #define E830_VFINT_ITRN_64_INTERVAL_S 0
11255 #define E830_VFINT_ITRN_64_INTERVAL_M MAKEMASK(0xFFF, 0)
11256 #define E830_GLQTX_TXTIME_DBELL_LSB1(_DBQM) (0x0000D000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
11258 #define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_S 0
11259 #define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
11260 #define E830_GLQTX_TXTIME_DBELL_MSB1(_DBQM) (0x0000D004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
11262 #define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_S 0
11263 #define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
11264 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB(_DBQM) (0x00040000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
11266 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_S 0
11267 #define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
11268 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB(_DBQM) (0x00040004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */
11270 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_S 0
11271 #define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)
11272 #define E830_GLTSYN_TIME_H_0_AL1 0x00003004 /* Reset Source: CORER */
11273 #define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_S 0
11274 #define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11275 #define E830_GLTSYN_TIME_H_1_AL1 0x0000300C /* Reset Source: CORER */
11276 #define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_S 0
11277 #define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11278 #define E830_GLTSYN_TIME_L_0_AL1 0x00003000 /* Reset Source: CORER */
11279 #define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_S 0
11280 #define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11281 #define E830_GLTSYN_TIME_L_1_AL1 0x00003008 /* Reset Source: CORER */
11282 #define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_S 0
11283 #define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0)
11284 #define E830_VSI_VSI2F_LEM(_VSI) (0x006100A0 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */
11286 #define E830_VSI_VSI2F_LEM_VFVMNUMBER_S 0
11287 #define E830_VSI_VSI2F_LEM_VFVMNUMBER_M MAKEMASK(0x3FF, 0)
11289 #define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_M MAKEMASK(0x3, 10)
11291 #define E830_VSI_VSI2F_LEM_PFNUMBER_M MAKEMASK(0x7, 12)
11293 #define E830_VSI_VSI2F_LEM_BUFFERNUMBER_M MAKEMASK(0x7, 16)
11295 #define E830_VSI_VSI2F_LEM_VSI_NUMBER_M MAKEMASK(0x3FF, 20)