Lines Matching +full:0 +full:x8006
44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
59 /* Get version (direct 0x0001) */
73 /* Send driver version (indirect 0x0002) */
84 /* Queue Shutdown (direct 0x0003) */
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
91 /* Get Expanded Error Code (0x0005, direct) */
94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF
99 /* Request resource ownership (direct 0x0008)
100 * Release resource ownership (direct 0x0009)
125 #define ICE_AQ_RES_GLBL_SUCCESS 0
131 /* Get function capabilities (indirect 0x000A)
132 * Get device capabilities (indirect 0x000B)
146 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001
147 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002
148 #define ICE_AQC_CAPS_OS2BMC 0x0004
149 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
150 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
151 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006
152 #define ICE_AQC_CAPS_WOL_PROXY 0x0008
153 #define ICE_AQC_CAPS_SRIOV 0x0012
154 #define ICE_AQC_CAPS_VF 0x0013
155 #define ICE_AQC_CAPS_VMDQ 0x0014
156 #define ICE_AQC_CAPS_802_1QBG 0x0015
157 #define ICE_AQC_CAPS_802_1BR 0x0016
158 #define ICE_AQC_CAPS_VSI 0x0017
159 #define ICE_AQC_CAPS_DCB 0x0018
160 #define ICE_AQC_CAPS_RSVD 0x0021
161 #define ICE_AQC_CAPS_ISCSI 0x0022
162 #define ICE_AQC_CAPS_RSS 0x0040
163 #define ICE_AQC_CAPS_RXQS 0x0041
164 #define ICE_AQC_CAPS_TXQS 0x0042
165 #define ICE_AQC_CAPS_MSIX 0x0043
166 #define ICE_AQC_CAPS_MAX_MTU 0x0047
167 #define ICE_AQC_CAPS_CEM 0x00F2
168 #define ICE_AQC_CAPS_IWARP 0x0051
169 #define ICE_AQC_CAPS_LED 0x0061
170 #define ICE_AQC_CAPS_SDP 0x0062
171 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064
172 #define ICE_AQC_CAPS_SENSOR_READING 0x0067
173 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073
174 #define ICE_AQC_CAPS_SKU 0x0074
175 #define ICE_AQC_CAPS_PORT_MAP 0x0075
176 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
177 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
178 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
179 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081
180 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
181 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
182 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
183 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
184 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
185 #define ICE_AQC_CAPS_DYN_FLATTENING 0x008A
186 #define ICE_AQC_CAPS_OROM_RECOVERY_UPDATE 0x0090
187 #define ICE_AQC_CAPS_ROCEV2_LAG 0x0092
188 #define ICE_AQC_BIT_ROCEV2_LAG 0x01
189 #define ICE_AQC_BIT_SRIOV_LAG 0x02
190 #define ICE_AQC_CAPS_NEXT_CLUSTER_ID 0x0096
203 /* Manage MAC address, read command - indirect (0x0107)
215 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
227 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
232 /* Manage MAC address, write command - direct (0x0108) */
236 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
240 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
248 /* Clear PXE Command and response (direct 0x0110) */
251 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
255 /* Configure No-Drop Policy Command (direct 0x0112) */
258 #define ICE_AQC_FORCE_NO_DROP BIT(0)
262 /* Get switch configuration (0x0200) */
283 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
285 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
287 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
288 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
295 /* Bit 14..0 : PF/VF number VSI belongs to
299 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
301 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
305 /* Set Port parameters, (direct, 0x0203) */
308 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0)
312 #define ICE_AQC_SET_P_PARAMS_VSI_S 0
313 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S)
316 #define ICE_AQC_SET_P_PARAMS_SWID_S 0
317 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S)
320 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
325 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NORMAL 0x00
326 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NO 0x01
327 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_HIGH 0x02
333 * Get Resource Allocation command (indirect 0x0204)
334 * Allocate Resources command (indirect 0x0208)
335 * Free Resources command (indirect 0x0209)
336 * Get Allocated Resource Descriptors Command (indirect 0x020A)
338 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
339 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
340 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
341 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
342 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
343 #define ICE_AQC_RES_TYPE_RECIPE 0x05
344 #define ICE_AQC_RES_TYPE_PROFILE 0x06
345 #define ICE_AQC_RES_TYPE_SWID 0x07
346 #define ICE_AQC_RES_TYPE_VSI 0x08
347 #define ICE_AQC_RES_TYPE_FLU 0x09
348 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
349 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
350 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
351 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
352 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
353 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
354 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
355 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
356 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
357 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
358 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
359 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
360 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
361 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
362 /* Resource types 0x62-67 are reserved for Hash profile builder */
363 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
364 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
372 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
374 #define ICE_AQC_RES_TYPE_S 0
375 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
377 /* Get Resource Allocation command (indirect 0x0204) */
387 __le16 res_type; /* Types defined above cmd 0x0204 */
394 /* Allocate Resources command (indirect 0x0208)
395 * Free Resources command (indirect 0x0209)
414 __le16 res_type; /* Types defined above cmd 0x0204 */
417 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
422 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
426 __le16 res; /* Types defined above cmd 0x0204 */
441 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
445 #define ICE_AQ_VLAN_PRIO_TAG_S 0
446 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
447 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
448 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
449 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
450 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
451 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
452 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
453 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
456 #define ICE_AQ_VLAN_RDMA_TAG_S 0
457 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
458 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
459 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
462 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
463 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
467 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
470 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
475 /* Add VSI (indirect 0x0210)
476 * Update VSI (indirect 0x0211)
477 * Get VSI (indirect 0x0212)
478 * Free VSI (indirect 0x0213)
482 #define ICE_AQ_VSI_NUM_S 0
483 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
486 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
490 #define ICE_AQ_VSI_TYPE_S 0
491 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
492 #define ICE_AQ_VSI_TYPE_VF 0x0
493 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
494 #define ICE_AQ_VSI_TYPE_PF 0x2
495 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
501 * Add VSI (indirect 0x0210)
502 * Update VSI (indirect 0x0211)
503 * Free VSI (indirect 0x0213)
529 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
547 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
548 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
549 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
553 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
554 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
558 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
561 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
562 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
568 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
569 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
570 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
571 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
572 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
575 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
576 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
577 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
578 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
579 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
584 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
585 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
587 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
589 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
591 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
593 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
595 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
597 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
599 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
604 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
605 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
606 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
607 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
608 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
609 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
611 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
612 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
613 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
614 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
615 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
618 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
619 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
620 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
621 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
626 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
627 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
629 #define ICE_AQ_VSI_Q_S 0
630 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
632 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
633 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
635 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
638 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
639 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
640 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
641 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
642 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
644 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
646 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
647 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
648 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
649 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
650 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
652 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
653 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
656 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
664 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
670 #define ICE_AQ_VSI_FD_DEF_Q_S 0
671 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
673 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
675 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
676 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
678 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
682 #define ICE_AQ_VSI_PASID_ID_S 0
683 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
688 /* Add/update mirror rule - direct (0x0260) */
690 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
691 #define ICE_AQC_RULE_ID_S 0
692 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
698 * 0 = Remove VSI from mirror rule
702 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
704 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
705 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
713 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
719 #define ICE_AQC_RULE_TYPE_S 0
720 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
722 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
723 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
727 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
729 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
742 /* Delete mirror rule - direct(0x0261) */
751 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
752 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
758 /* Set/Get storm config - (direct 0x0280, 0x0281) */
765 /* Bit 18:0 - Traffic upper threshold size
768 #define ICE_AQ_THRESHOLD_S 0
769 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
772 /* Bit 0: MDIPW - Drop Multicast packets in previous window
777 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
788 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
794 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
814 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
815 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
816 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
817 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
818 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
819 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
820 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
838 /* Bit 0:1 - Action type */
839 #define ICE_SINGLE_ACT_TYPE_S 0x00
840 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
848 /* Action type = 0 - Forward to VSI or VSI list */
849 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
852 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
854 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
861 #define ICE_SINGLE_ACT_TO_Q 0x1
863 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
865 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
869 #define ICE_SINGLE_ACT_PRUNE 0x2
873 /* Bit 18 should be set to 0 for this action */
876 #define ICE_SINGLE_ACT_PTR 0x2
878 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
887 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
890 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
893 /* Other action = 0 - Mirror VSI */
894 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
897 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
903 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
925 /* Bit 0:1 - Action type */
926 #define ICE_LG_ACT_TYPE_S 0
927 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
929 /* Action type = 0 - Forward to VSI or VSI list */
930 #define ICE_LG_ACT_VSI_FORWARDING 0
932 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
934 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
941 #define ICE_LG_ACT_TO_Q 0x1
943 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
945 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
949 #define ICE_LG_ACT_PRUNE 0x2
955 #define ICE_LG_OTHER_ACT_MIRROR 0x3
957 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
960 #define ICE_LG_ACT_GENERIC 0x5
962 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
964 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
966 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
970 #define ICE_LG_ACT_STAT_COUNT 0x7
972 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
999 /* PFC Ignore (direct 0x0301)
1006 #define ICE_AQC_PFC_IGNORE_CLEAR 0
1010 /* Query PFC Mode (direct 0x0302)
1011 * Set PFC Mode (direct 0x0303)
1016 #define ICE_AQC_PFC_NOT_CONFIGURED 0
1018 #define ICE_AQC_DCB_DIS 0
1024 /* Set DCB Parameters (direct 0x0306) */
1027 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
1030 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
1035 /* Get Default Topology (indirect 0x0400) */
1045 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */
1048 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0)
1054 #define ICE_AQC_TX_TOPO_GET_NO_UPDATE 0
1063 /* Update TSE (indirect 0x0403)
1064 * Get TSE (indirect 0x0404)
1065 * Add TSE (indirect 0x0401)
1066 * Delete TSE (indirect 0x040F)
1067 * Move TSE (indirect 0x0408)
1068 * Suspend Nodes (indirect 0x0409)
1069 * Resume Nodes (indirect 0x040A)
1099 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1100 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1101 #define ICE_AQC_ELEM_TYPE_TC 0x2
1102 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1103 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1104 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1105 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1107 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1112 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1113 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1114 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1115 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1116 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1117 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1119 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1121 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1156 /* Query Port ETS (indirect 0x040E)
1170 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1175 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1177 #define ICE_TC_NODE_PRIO_S 0x4
1183 * Add RL profile (indirect 0x0410)
1184 * Query RL profile (indirect 0x0411)
1185 * Remove RL profile (indirect 0x0415)
1200 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1201 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1202 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1206 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1207 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1216 /* Config Node Attributes (indirect 0x0419)
1217 * Query Node Attributes (indirect 0x041A)
1232 /* Configure L2 Node CGD (indirect 0x0414)
1249 /* Query Scheduler Resource Allocation (indirect 0x0412)
1288 /* Query Node to Root Topology (indirect 0x0413)
1298 /* Get PHY capabilities (indirect 0x0600) */
1304 #define ICE_AQC_GET_PHY_RQM BIT(0)
1314 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1326 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1392 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1414 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1422 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1424 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1429 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1444 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1452 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1454 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1458 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1459 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1461 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1467 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1468 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1481 /* Set PHY capabilities (direct 0x0601)
1496 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1497 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1511 /* Set MAC Config command data structure (direct 0x0603) */
1516 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1518 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1524 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1525 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1526 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1530 /* Restart AN command data structure (direct 0x0605)
1542 /* Get link status (indirect 0x0607), also used for Link Status Event */
1547 #define ICE_AQ_LSE_M 0x3
1548 #define ICE_AQ_LSE_NOP 0x0
1549 #define ICE_AQ_LSE_DIS 0x2
1550 #define ICE_AQ_LSE_ENA 0x3
1552 #define ICE_AQ_LSE_IS_ENABLED 0x1
1570 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1578 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1586 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1595 #define ICE_AQ_AN_COMPLETED BIT(0)
1604 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1608 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1609 #define ICE_AQ_LINK_TX_ACTIVE 0
1613 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
1617 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
1620 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1623 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1626 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1628 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1632 #define ICE_AQ_PWR_CLASS_M 0x3F
1633 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1635 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1640 #define ICE_AQ_LINK_SPEED_M 0xFFF
1641 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1656 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */
1664 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0)
1671 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0)
1676 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0)
1683 /* Set event mask command (direct 0x0613) */
1703 /* Set PHY Loopback command (direct 0x0619) */
1707 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0)
1710 #define ICE_AQ_PHY_LB_EN BIT(0)
1712 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0
1715 #define ICE_AQ_PHY_LB_LEVEL_PMD 0
1720 /* Set MAC Loopback command (direct 0x0620) */
1723 #define ICE_AQ_MAC_LB_EN BIT(0)
1728 /* Get sensor reading (direct 0x0632) */
1731 #define ICE_AQC_INT_TEMP_SENSOR 0x0
1733 #define ICE_AQC_INT_TEMP_FORMAT 0x0
1739 /* Get sensor reading response (direct 0x0632) */
1743 /* Output data for sensor 0x00, format 0x00 */
1754 /* DNL Get Status command (indirect 0x0680)
1761 #define ICE_AQ_DNL_STATUS_IDLE 0x0
1762 #define ICE_AQ_DNL_STATUS_RESERVED 0x1
1763 #define ICE_AQ_DNL_STATUS_STOPPED 0x2
1764 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */
1766 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S)
1767 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S)
1768 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S)
1770 #define ICE_AQ_DNL_ST_PTR_S 0x0
1771 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S)
1788 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */
1789 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */
1790 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */
1791 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */
1792 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */
1793 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */
1794 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */
1795 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */
1796 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */
1797 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */
1803 #define ICE_AQ_DNL_STACK_SZ_S 0
1804 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S)
1806 #define ICE_AQ_DNL_PORT_CNT_S 0
1807 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S)
1814 /* DNL run command (direct 0x0681) */
1818 #define ICE_AQ_DNL_CMD_S 0
1819 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S)
1820 #define ICE_AQ_DNL_CMD_RESET 0x0
1821 #define ICE_AQ_DNL_CMD_RUN 0x1
1822 #define ICE_AQ_DNL_CMD_STEP 0x3
1823 #define ICE_AQ_DNL_CMD_ABORT 0x4
1824 #define ICE_AQ_DNL_CMD_SET_PC 0x7
1826 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S)
1827 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0
1828 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1
1833 /* DNL call command (indirect 0x0682)
1840 #define ICE_AQC_ACT_ID_DNL 0x1129
1849 #define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT)
1850 #define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT)
1851 #define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT)
1852 #define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT)
1853 #define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT)
1854 #define ICE_AQC_RX_EQU_DRATE (0x15 << ICE_AQC_RX_EQU_SHIFT)
1855 #define ICE_AQC_TX_EQU_PRE1 0x0
1856 #define ICE_AQC_TX_EQU_PRE3 0x3
1857 #define ICE_AQC_TX_EQU_ATTEN 0x4
1858 #define ICE_AQC_TX_EQU_POST1 0x8
1859 #define ICE_AQC_TX_EQU_PRE2 0xC
1862 #define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT)
1863 #define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT)
1873 /* DNL call command/response buffer (indirect 0x0682) */
1883 * DNL read sto command (indirect 0x0683)
1884 * DNL write sto command (indirect 0x0684)
1889 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0
1890 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1
1891 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2
1899 * DNL read sto response (indirect 0x0683)
1900 * DNL write sto response (indirect 0x0684)
1911 /* DNL set breakpoints command (indirect 0x0686) */
1918 /* DNL set breakpoints data buffer structure (indirect 0x0686) */
1921 u8 ena; /* 0- disabled, 1- enabled */
1926 /* DNL read log data command(indirect 0x0687) */
1936 /* DNL read log data response(indirect 0x0687) */
1949 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1951 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1952 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1953 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1964 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1965 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1977 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1978 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1981 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM 0
1983 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1986 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1988 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1991 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1994 /* Get Link Topology Handle (direct, 0x06E0) */
1998 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
2002 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
2007 #define ICE_AQC_I2C_DATA_SIZE_S 0
2008 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S)
2010 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0
2013 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
2017 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F
2018 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF
2022 /* Read I2C Response (direct, 0x06E2) */
2027 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */
2031 #define ICE_AQC_MDIO_DEV_S 0
2032 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S)
2036 #define ICE_AQC_MDIO_BUS_ADDR_S 0
2037 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S)
2043 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */
2047 #define ICE_AQC_GPIO_FUNC_S 0
2048 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S)
2050 #define ICE_AQC_GPIO_ON BIT(0)
2051 #define ICE_AQC_GPIO_OFF 0
2055 /* Set LED (direct, 0x06E8) */
2059 #define ICE_AQC_LED_COLOR_S 0
2060 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S)
2061 #define ICE_AQC_LED_COLOR_SKIP 0
2069 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S)
2070 #define ICE_AQC_LED_BLINK_NONE 0
2080 /* Set Port Identification LED (direct, 0x06E9) */
2084 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
2086 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
2087 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
2091 /* Get Port Options (indirect, 0x06EA) */
2095 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0)
2097 #define ICE_AQC_PORT_OPT_COUNT_S 0
2098 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S)
2102 #define ICE_AQC_PORT_OPT_ACTIVE_S 0
2103 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S)
2107 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0
2108 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S)
2118 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0
2119 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S)
2121 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S)
2123 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0
2124 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S)
2125 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0
2139 /* Set Port Option (direct, 0x06EB) */
2143 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0)
2148 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
2151 #define ICE_AQC_GPIO_HANDLE_S 0
2152 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
2158 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
2162 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
2164 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
2165 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
2167 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
2170 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
2171 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
2177 #define ICE_AQC_SFF_EEPROM_BANK_S 0
2178 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
2180 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
2185 /* SW Set GPIO command (indirect 0x6EF)
2186 * SW Get GPIO command (indirect 0x6F0)
2190 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0
2191 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
2193 #define ICE_AQC_SW_GPIO_NUMBER_S 0
2194 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
2197 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
2201 /* Program Topology Device NVM (direct, 0x06F2) */
2207 /* Read Topology Device NVM (direct, 0x06F3) */
2215 /* NVM Read command (indirect 0x0701)
2216 * NVM Erase commands (direct 0x0702)
2217 * NVM Write commands (indirect 0x0703)
2218 * NVM Write Activate commands (direct 0x0707)
2219 * NVM Shadow RAM Dump commands (direct 0x0707)
2222 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
2226 #define ICE_AQC_NVM_LAST_CMD BIT(0)
2227 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
2230 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
2239 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
2241 #define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */
2242 #define ICE_AQC_NVM_POR_FLAG 0
2245 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
2254 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
2263 #define ICE_AQC_NVM_START_POINT 0
2264 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
2266 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
2271 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
2275 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
2277 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
2281 #define ICE_AQC_NVM_SDP_CFG_PTR_OFFSET 0xD8
2283 #define ICE_AQC_NVM_SDP_CFG_PTR_M MAKEMASK(0x7FFF, 0)
2291 #define ICE_AQC_NVM_SDP_CFG_PIN_MASK MAKEMASK(0x3FF, \
2294 #define ICE_AQC_NVM_SDP_CFG_CHAN_MASK MAKEMASK(0x3, \
2297 #define ICE_AQC_NVM_SDP_CFG_DIR_MASK MAKEMASK(0x1, \
2299 #define ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET 0
2300 #define ICE_AQC_NVM_SDP_CFG_SDP_NUM_MASK MAKEMASK(0x7, \
2302 #define ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK MAKEMASK(0x1, 15)
2304 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130
2305 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B
2306 #define ICE_AQC_NVM_CMPO_MOD_ID 0x153
2315 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the
2322 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0)
2337 /* Used for 0x0704 as well as for 0x0705 commands */
2340 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
2357 /* NVM Checksum Command (direct, 0x0706) */
2360 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
2364 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
2368 /* Used for NVM Sanitization command - 0x070C */
2371 #define ICE_AQ_NVM_SANITIZE_REQ_READ 0
2372 #define ICE_AQ_NVM_SANITIZE_REQ_OPERATE BIT(0)
2374 #define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_BITS 0
2376 #define ICE_AQ_NVM_SANITIZE_OPERATE_SUBJECT_CLEAR 0
2378 #define ICE_AQ_NVM_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0)
2380 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0)
2384 #define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0)
2392 * Send to PF command (indirect 0x0801) ID is only used by PF
2394 * Send to VF command (indirect 0x0802) ID is only used by PF
2404 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */
2412 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */
2420 /* Done Alternate Write (direct 0x0904) */
2423 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0)
2428 /* Clear Port Alternate Write (direct 0x0906) */
2433 /* Get LLDP MIB (indirect 0x0A00)
2434 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
2439 #define ICE_AQ_LLDP_MIB_TYPE_S 0
2440 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
2441 #define ICE_AQ_LLDP_MIB_LOCAL 0
2445 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
2446 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
2448 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
2449 #define ICE_AQ_LLDP_TX_S 0x4
2450 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
2451 #define ICE_AQ_LLDP_TX_ACTIVE 0
2456 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S)
2457 #define ICE_AQ_LLDP_DCBX_NA 0
2460 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
2461 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
2462 * Get LLDP MIB (0x0A00) response only.
2465 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0
2467 (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S)
2468 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0
2477 /* Configure LLDP MIB Change Event (direct 0x0A01) */
2481 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2482 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
2485 (0x1 << ICE_AQ_LLDP_MIB_PENDING_S)
2486 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0
2491 /* Add LLDP TLV (indirect 0x0A02)
2492 * Delete LLDP TLV (indirect 0x0A04)
2495 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2503 /* Update LLDP TLV (indirect 0x0A03) */
2505 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2514 /* Stop LLDP (direct 0x0A05) */
2517 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
2518 #define ICE_AQ_LLDP_AGENT_STOP 0x0
2524 /* Start LLDP (direct 0x0A06) */
2527 #define ICE_AQ_LLDP_AGENT_START BIT(0)
2532 /* Get CEE DCBX Oper Config (0x0A07)
2542 #define ICE_AQC_CEE_APP_FCOE_S 0
2543 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
2545 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
2547 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
2549 #define ICE_AQC_CEE_PG_STATUS_S 0
2550 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
2552 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
2554 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
2556 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
2558 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
2562 /* Set Local LLDP MIB (indirect 0x0A08)
2567 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
2568 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
2570 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
2581 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
2582 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
2587 /* Stop/Start LLDP Agent (direct 0x0A09)
2594 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
2595 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
2600 /* LLDP Filter Control (direct 0x0A0A) */
2603 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0)
2604 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
2605 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
2606 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2
2612 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
2615 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
2616 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
2623 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
2624 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
2645 ICE_LUT_VSI = 0,
2659 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
2662 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
2663 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
2665 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
2678 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
2687 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */
2695 /* Add Tx LAN Queues (indirect 0x0C30) */
2705 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2716 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2728 /* Disable Tx LAN Queues (indirect 0x0C31) */
2731 #define ICE_AQC_Q_DIS_CMD_S 0
2732 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
2733 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
2741 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2742 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2744 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2750 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2766 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2773 /* Tx LAN Queues Cleanup Event (0x0C31) */
2780 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2783 #define ICE_AQC_Q_CMD_TYPE_S 0
2784 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2794 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2815 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
2824 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
2833 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
2845 /* Move RDMA Queue Set (indirect 0x0C34) */
2848 #define ICE_AQC_PF_MODE_SAME_PF 0x0
2849 #define ICE_AQC_PF_MODE_GIVE_OWNERSHIP 0x1
2850 #define ICE_AQC_PF_MODE_KEEP_OWNERSHIP 0x2
2869 /* Download Package (indirect 0x0C40) */
2870 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
2873 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2887 /* Get Package Info List (indirect 0x0C43) */
2917 /* Get Package Info List response buffer format (0x0C43) */
2923 /* Driver Shared Parameters (direct, 0x0C90) */
2926 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2927 #define ICE_AQC_DRIVER_PARAM_SET ((u8)0)
2937 /* Lan Queue Overflow Event (direct, 0x1001) */
2944 /* Debug Dump Internal Data (indirect 0xFF08) */
2947 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E810 0
2963 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_START_ALL 0
2981 ICE_AQC_FW_LOG_ID_GENERAL = 0,
3016 /* Set Health Status (direct 0xFF20) */
3019 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
3025 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101
3026 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102
3027 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103
3028 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104
3029 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105
3030 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
3031 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
3032 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
3033 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109
3034 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
3035 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
3036 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
3037 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F
3038 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
3039 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
3040 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
3041 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
3042 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
3043 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
3044 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
3045 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
3046 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120
3047 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121
3048 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
3049 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
3050 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
3051 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
3052 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
3053 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
3054 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
3055 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507
3056 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508
3057 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
3058 #define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A
3059 #define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET 0x50B
3060 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C
3061 #define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D
3062 #define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000
3063 #define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001
3064 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002
3066 /* Get Health Status codes (indirect 0xFF21) */
3074 /* Get Health Status (indirect 0xFF22) */
3082 /* Get Health Status event buffer entry, (0xFF22)
3088 #define ICE_AQC_HEALTH_STATUS_PF (0x1)
3089 #define ICE_AQC_HEALTH_STATUS_PORT (0x2)
3090 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3)
3092 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF)
3096 /* Clear Health Status (direct 0xFF23) */
3101 /* Set FW Logging configuration (indirect 0xFF30)
3102 * Register for FW Logging (indirect 0xFF31)
3103 * Query FW Logging (indirect 0xFF32)
3104 * FW Log Event (indirect 0xFF33)
3105 * Get FW Log (indirect 0xFF34)
3106 * Clear FW Log (indirect 0xFF35)
3110 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
3114 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
3116 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
3136 * Set Firmware Logging Configuration (0xFF30)
3137 * Query FW Logging (0xFF32)
3285 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
3290 #define ICE_AQ_FLAG_DD_S 0
3302 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
3303 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
3304 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
3305 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
3306 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
3307 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
3308 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
3309 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
3310 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
3311 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
3312 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
3316 ICE_AQ_RC_OK = 0, /* Success */
3351 ice_aqc_opc_get_ver = 0x0001,
3352 ice_aqc_opc_driver_ver = 0x0002,
3353 ice_aqc_opc_q_shutdown = 0x0003,
3354 ice_aqc_opc_get_exp_err = 0x0005,
3357 ice_aqc_opc_req_res = 0x0008,
3358 ice_aqc_opc_release_res = 0x0009,
3361 ice_aqc_opc_list_func_caps = 0x000A,
3362 ice_aqc_opc_list_dev_caps = 0x000B,
3365 ice_aqc_opc_manage_mac_read = 0x0107,
3366 ice_aqc_opc_manage_mac_write = 0x0108,
3369 ice_aqc_opc_clear_pxe_mode = 0x0110,
3371 ice_aqc_opc_config_no_drop_policy = 0x0112,
3374 ice_aqc_opc_get_sw_cfg = 0x0200,
3375 ice_aqc_opc_set_port_params = 0x0203,
3378 ice_aqc_opc_get_res_alloc = 0x0204,
3379 ice_aqc_opc_alloc_res = 0x0208,
3380 ice_aqc_opc_free_res = 0x0209,
3381 ice_aqc_opc_get_allocd_res_desc = 0x020A,
3382 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
3383 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
3386 ice_aqc_opc_add_vsi = 0x0210,
3387 ice_aqc_opc_update_vsi = 0x0211,
3388 ice_aqc_opc_get_vsi_params = 0x0212,
3389 ice_aqc_opc_free_vsi = 0x0213,
3392 ice_aqc_opc_add_update_mir_rule = 0x0260,
3393 ice_aqc_opc_del_mir_rule = 0x0261,
3396 ice_aqc_opc_set_storm_cfg = 0x0280,
3397 ice_aqc_opc_get_storm_cfg = 0x0281,
3400 ice_aqc_opc_add_sw_rules = 0x02A0,
3401 ice_aqc_opc_update_sw_rules = 0x02A1,
3402 ice_aqc_opc_remove_sw_rules = 0x02A2,
3403 ice_aqc_opc_get_sw_rules = 0x02A3,
3404 ice_aqc_opc_clear_pf_cfg = 0x02A4,
3407 ice_aqc_opc_pfc_ignore = 0x0301,
3408 ice_aqc_opc_query_pfc_mode = 0x0302,
3409 ice_aqc_opc_set_pfc_mode = 0x0303,
3410 ice_aqc_opc_set_dcb_params = 0x0306,
3413 ice_aqc_opc_get_dflt_topo = 0x0400,
3414 ice_aqc_opc_add_sched_elems = 0x0401,
3415 ice_aqc_opc_cfg_sched_elems = 0x0403,
3416 ice_aqc_opc_get_sched_elems = 0x0404,
3417 ice_aqc_opc_move_sched_elems = 0x0408,
3418 ice_aqc_opc_suspend_sched_elems = 0x0409,
3419 ice_aqc_opc_resume_sched_elems = 0x040A,
3420 ice_aqc_opc_query_port_ets = 0x040E,
3421 ice_aqc_opc_delete_sched_elems = 0x040F,
3422 ice_aqc_opc_add_rl_profiles = 0x0410,
3423 ice_aqc_opc_query_rl_profiles = 0x0411,
3424 ice_aqc_opc_query_sched_res = 0x0412,
3425 ice_aqc_opc_query_node_to_root = 0x0413,
3426 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
3427 ice_aqc_opc_remove_rl_profiles = 0x0415,
3428 ice_aqc_opc_set_tx_topo = 0x0417,
3429 ice_aqc_opc_get_tx_topo = 0x0418,
3430 ice_aqc_opc_cfg_node_attr = 0x0419,
3431 ice_aqc_opc_query_node_attr = 0x041A,
3434 ice_aqc_opc_get_phy_caps = 0x0600,
3435 ice_aqc_opc_set_phy_cfg = 0x0601,
3436 ice_aqc_opc_set_mac_cfg = 0x0603,
3437 ice_aqc_opc_restart_an = 0x0605,
3438 ice_aqc_opc_get_link_status = 0x0607,
3439 ice_aqc_opc_set_event_mask = 0x0613,
3440 ice_aqc_opc_set_mac_lb = 0x0620,
3441 ice_aqc_opc_get_sensor_reading = 0x0632,
3442 ice_aqc_opc_dnl_get_status = 0x0680,
3443 ice_aqc_opc_dnl_run = 0x0681,
3444 ice_aqc_opc_dnl_call = 0x0682,
3445 ice_aqc_opc_dnl_read_sto = 0x0683,
3446 ice_aqc_opc_dnl_write_sto = 0x0684,
3447 ice_aqc_opc_dnl_set_breakpoints = 0x0686,
3448 ice_aqc_opc_dnl_read_log = 0x0687,
3449 ice_aqc_opc_get_link_topo = 0x06E0,
3450 ice_aqc_opc_read_i2c = 0x06E2,
3451 ice_aqc_opc_write_i2c = 0x06E3,
3452 ice_aqc_opc_read_mdio = 0x06E4,
3453 ice_aqc_opc_write_mdio = 0x06E5,
3454 ice_aqc_opc_set_gpio_by_func = 0x06E6,
3455 ice_aqc_opc_get_gpio_by_func = 0x06E7,
3456 ice_aqc_opc_set_led = 0x06E8,
3457 ice_aqc_opc_set_port_id_led = 0x06E9,
3458 ice_aqc_opc_get_port_options = 0x06EA,
3459 ice_aqc_opc_set_port_option = 0x06EB,
3460 ice_aqc_opc_set_gpio = 0x06EC,
3461 ice_aqc_opc_get_gpio = 0x06ED,
3462 ice_aqc_opc_sff_eeprom = 0x06EE,
3463 ice_aqc_opc_sw_set_gpio = 0x06EF,
3464 ice_aqc_opc_sw_get_gpio = 0x06F0,
3465 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2,
3466 ice_aqc_opc_read_topo_dev_nvm = 0x06F3,
3469 ice_aqc_opc_nvm_read = 0x0701,
3470 ice_aqc_opc_nvm_erase = 0x0702,
3471 ice_aqc_opc_nvm_write = 0x0703,
3472 ice_aqc_opc_nvm_cfg_read = 0x0704,
3473 ice_aqc_opc_nvm_cfg_write = 0x0705,
3474 ice_aqc_opc_nvm_checksum = 0x0706,
3475 ice_aqc_opc_nvm_write_activate = 0x0707,
3476 ice_aqc_opc_nvm_sr_dump = 0x0707,
3477 ice_aqc_opc_nvm_save_factory_settings = 0x0708,
3478 ice_aqc_opc_nvm_update_empr = 0x0709,
3479 ice_aqc_opc_nvm_pkg_data = 0x070A,
3480 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
3481 ice_aqc_opc_nvm_sanitization = 0x070C,
3484 ice_mbx_opc_send_msg_to_pf = 0x0801,
3485 ice_mbx_opc_send_msg_to_vf = 0x0802,
3487 ice_aqc_opc_write_alt_direct = 0x0900,
3488 ice_aqc_opc_write_alt_indirect = 0x0901,
3489 ice_aqc_opc_read_alt_direct = 0x0902,
3490 ice_aqc_opc_read_alt_indirect = 0x0903,
3491 ice_aqc_opc_done_alt_write = 0x0904,
3492 ice_aqc_opc_clear_port_alt_write = 0x0906,
3494 ice_aqc_opc_lldp_get_mib = 0x0A00,
3495 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
3496 ice_aqc_opc_lldp_add_tlv = 0x0A02,
3497 ice_aqc_opc_lldp_update_tlv = 0x0A03,
3498 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
3499 ice_aqc_opc_lldp_stop = 0x0A05,
3500 ice_aqc_opc_lldp_start = 0x0A06,
3501 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
3502 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
3503 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
3504 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
3505 ice_execute_pending_lldp_mib = 0x0A0B,
3508 ice_aqc_opc_set_rss_key = 0x0B02,
3509 ice_aqc_opc_set_rss_lut = 0x0B03,
3510 ice_aqc_opc_get_rss_key = 0x0B04,
3511 ice_aqc_opc_get_rss_lut = 0x0B05,
3513 ice_aqc_opc_neighbour_device_request = 0x0C00,
3516 ice_aqc_opc_add_txqs = 0x0C30,
3517 ice_aqc_opc_dis_txqs = 0x0C31,
3518 ice_aqc_opc_txqs_cleanup = 0x0C31,
3519 ice_aqc_opc_move_recfg_txqs = 0x0C32,
3520 ice_aqc_opc_add_rdma_qset = 0x0C33,
3521 ice_aqc_opc_move_rdma_qset = 0x0C34,
3524 ice_aqc_opc_download_pkg = 0x0C40,
3525 ice_aqc_opc_upload_section = 0x0C41,
3526 ice_aqc_opc_update_pkg = 0x0C42,
3527 ice_aqc_opc_get_pkg_info_list = 0x0C43,
3529 ice_aqc_opc_driver_shared_params = 0x0C90,
3532 ice_aqc_opc_event_lan_overflow = 0x1001,
3535 ice_aqc_opc_debug_dump_internals = 0xFF08,
3538 ice_aqc_opc_set_health_status_config = 0xFF20,
3539 ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
3540 ice_aqc_opc_get_health_status = 0xFF22,
3541 ice_aqc_opc_clear_health_status = 0xFF23,
3544 ice_aqc_opc_fw_logs_config = 0xFF30,
3545 ice_aqc_opc_fw_logs_register = 0xFF31,
3546 ice_aqc_opc_fw_logs_query = 0xFF32,
3547 ice_aqc_opc_fw_logs_event = 0xFF33,
3548 ice_aqc_opc_fw_logs_get = 0xFF34,
3549 ice_aqc_opc_fw_logs_clear = 0xFF35