Lines Matching +full:tx +full:- +full:sync +full:- +full:clock
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 #define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */
53 #define WR_SCF 7 /* Sync Character or (SDCL) Flag. */
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
58 #define WR_CMC 11 /* Clock Mode Control. */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
84 #define BES_TXU 0x40 /* Tx Underrun (EOM). */
86 #define BES_SYNC 0x10 /* Sync. */
88 #define BES_TXE 0x04 /* Tx Empty. */
92 /* Clock Mode Control (WR11). */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
94 #define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */
95 #define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
98 #define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
99 #define CMC_TC_BRG 0x10 /* Tx Clock from BRG */
100 #define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
101 #define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
102 #define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
103 #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
104 #define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
105 #define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
106 #define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
109 #define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */
110 #define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */
114 #define CR_RSTTXI 0x28 /* Reset Tx. Int. */
126 #define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */
130 #define IC_TXU 0x40 /* Tx Underrun IE. */
132 #define IC_SYNC 0x10 /* Sync IE. */
146 #define IDT_TIE 0x02 /* Tx Int. Enable. */
151 #define IP_TIA 0x10 /* Tx. Int. ch. A. */
154 #define IP_TIB 0x02 /* Tx. Int. ch. B. */
177 #define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */
180 #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181 #define MCB2_FM 0xc0 /* DPLL - FM mode. */
182 #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183 #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184 #define MCB2_OFF 0x60 /* DPLL - Disable. */
185 #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186 #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
205 #define MPM_CM64 0xc0 /* X64 Clock Mode. */
206 #define MPM_CM32 0x80 /* X32 Clock Mode. */
207 #define MPM_CM16 0x40 /* X16 Clock Mode. */
208 #define MPM_CM1 0x00 /* X1 Clock Mode. */
209 #define MPM_EXT 0x30 /* External Sync Mode. */
211 #define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
212 #define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
216 #define MPM_SYNC 0x00 /* Sync Mode Enable. */
229 #define RPC_LI 0x02 /* SYNC Character Load Inhibit */