Lines Matching +full:sync +full:- +full:2
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
38 * Channel A control: 2 16
48 #define WR_IV 2 /* Interrupt Vector (shared). */
52 #define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */
53 #define WR_SCF 7 /* Sync Character or (SDCL) Flag. */
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
67 #define RR_IV 2 /* Interrupt Vector. */
86 #define BES_SYNC 0x10 /* Sync. */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
100 #define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
101 #define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
102 #define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
103 #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
104 #define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
105 #define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
106 #define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
132 #define IC_SYNC 0x10 /* Sync IE. */
177 #define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */
179 /* Miscellaneous Control Bits part 2 (WR14). */
180 #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181 #define MCB2_FM 0xc0 /* DPLL - FM mode. */
182 #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183 #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184 #define MCB2_OFF 0x60 /* DPLL - Disable. */
185 #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186 #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
209 #define MPM_EXT 0x30 /* External Sync Mode. */
211 #define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
212 #define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
213 #define MPM_SB2 0x0c /* Async mode: 2 stopbits. */
216 #define MPM_SYNC 0x00 /* Sync Mode Enable. */
229 #define RPC_LI 0x02 /* SYNC Character Load Inhibit */
239 #define SRC_RC2 0x02 /* Residue Code 2. */