Lines Matching +full:reset +full:- +full:mode
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #define WR_IDT 1 /* Interrupt and Data Transfer Mode. */
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
58 #define WR_CMC 11 /* Clock Mode Control. */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
92 /* Clock Mode Control (WR11). */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
100 #define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
101 #define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
102 #define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
103 #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
104 #define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
105 #define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
106 #define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
109 #define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */
110 #define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */
111 #define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */
112 #define CR_RSTIUS 0x38 /* Reset Int. Under Service. */
113 #define CR_RSTERR 0x30 /* Error Reset. */
114 #define CR_RSTTXI 0x28 /* Reset Tx. Int. */
117 #define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */
125 #define EFC_EOM 0x02 /* Auto EOM Reset. */
138 /* Interrupt and Data Transfer Mode (WR1). */
176 #define MCB1_LM 0x02 /* Loop Mode. */
180 #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181 #define MCB2_FM 0xc0 /* DPLL - FM mode. */
182 #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183 #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184 #define MCB2_OFF 0x60 /* DPLL - Disable. */
185 #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186 #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
194 #define MIC_FHR 0xc0 /* Force Hardware Reset. */
195 #define MIC_CRA 0x80 /* Channel Reset A. */
196 #define MIC_CRB 0x40 /* Channel Reset B. */
205 #define MPM_CM64 0xc0 /* X64 Clock Mode. */
206 #define MPM_CM32 0x80 /* X32 Clock Mode. */
207 #define MPM_CM16 0x40 /* X16 Clock Mode. */
208 #define MPM_CM1 0x00 /* X1 Clock Mode. */
209 #define MPM_EXT 0x30 /* External Sync Mode. */
210 #define MPM_SDLC 0x20 /* SDLC mode. */
211 #define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
212 #define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
213 #define MPM_SB2 0x0c /* Async mode: 2 stopbits. */
214 #define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */
215 #define MPM_SB1 0x04 /* Async mode: 1 stopbit. */
216 #define MPM_SYNC 0x00 /* Sync Mode Enable. */
217 #define MPM_EVEN 0x02 /* Async mode: even parity. */
218 #define MPM_PE 0x01 /* Async mode: parity enable. */
226 #define RPC_EHM 0x10 /* Enter Hunt Mode. */
228 #define RPC_ASM 0x04 /* Address Search Mode. */