Lines Matching +full:control +full:- +full:channel
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * Channel B control: 0 0
37 * Channel B data: 1 1
38 * Channel A control: 2 16
39 * Channel A data: 3 17
49 #define WR_RPC 3 /* Receive Parameters and Control. */
51 #define WR_TPC 5 /* Transmit Parameters and Control. */
54 #define WR_EFC 7 /* Extended Feature and FIFO Control. */
56 #define WR_MIC 9 /* Master Interrupt Control (shared). */
57 #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
58 #define WR_CMC 11 /* Clock Mode Control. */
61 #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
62 #define WR_IC 15 /* Interrupt Control. */
70 #define RR_TPC 5 /* Transmit Parameters and Control. */
74 #define RR_RPC 9 /* Receive Parameters and Control. */
76 #define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */
79 #define RR_EFC 14 /* Extended Feature and FIFO Control. */
80 #define RR_IC 15 /* Interrupt Control. */
92 /* Clock Mode Control (WR11). */
93 #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
96 #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97 #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
100 #define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
101 #define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
102 #define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
103 #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
104 #define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
105 #define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
106 #define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
119 /* Extended Feature and FIFO Control (WR7 prime). */
128 /* Interrupt Control (WR15). */
167 /* Miscellaneous Control Bits part 1 (WR10). */
179 /* Miscellaneous Control Bits part 2 (WR14). */
180 #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181 #define MCB2_FM 0xc0 /* DPLL - FM mode. */
182 #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183 #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184 #define MCB2_OFF 0x60 /* DPLL - Disable. */
185 #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186 #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
193 /* Master Interrupt Control (WR9). */
195 #define MIC_CRA 0x80 /* Channel Reset A. */
196 #define MIC_CRB 0x40 /* Channel Reset B. */
211 #define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
212 #define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
220 /* Receive Parameters and Control (WR3). */
242 /* Transmit Parameter and Control (WR5). */