Lines Matching +full:20 +full:w

38 #define	com_data	0	/* data register (R/W) */
41 #define	com_ier		1	/* interrupt enable register (W) */
53 #define	IER_BITS	"\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC\5RXTMOUT"
67 #define	IIR_BITS	"\20\1NOPEND\2TXRDY\3RXRDY"
69 #define	com_lcr		3	/* line control register (R/W) */
70 #define	com_cfcr	com_lcr	/* character format control register (R/W) */
99 #define	com_mcr		4	/* modem control register (R/W) */
109 #define	MCR_BITS	"\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE"
111 #define	com_lsr		5	/* line status register (R/W) */
125 #define	LSR_BITS	"\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO"
127 #define	com_msr		6	/* modem status register (R/W) */
138 #define	MSR_BITS	"\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD"
141 #define	com_dll		0	/* divisor latch low (R/W) */
143 #define	com_dlm		1	/* divisor latch high (R/W) */
149 #define	com_scr		7	/* scratch register (R/W) */
152 #define	com_fcr		2	/* FIFO control register (W) */
172 #define	FCR_BITS	"\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA"
176 #define	com_efr		2	/* enhanced features register (R/W) */
184 #define	com_xon1	4	/* XON 1 character (R/W) */
185 #define	com_xon2	5	/* XON 2 character (R/W) */
186 #define	com_xoff1	6	/* XOFF 1 character (R/W) */
187 #define	com_xoff2	7	/* XOFF 2 character (R/W) */
196 #define	com_asr		1	/* additional status register (R[0-7]/W[0-1]) */
198 /* 16950 register #3.  R/W access enabled by ACR[7]. */
211 #define	com_icr		5	/* index control register (R/W) */
219 #define	com_spr		com_scr	/* scratch pad (and index) register (R/W) */
227 #define	com_acr		0	/* additional control register (R/W) */
233 #define	com_cpr		1	/* clock prescaler register (R/W) */
234 #define	com_tcr		2	/* times clock register (R/W) */
235 #define	com_ttl		4	/* transmitter trigger level (R/W) */
236 #define	com_rtl		5	/* receiver trigger level (R/W) */