Lines Matching +full:on +full:- +full:the +full:- +full:fly

1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
4  * Copyright (c) 1993 The Regents of the University of California.
8  * modification, are permitted provided that the following conditions
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. Neither the name of the University nor the names of its contributors
19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35  * Register definitions for the Intel 8253 Programmable Interval Timer.
37  * This chip has three independent 16-bit down counters that can be
38  * read on the fly.  There are three mode registers and three countdown
39  * registers.  The countdown registers are addressed directly, via the
40  * first three I/O ports.  The three mode registers are accessed via
41  * the fourth I/O port, with two bits in the mode byte indicating the
44  * To write a value into the countdown register, the mode register
45  * is first programmed with a command indicating the which byte of
46  * the two byte register is to be modified.  The three possibilities
50  * To read the current value ("on the fly") from the countdown register,
51  * you write a "latch" command into the mode register, then read the stable
52  * value from the corresponding I/O port.  For example, you write
53  * TMR_MR_LATCH into the corresponding mode register.  Presumably,
54  * after doing this, a write operation to the I/O port would result
55  * in undefined behavior (but hopefully not fry the chip).
69 #define		TIMER_INTTC	0x00	/* mode 0, intr on terminal cnt */