Lines Matching +full:double +full:- +full:channel
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 #define CD180_GICR 0x41 /* Global Interrupting Channel Register */
40 #define CD180_CAR 0x64 /* Channel Access Register */
49 /* Channel Registers */
50 #define CD180_CCR 0x01 /* Channel Command Register */
52 #define CD180_COR1 0x03 /* Channel Option Register 1 */
53 #define CD180_COR2 0x04 /* Channel Option Register 1 */
54 #define CD180_COR3 0x05 /* Channel Option Register 1 */
55 #define CD180_CCSR 0x06 /* Channel Control STatus Register */
79 /* Global Interrupt Channel Register */
80 #define GICR_CHAN 0x1C /* Channel Number Mask */
81 #define GICR_LSH 2 /* Channel Number Shift */
83 /* Channel Address Register */
84 #define CAR_CHAN 0x07 /* Channel Number Mask */
99 /* Channel Command Register */
100 #define CCR_ResetChan 0x80 /* Reset Channel */
102 #define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
103 #define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
104 #define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
124 /* Channel Option Register 1 */
141 /* Channel Option Register 2 */
143 #define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */
151 /* Channel Option Register 3 */
152 #define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */
153 #define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */
154 #define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
156 #define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */
158 /* Channel Control Status Register */
167 #define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */
168 #define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */
169 #define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */
170 #define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */
173 #define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */
174 #define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */
175 #define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */