55 	PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());  in intel_switch_in()
57 	return 0;  in intel_switch_in()
66 	PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,  in intel_switch_out()
72 	return 0;  in intel_switch_out()
85 	PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);  in pmc_intel_initialize()
89 	error = 0;  in pmc_intel_initialize()
90 	verov = 0;  in pmc_intel_initialize()
98 	switch (cpu_id & 0xF00) {  in pmc_intel_initialize()
99 	case 0x600:  in pmc_intel_initialize()
101 		case 0xE:  in pmc_intel_initialize()
104 		case 0xF:  in pmc_intel_initialize()
106 			if (stepping == 0x7) {  in pmc_intel_initialize()
114 		case 0x17:  in pmc_intel_initialize()
118 		case 0x1A:  in pmc_intel_initialize()
119 		case 0x1E:	/*  in pmc_intel_initialize()
123 		case 0x1F:	/*  in pmc_intel_initialize()
130 		case 0x2E:  in pmc_intel_initialize()
134 		case 0x25:	/* Per Intel document 253669-033US 12/2009. */  in pmc_intel_initialize()
135 		case 0x2C:	/* Per Intel document 253669-033US 12/2009. */  in pmc_intel_initialize()
139 		case 0x2F:	/* Westmere-EX, seen in wild */  in pmc_intel_initialize()
143 		case 0x2A:	/* Per Intel document 253669-039US 05/2011. */  in pmc_intel_initialize()
147 		case 0x2D:	/* Per Intel document 253669-044US 08/2012. */  in pmc_intel_initialize()
151 		case 0x3A:	/* Per Intel document 253669-043US 05/2012. */  in pmc_intel_initialize()
155 		case 0x3E:	/* Per Intel document 325462-045US 01/2013. */  in pmc_intel_initialize()
159 		case 0x3D:  in pmc_intel_initialize()
160 		case 0x47:  in pmc_intel_initialize()
164 		case 0x4f:  in pmc_intel_initialize()
165 		case 0x56:  in pmc_intel_initialize()
169 		case 0x3C:	/* Per Intel document 325462-045US 01/2013. */  in pmc_intel_initialize()
170 		case 0x45:	/* Per Intel document 325462-045US 09/2014. */  in pmc_intel_initialize()
174 		case 0x3F:	/* Per Intel document 325462-045US 09/2014. */  in pmc_intel_initialize()
175 		case 0x46:	/* Per Intel document 325462-045US 09/2014. */  in pmc_intel_initialize()
181 		case 0x4e:  in pmc_intel_initialize()
182 		case 0x5e:  in pmc_intel_initialize()
184 		case 0x8E:	/* Per Intel document 325462-063US July 2017. */  in pmc_intel_initialize()
185 		case 0x9E:	/* Per Intel document 325462-063US July 2017. */  in pmc_intel_initialize()
187 		case 0xA5:  in pmc_intel_initialize()
188 		case 0xA6:  in pmc_intel_initialize()
192 		case 0x55:	/* SDM rev 63 */  in pmc_intel_initialize()
197 		case 0x7D:  in pmc_intel_initialize()
198 		case 0x7E:  in pmc_intel_initialize()
200 		case 0x8C:  in pmc_intel_initialize()
201 		case 0x8D:  in pmc_intel_initialize()
203 		case 0xA7:  in pmc_intel_initialize()
207 		case 0x6A:  in pmc_intel_initialize()
208 		case 0x6C:  in pmc_intel_initialize()
212 		case 0x97:  in pmc_intel_initialize()
213 		case 0x9A:  in pmc_intel_initialize()
217 		case 0x1C:	/* Per Intel document 320047-002. */  in pmc_intel_initialize()
218 		case 0x26:  in pmc_intel_initialize()
219 		case 0x27:  in pmc_intel_initialize()
220 		case 0x35:  in pmc_intel_initialize()
221 		case 0x36:  in pmc_intel_initialize()
225 		case 0x37:  in pmc_intel_initialize()
226 		case 0x4A:  in pmc_intel_initialize()
227 		case 0x4D:      /* Per Intel document 330061-001 01/2014. */  in pmc_intel_initialize()
228 		case 0x5A:  in pmc_intel_initialize()
229 		case 0x5D:  in pmc_intel_initialize()
233 		case 0x5C:	/* Per Intel document 325462-071US 10/2019. */  in pmc_intel_initialize()
234 		case 0x5F:  in pmc_intel_initialize()
238 		case 0x7A:  in pmc_intel_initialize()
242 		case 0x86:  in pmc_intel_initialize()
243 		case 0x96:  in pmc_intel_initialize()