Lines Matching +full:0 +full:x4090
32 #define DBG 0
35 int hpt_iop_dbg_level = 0;
36 #define KdPrint(x) do { if (hpt_iop_dbg_level) printf x; } while (0)
44 #define HPT_SRB_MAX_QUEUE_SIZE 0x100
47 #define HPT_SRB_FLAG_HIGH_MEM_ACESS 0x1
48 #define HPT_SRB_MAX_SIZE ((sizeof(struct hpt_iop_srb) + 0x1f) & ~0x1f)
50 #define offsetof(TYPE, MEM) ((size_t)&((TYPE*)0)->MEM)
57 #define HPT_IOCTL_MAGIC 0xA1B2C3D4
58 #define HPT_IOCTL_MAGIC32 0x1A2B3C4D
77 #define IOPMU_QUEUE_EMPTY 0xffffffff
78 #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000
79 #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000
80 #define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000
81 #define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000
82 #define IOPMU_MAX_MEM_SUPPORT_MASK_64G 0xfffffff000000000ull
83 #define IOPMU_MAX_MEM_SUPPORT_MASK_32G 0xfffffff800000000ull
89 #define IOPMU_OUTBOUND_INT_PCI 0x10
95 #define IOPMU_INBOUND_INT_POSTQUEUE 0x10
111 u_int32_t reserved[0x20400 / 4];
118 #define CL_POINTER_TOGGLE 0x00004000
119 #define CPU_TO_F0_DRBL_MSG_A_BIT 0x02000000
123 u_int32_t reserved[0x4000 / 4];
126 u_int32_t inbound_base; /* 0x4000 : 0 */
128 u_int32_t reserved2[(0x18 - 8)/ 4];
129 u_int32_t inbound_write_ptr; /* 0x18 */
130 u_int32_t inbound_read_ptr; /* 0x1c */
131 u_int32_t reserved3[(0x2c - 0x20) / 4];
132 u_int32_t inbound_conf_ctl; /* 0x2c */
133 u_int32_t reserved4[(0x50 - 0x30) / 4];
134 u_int32_t outbound_base; /* 0x50 */
135 u_int32_t outbound_base_high; /* 0x54 */
136 u_int32_t outbound_shadow_base; /* 0x58 */
137 u_int32_t outbound_shadow_base_high; /* 0x5c */
138 u_int32_t reserved5[(0x68 - 0x60) / 4];
139 u_int32_t outbound_write; /* 0x68 */
140 u_int32_t reserved6[(0x70 - 0x6c) / 4];
141 u_int32_t outbound_read; /* 0x70 */
142 u_int32_t reserved7[(0x88 - 0x74) / 4];
143 u_int32_t isr_cause; /* 0x88 */
144 u_int32_t isr_enable; /* 0x8c */
146 u_int32_t reserved8[(0x10200 - 0x4090) / 4];
149 u_int32_t main_int_cuase; /* 0x10200: 0 */
152 u_int32_t pcie_f0_int_enable; /* 0xc */
153 u_int32_t pcie_f1_int_enable; /* 0x10 */
154 u_int32_t pcie_f2_int_enable; /* 0x14 */
155 u_int32_t pcie_f3_int_enable; /* 0x18 */
157 u_int32_t reserved9[(0x10400 - 0x1021c) / 4];
160 u_int32_t f0_to_cpu_msg_a; /* 0x10400: 0 */
161 u_int32_t reserved10[(0x20 - 4) / 4];
162 u_int32_t cpu_to_f0_msg_a; /* 0x20 */
163 u_int32_t reserved11[(0x80 - 0x24) / 4];
164 u_int32_t f0_doorbell; /* 0x80 */
165 u_int32_t f0_doorbell_enable; /* 0x84 */
180 #define MVIOP_IOCTLCFG_SIZE 0x800
181 #define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full))
184 #define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32 0xffffffff
201 #define MVFREYIOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000
205 IOPMU_INBOUND_MSG0_NOP = 0,
212 IOPMU_INBOUND_MSG0_MAX = 0xff,
214 IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
215 IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
216 IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
217 IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
218 IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
219 IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
227 #define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */
230 IOP_REQUEST_TYPE_GET_CONFIG = 0,
239 IOP_RESULT_PENDING = 0,
334 #define HPT_CTL_CODE_BSD_TO_IOP(x) ((x)-0xff00)
428 INTEL_BASED_IOP = 0,
431 UNKNOWN_BASED_IOP = 0xf
471 #define HPT_DO_IOCONTROL _IOW('H', 0, struct hpt_iop_ioctl_param)