Lines Matching full:processing

112  * Processing Unit Registers (offset from BASEREG0)
114 #define	HIFN_0_PUDATA		0x00	/* Processing Unit Data */
115 #define	HIFN_0_PUCTRL		0x04	/* Processing Unit Control */
116 #define	HIFN_0_PUISR		0x08	/* Processing Unit Interrupt Status */
117 #define	HIFN_0_PUCNFG		0x0c	/* Processing Unit Configuration */
118 #define	HIFN_0_PUIER		0x10	/* Processing Unit Interrupt Enable */
119 #define	HIFN_0_PUSTAT		0x14	/* Processing Unit Status/Chip ID */
122 #define	HIFN_0_PUCTRL2		0x28	/* Processing Unit Control (2nd map) */
127 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
132 #define	HIFN_PUCTRL_RESET	0x0001	/* Reset processing unit */
134 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
146 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
171 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
183 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */