Lines Matching +full:0 +full:x3ffff
53 #define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */
55 #define HIFN_TRDY_TIMEOUT 0x40
56 #define HIFN_RETRY_TIMEOUT 0x41
62 #define PCI_VENDOR_HIFN 0x13a3 /* Hifn */
63 #define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */
64 #define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */
65 #define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */
66 #define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */
67 #define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */
68 #define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */
70 #define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */
71 #define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */
73 #define PCI_VENDOR_NETSEC 0x1660 /* NetSec */
74 #define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */
102 #define HIFN_D_LENGTH 0x0000ffff /* length bit mask */
103 #define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */
104 #define HIFN_D_DESTOVER 0x04000000 /* destination overflow */
105 #define HIFN_D_OVER 0x08000000 /* overflow */
106 #define HIFN_D_LAST 0x20000000 /* last descriptor in chain */
107 #define HIFN_D_JUMP 0x40000000 /* jump descriptor */
108 #define HIFN_D_VALID 0x80000000 /* valid bit */
114 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
115 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
116 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
117 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
118 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
119 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
120 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
121 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
122 #define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */
123 #define HIFN_0_MUTE1 0x80
124 #define HIFN_0_MUTE2 0x90
125 #define HIFN_0_SPACESIZE 0x100 /* Register space size */
128 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
129 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
130 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
131 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
132 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
135 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
136 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
137 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
138 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
139 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
140 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
141 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
142 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
143 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
144 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
147 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
148 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
149 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
150 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
151 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
152 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
153 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
154 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
155 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
156 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
157 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
158 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
159 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
160 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
161 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
162 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
163 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
164 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
165 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
166 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
167 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
168 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
169 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
172 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
173 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
174 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
175 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
176 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
177 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
178 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
179 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
180 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
181 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
184 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
185 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
186 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
187 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
188 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
189 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
190 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
191 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
192 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
193 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
194 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
195 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
196 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
197 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
198 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
199 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
200 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
203 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
204 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
207 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */
212 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
213 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
214 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
215 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
216 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
217 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
218 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
219 #define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */
220 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
221 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
222 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
223 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
224 #define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */
225 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
226 #define HIFN_1_REVID 0x98 /* Revision ID */
228 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
229 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
230 #define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */
231 #define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */
232 #define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */
233 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
234 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
235 #define HIFN_1_RNG_DATA 0x318 /* RNG data */
236 #define HIFN_1_PUB_MODE 0x320 /* PK mode */
237 #define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */
238 #define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */
239 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
240 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
243 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
244 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
245 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
246 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
247 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
248 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
249 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
250 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
251 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
252 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
253 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
254 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
255 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
256 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
257 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
258 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
259 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
260 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
261 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
262 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
263 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
264 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
265 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
266 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
267 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
268 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
269 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
270 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
271 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
272 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
273 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
274 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
275 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
276 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
277 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
278 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
279 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
280 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
283 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
284 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
285 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
286 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
287 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
288 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
289 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
290 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
291 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
292 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
293 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
294 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
295 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
296 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
297 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
298 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
299 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
300 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
301 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
302 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
303 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
304 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
307 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
308 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
309 #define HIFN_DMACNFG_UNLOCK 0x00000800
310 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
311 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
312 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
313 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
314 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
324 #define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0
327 #define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */
330 #define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */
331 #define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */
332 #define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */
335 #define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */
336 #define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */
339 #define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */
340 #define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */
341 #define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */
342 #define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */
343 #define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */
344 #define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */
345 #define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */
346 #define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */
347 #define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */
350 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
353 #define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */
354 #define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */
355 #define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */
356 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
357 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
358 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
359 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
360 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
361 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
362 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
363 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
364 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
365 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
366 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
367 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
368 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */
369 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */
372 #define HIFN_PUBOPLEN_MODLEN 0x0000007f
373 #define HIFN_PUBOPLEN_EXPLEN 0x0003ff80
374 #define HIFN_PUBOPLEN_REDLEN 0x003c0000
377 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
378 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
379 #define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */
380 #define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */
381 #define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */
382 #define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */
383 #define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */
386 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
389 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
395 #define HIFN_UNLOCK_SECRET1 0xf4
396 #define HIFN_UNLOCK_SECRET2 0xfc
409 #define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */
410 #define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */
412 #define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */
413 #define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */
415 #define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */
416 #define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */
418 #define HIFN_PLL_ND_2 0x00000000 /* 2x */
419 #define HIFN_PLL_ND_4 0x00000800 /* 4x */
420 #define HIFN_PLL_ND_6 0x00001000 /* 6x */
421 #define HIFN_PLL_ND_8 0x00001800 /* 8x */
422 #define HIFN_PLL_ND_10 0x00002000 /* 10x */
423 #define HIFN_PLL_ND_12 0x00002800 /* 12x */
425 #define HIFN_PLL_IS 0x00010000 /* charge pump current select */
436 #define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */
455 #define HIFN_BASE_CMD_MAC 0x0400
456 #define HIFN_BASE_CMD_CRYPT 0x0800
457 #define HIFN_BASE_CMD_DECODE 0x2000
458 #define HIFN_BASE_CMD_SRCLEN_M 0xc000
460 #define HIFN_BASE_CMD_DSTLEN_M 0x3000
462 #define HIFN_BASE_CMD_LENMASK_HI 0x30000
463 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
475 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
476 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
477 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
478 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
479 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
480 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
481 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
482 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
483 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
484 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
485 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
486 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
487 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
489 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
492 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
493 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
494 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
495 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
507 #define HIFN_MAC_CMD_ALG_MASK 0x0001
508 #define HIFN_MAC_CMD_ALG_SHA1 0x0000
509 #define HIFN_MAC_CMD_ALG_MD5 0x0001
510 #define HIFN_MAC_CMD_MODE_MASK 0x000c
511 #define HIFN_MAC_CMD_MODE_HMAC 0x0000
512 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
513 #define HIFN_MAC_CMD_MODE_HASH 0x0008
514 #define HIFN_MAC_CMD_MODE_FULL 0x0004
515 #define HIFN_MAC_CMD_TRUNC 0x0010
516 #define HIFN_MAC_CMD_RESULT 0x0020
517 #define HIFN_MAC_CMD_APPEND 0x0040
518 #define HIFN_MAC_CMD_SRCLEN_M 0xc000
525 #define HIFN_MAC_CMD_POS_IPSEC 0x0200
526 #define HIFN_MAC_CMD_NEW_KEY 0x0800
533 #define HIFN_POLL_FREQUENCY 0x1
537 #define HIFN_POLL_SCALAR 0x0
540 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
541 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */