95 	WR1(sc, HDMI_IH_I2CMPHY_STAT0,  in dwc_hdmi_phy_i2c_write()
97 	WR1(sc, HDMI_PHY_I2CM_ADDRESS_ADDR, addr);  in dwc_hdmi_phy_i2c_write()
98 	WR1(sc, HDMI_PHY_I2CM_DATAO_1_ADDR, ((data >> 8) & 0xff));  in dwc_hdmi_phy_i2c_write()
99 	WR1(sc, HDMI_PHY_I2CM_DATAO_0_ADDR, ((data >> 0) & 0xff));  in dwc_hdmi_phy_i2c_write()
100 	WR1(sc, HDMI_PHY_I2CM_OPERATION_ADDR, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);  in dwc_hdmi_phy_i2c_write()
107 	WR1(sc, HDMI_IH_MUTE_FC_STAT2, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK);  in dwc_hdmi_disable_overflow_interrupts()
108 	WR1(sc, HDMI_FC_MASK2,  in dwc_hdmi_disable_overflow_interrupts()
144 	WR1(sc, HDMI_FC_INVIDCONF, inv_val);  in dwc_hdmi_av_composer()
147 	WR1(sc, HDMI_FC_INHACTV1, sc->sc_mode.hdisplay >> 8);  in dwc_hdmi_av_composer()
148 	WR1(sc, HDMI_FC_INHACTV0, sc->sc_mode.hdisplay);  in dwc_hdmi_av_composer()
151 	WR1(sc, HDMI_FC_INVACTV1, sc->sc_mode.vdisplay >> 8);  in dwc_hdmi_av_composer()
152 	WR1(sc, HDMI_FC_INVACTV0, sc->sc_mode.vdisplay);  in dwc_hdmi_av_composer()
156 	WR1(sc, HDMI_FC_INHBLANK1, hblank >> 8);  in dwc_hdmi_av_composer()
157 	WR1(sc, HDMI_FC_INHBLANK0, hblank);  in dwc_hdmi_av_composer()
161 	WR1(sc, HDMI_FC_INVBLANK, vblank);  in dwc_hdmi_av_composer()
165 	WR1(sc, HDMI_FC_HSYNCINDELAY1, hfp >> 8);  in dwc_hdmi_av_composer()
166 	WR1(sc, HDMI_FC_HSYNCINDELAY0, hfp);  in dwc_hdmi_av_composer()
170 	WR1(sc, HDMI_FC_VSYNCINDELAY, vfp);  in dwc_hdmi_av_composer()
174 	WR1(sc, HDMI_FC_HSYNCINWIDTH1, hsync_len >> 8);  in dwc_hdmi_av_composer()
175 	WR1(sc, HDMI_FC_HSYNCINWIDTH0, hsync_len);  in dwc_hdmi_av_composer()
178 	WR1(sc, HDMI_FC_VSYNCINWIDTH, (sc->sc_mode.vsync_end - sc->sc_mode.vsync_start));  in dwc_hdmi_av_composer()
189 	WR1(sc, HDMI_PHY_CONF0, reg);  in dwc_hdmi_phy_enable_power()
200 	WR1(sc, HDMI_PHY_CONF0, reg);  in dwc_hdmi_phy_enable_tmds()
211 	WR1(sc, HDMI_PHY_CONF0, reg);  in dwc_hdmi_phy_gen2_pddq()
222 	WR1(sc, HDMI_PHY_CONF0, reg);  in dwc_hdmi_phy_gen2_txpwron()
233 	WR1(sc, HDMI_PHY_CONF0, reg);  in dwc_hdmi_phy_sel_data_en_pol()
244 	WR1(sc, HDMI_PHY_CONF0, reg);  in dwc_hdmi_phy_sel_interface_control()
256 	WR1(sc, HDMI_PHY_TST0, val);  in dwc_hdmi_phy_test_clear()
266 	WR1(sc, HDMI_MC_SWRSTZ, (uint8_t)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ);  in dwc_hdmi_clear_overflow()
271 		WR1(sc, HDMI_FC_INVIDCONF, val);  in dwc_hdmi_clear_overflow()
280 	WR1(sc, HDMI_MC_FLOWCTRL, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);  in dwc_hdmi_phy_configure()
289 	WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT);  in dwc_hdmi_phy_configure()
290 	WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_ASSERT);  in dwc_hdmi_phy_configure()
292 	WR1(sc, HDMI_MC_HEACPHY_RST, HDMI_MC_HEACPHY_RST_ASSERT);  in dwc_hdmi_phy_configure()
295 	WR1(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);  in dwc_hdmi_phy_configure()
411 	WR1(sc, HDMI_FC_CTRLDUR, 12);  in dwc_hdmi_enable_video_path()
412 	WR1(sc, HDMI_FC_EXCTRLDUR, 32);  in dwc_hdmi_enable_video_path()
413 	WR1(sc, HDMI_FC_EXCTRLSPAC, 1);  in dwc_hdmi_enable_video_path()
419 	WR1(sc, HDMI_FC_CH0PREAM, 0x0B);  in dwc_hdmi_enable_video_path()
420 	WR1(sc, HDMI_FC_CH1PREAM, 0x16);  in dwc_hdmi_enable_video_path()
421 	WR1(sc, HDMI_FC_CH2PREAM, 0x21);  in dwc_hdmi_enable_video_path()
429 	WR1(sc, HDMI_MC_CLKDIS, clkdis);  in dwc_hdmi_enable_video_path()
432 	WR1(sc, HDMI_MC_CLKDIS, clkdis);  in dwc_hdmi_enable_video_path()
463 	WR1(sc, HDMI_AUD_N1, (n >> 0) & 0xff);  in dwc_hdmi_configure_audio()
464 	WR1(sc, HDMI_AUD_N2, (n >> 8) & 0xff);  in dwc_hdmi_configure_audio()
465 	WR1(sc, HDMI_AUD_N3, (n >> 16) & 0xff);  in dwc_hdmi_configure_audio()
469 	WR1(sc, HDMI_AUD_CTS3, val);  in dwc_hdmi_configure_audio()
476 	WR1(sc, HDMI_AUD_CONF0, val);  in dwc_hdmi_configure_audio()
483 	WR1(sc, HDMI_AUD_CONF1, val);  in dwc_hdmi_configure_audio()
485 	WR1(sc, HDMI_AUD_INPUTCLKFS, HDMI_AUD_INPUTCLKFS_64);  in dwc_hdmi_configure_audio()
487 	WR1(sc, HDMI_FC_AUDICONF0, 1 << 4);	/* CC=1 */  in dwc_hdmi_configure_audio()
488 	WR1(sc, HDMI_FC_AUDICONF1, 0);  in dwc_hdmi_configure_audio()
489 	WR1(sc, HDMI_FC_AUDICONF2, 0);		/* CA=0 */  in dwc_hdmi_configure_audio()
490 	WR1(sc, HDMI_FC_AUDICONF3, 0);  in dwc_hdmi_configure_audio()
491 	WR1(sc, HDMI_FC_AUDSV, 0xee);		/* channels valid */  in dwc_hdmi_configure_audio()
496 	WR1(sc, HDMI_MC_CLKDIS, val);  in dwc_hdmi_configure_audio()
513 	WR1(sc, HDMI_VP_PR_CD, val);  in dwc_hdmi_video_packetize()
518 	WR1(sc, HDMI_VP_STUFF, val);  in dwc_hdmi_video_packetize()
525 	WR1(sc, HDMI_VP_CONF, val);  in dwc_hdmi_video_packetize()
530 	WR1(sc, HDMI_VP_STUFF, val);  in dwc_hdmi_video_packetize()
532 	WR1(sc, HDMI_VP_REMAP, remap_size);  in dwc_hdmi_video_packetize()
542 		WR1(sc, HDMI_VP_CONF, val);  in dwc_hdmi_video_packetize()
551 		WR1(sc, HDMI_VP_CONF, val);  in dwc_hdmi_video_packetize()
560 		WR1(sc, HDMI_VP_CONF, val);  in dwc_hdmi_video_packetize()
570 	WR1(sc, HDMI_VP_STUFF, val);  in dwc_hdmi_video_packetize()
575 	WR1(sc, HDMI_VP_CONF, val);  in dwc_hdmi_video_packetize()
588 	WR1(sc, HDMI_TX_INVID0, val);  in dwc_hdmi_video_sample()
594 	WR1(sc, HDMI_TX_INSTUFFING, val);  in dwc_hdmi_video_sample()
595 	WR1(sc, HDMI_TX_GYDATA0, 0x0);  in dwc_hdmi_video_sample()
596 	WR1(sc, HDMI_TX_GYDATA1, 0x0);  in dwc_hdmi_video_sample()
597 	WR1(sc, HDMI_TX_RCRDATA0, 0x0);  in dwc_hdmi_video_sample()
598 	WR1(sc, HDMI_TX_RCRDATA1, 0x0);  in dwc_hdmi_video_sample()
599 	WR1(sc, HDMI_TX_BCBDATA0, 0x0);  in dwc_hdmi_video_sample()
600 	WR1(sc, HDMI_TX_BCBDATA1, 0x0);  in dwc_hdmi_video_sample()
614 	WR1(sc, HDMI_A_HDCPCFG0, val);  in dwc_hdmi_tx_hdcp_config()
620 	WR1(sc, HDMI_A_VIDPOLCFG, val);  in dwc_hdmi_tx_hdcp_config()
626 	WR1(sc, HDMI_A_HDCPCFG1, val);  in dwc_hdmi_tx_hdcp_config()
741 	WR1(sc, HDMI_PHY_POL0, HDMI_PHY_POL0_HPD);  in dwc_hdmi_init()
742 	WR1(sc, HDMI_IH_PHY_STAT0, HDMI_IH_PHY_STAT0_HPD);  in dwc_hdmi_init()