Lines Matching refs:HDMI_PHY_CONF0
186 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_enable_power()
189 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_enable_power()
197 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_enable_tmds()
200 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_enable_tmds()
208 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_gen2_pddq()
211 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_gen2_pddq()
219 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_gen2_txpwron()
222 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_gen2_txpwron()
230 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_sel_data_en_pol()
233 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_sel_data_en_pol()
241 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_sel_interface_control()
244 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_sel_interface_control()