Lines Matching full:sc
73 dwc_hdmi_phy_wait_i2c_done(struct dwc_hdmi_softc *sc, int msec) in dwc_hdmi_phy_wait_i2c_done() argument
77 val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) & in dwc_hdmi_phy_wait_i2c_done()
84 val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) & in dwc_hdmi_phy_wait_i2c_done()
90 dwc_hdmi_phy_i2c_write(struct dwc_hdmi_softc *sc, unsigned short data, in dwc_hdmi_phy_i2c_write() argument
95 WR1(sc, HDMI_IH_I2CMPHY_STAT0, in dwc_hdmi_phy_i2c_write()
97 WR1(sc, HDMI_PHY_I2CM_ADDRESS_ADDR, addr); in dwc_hdmi_phy_i2c_write()
98 WR1(sc, HDMI_PHY_I2CM_DATAO_1_ADDR, ((data >> 8) & 0xff)); in dwc_hdmi_phy_i2c_write()
99 WR1(sc, HDMI_PHY_I2CM_DATAO_0_ADDR, ((data >> 0) & 0xff)); in dwc_hdmi_phy_i2c_write()
100 WR1(sc, HDMI_PHY_I2CM_OPERATION_ADDR, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE); in dwc_hdmi_phy_i2c_write()
101 dwc_hdmi_phy_wait_i2c_done(sc, 1000); in dwc_hdmi_phy_i2c_write()
105 dwc_hdmi_disable_overflow_interrupts(struct dwc_hdmi_softc *sc) in dwc_hdmi_disable_overflow_interrupts() argument
107 WR1(sc, HDMI_IH_MUTE_FC_STAT2, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK); in dwc_hdmi_disable_overflow_interrupts()
108 WR1(sc, HDMI_FC_MASK2, in dwc_hdmi_disable_overflow_interrupts()
113 dwc_hdmi_av_composer(struct dwc_hdmi_softc *sc) in dwc_hdmi_av_composer() argument
120 inv_val = ((sc->sc_mode.flags & VID_PVSYNC) ? in dwc_hdmi_av_composer()
124 inv_val |= ((sc->sc_mode.flags & VID_PHSYNC) ? in dwc_hdmi_av_composer()
130 inv_val |= ((sc->sc_mode.flags & VID_INTERLACE) ? in dwc_hdmi_av_composer()
134 inv_val |= ((sc->sc_mode.flags & VID_INTERLACE) ? in dwc_hdmi_av_composer()
139 is_dvi = sc->sc_has_audio == 0; in dwc_hdmi_av_composer()
144 WR1(sc, HDMI_FC_INVIDCONF, inv_val); in dwc_hdmi_av_composer()
147 WR1(sc, HDMI_FC_INHACTV1, sc->sc_mode.hdisplay >> 8); in dwc_hdmi_av_composer()
148 WR1(sc, HDMI_FC_INHACTV0, sc->sc_mode.hdisplay); in dwc_hdmi_av_composer()
151 WR1(sc, HDMI_FC_INVACTV1, sc->sc_mode.vdisplay >> 8); in dwc_hdmi_av_composer()
152 WR1(sc, HDMI_FC_INVACTV0, sc->sc_mode.vdisplay); in dwc_hdmi_av_composer()
155 hblank = sc->sc_mode.htotal - sc->sc_mode.hdisplay; in dwc_hdmi_av_composer()
156 WR1(sc, HDMI_FC_INHBLANK1, hblank >> 8); in dwc_hdmi_av_composer()
157 WR1(sc, HDMI_FC_INHBLANK0, hblank); in dwc_hdmi_av_composer()
160 vblank = sc->sc_mode.vtotal - sc->sc_mode.vdisplay; in dwc_hdmi_av_composer()
161 WR1(sc, HDMI_FC_INVBLANK, vblank); in dwc_hdmi_av_composer()
164 hfp = sc->sc_mode.hsync_start - sc->sc_mode.hdisplay; in dwc_hdmi_av_composer()
165 WR1(sc, HDMI_FC_HSYNCINDELAY1, hfp >> 8); in dwc_hdmi_av_composer()
166 WR1(sc, HDMI_FC_HSYNCINDELAY0, hfp); in dwc_hdmi_av_composer()
169 vfp = sc->sc_mode.vsync_start - sc->sc_mode.vdisplay; in dwc_hdmi_av_composer()
170 WR1(sc, HDMI_FC_VSYNCINDELAY, vfp); in dwc_hdmi_av_composer()
172 hsync_len = (sc->sc_mode.hsync_end - sc->sc_mode.hsync_start); in dwc_hdmi_av_composer()
174 WR1(sc, HDMI_FC_HSYNCINWIDTH1, hsync_len >> 8); in dwc_hdmi_av_composer()
175 WR1(sc, HDMI_FC_HSYNCINWIDTH0, hsync_len); in dwc_hdmi_av_composer()
178 WR1(sc, HDMI_FC_VSYNCINWIDTH, (sc->sc_mode.vsync_end - sc->sc_mode.vsync_start)); in dwc_hdmi_av_composer()
182 dwc_hdmi_phy_enable_power(struct dwc_hdmi_softc *sc, uint8_t enable) in dwc_hdmi_phy_enable_power() argument
186 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_enable_power()
189 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_enable_power()
193 dwc_hdmi_phy_enable_tmds(struct dwc_hdmi_softc *sc, uint8_t enable) in dwc_hdmi_phy_enable_tmds() argument
197 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_enable_tmds()
200 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_enable_tmds()
204 dwc_hdmi_phy_gen2_pddq(struct dwc_hdmi_softc *sc, uint8_t enable) in dwc_hdmi_phy_gen2_pddq() argument
208 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_gen2_pddq()
211 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_gen2_pddq()
215 dwc_hdmi_phy_gen2_txpwron(struct dwc_hdmi_softc *sc, uint8_t enable) in dwc_hdmi_phy_gen2_txpwron() argument
219 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_gen2_txpwron()
222 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_gen2_txpwron()
226 dwc_hdmi_phy_sel_data_en_pol(struct dwc_hdmi_softc *sc, uint8_t enable) in dwc_hdmi_phy_sel_data_en_pol() argument
230 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_sel_data_en_pol()
233 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_sel_data_en_pol()
237 dwc_hdmi_phy_sel_interface_control(struct dwc_hdmi_softc *sc, uint8_t enable) in dwc_hdmi_phy_sel_interface_control() argument
241 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_sel_interface_control()
244 WR1(sc, HDMI_PHY_CONF0, reg); in dwc_hdmi_phy_sel_interface_control()
248 dwc_hdmi_phy_test_clear(struct dwc_hdmi_softc *sc, unsigned char bit) in dwc_hdmi_phy_test_clear() argument
252 val = RD1(sc, HDMI_PHY_TST0); in dwc_hdmi_phy_test_clear()
256 WR1(sc, HDMI_PHY_TST0, val); in dwc_hdmi_phy_test_clear()
260 dwc_hdmi_clear_overflow(struct dwc_hdmi_softc *sc) in dwc_hdmi_clear_overflow() argument
266 WR1(sc, HDMI_MC_SWRSTZ, (uint8_t)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ); in dwc_hdmi_clear_overflow()
268 val = RD1(sc, HDMI_FC_INVIDCONF); in dwc_hdmi_clear_overflow()
271 WR1(sc, HDMI_FC_INVIDCONF, val); in dwc_hdmi_clear_overflow()
275 dwc_hdmi_phy_configure(struct dwc_hdmi_softc *sc) in dwc_hdmi_phy_configure() argument
280 WR1(sc, HDMI_MC_FLOWCTRL, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS); in dwc_hdmi_phy_configure()
283 dwc_hdmi_phy_gen2_txpwron(sc, 0); in dwc_hdmi_phy_configure()
286 dwc_hdmi_phy_gen2_pddq(sc, 1); in dwc_hdmi_phy_configure()
289 WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT); in dwc_hdmi_phy_configure()
290 WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_ASSERT); in dwc_hdmi_phy_configure()
292 WR1(sc, HDMI_MC_HEACPHY_RST, HDMI_MC_HEACPHY_RST_ASSERT); in dwc_hdmi_phy_configure()
294 dwc_hdmi_phy_test_clear(sc, 1); in dwc_hdmi_phy_configure()
295 WR1(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); in dwc_hdmi_phy_configure()
296 dwc_hdmi_phy_test_clear(sc, 0); in dwc_hdmi_phy_configure()
306 if (sc->sc_mode.dot_clock*1000 <= 45250000) { in dwc_hdmi_phy_configure()
307 dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_45_25, HDMI_PHY_I2C_CPCE_CTRL); in dwc_hdmi_phy_configure()
308 dwc_hdmi_phy_i2c_write(sc, GMPCTRL_45_25, HDMI_PHY_I2C_GMPCTRL); in dwc_hdmi_phy_configure()
309 } else if (sc->sc_mode.dot_clock*1000 <= 92500000) { in dwc_hdmi_phy_configure()
310 dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_92_50, HDMI_PHY_I2C_CPCE_CTRL); in dwc_hdmi_phy_configure()
311 dwc_hdmi_phy_i2c_write(sc, GMPCTRL_92_50, HDMI_PHY_I2C_GMPCTRL); in dwc_hdmi_phy_configure()
312 } else if (sc->sc_mode.dot_clock*1000 <= 185000000) { in dwc_hdmi_phy_configure()
313 dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_185, HDMI_PHY_I2C_CPCE_CTRL); in dwc_hdmi_phy_configure()
314 dwc_hdmi_phy_i2c_write(sc, GMPCTRL_185, HDMI_PHY_I2C_GMPCTRL); in dwc_hdmi_phy_configure()
316 dwc_hdmi_phy_i2c_write(sc, CPCE_CTRL_370, HDMI_PHY_I2C_CPCE_CTRL); in dwc_hdmi_phy_configure()
317 dwc_hdmi_phy_i2c_write(sc, GMPCTRL_370, HDMI_PHY_I2C_GMPCTRL); in dwc_hdmi_phy_configure()
324 if (sc->sc_mode.dot_clock*1000 <= 54000000) { in dwc_hdmi_phy_configure()
325 dwc_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL); in dwc_hdmi_phy_configure()
326 } else if (sc->sc_mode.dot_clock*1000 <= 58400000) { in dwc_hdmi_phy_configure()
327 dwc_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL); in dwc_hdmi_phy_configure()
328 } else if (sc->sc_mode.dot_clock*1000 <= 72000000) { in dwc_hdmi_phy_configure()
329 dwc_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL); in dwc_hdmi_phy_configure()
330 } else if (sc->sc_mode.dot_clock*1000 <= 74250000) { in dwc_hdmi_phy_configure()
331 dwc_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL); in dwc_hdmi_phy_configure()
332 } else if (sc->sc_mode.dot_clock*1000 <= 118800000) { in dwc_hdmi_phy_configure()
333 dwc_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL); in dwc_hdmi_phy_configure()
334 } else if (sc->sc_mode.dot_clock*1000 <= 216000000) { in dwc_hdmi_phy_configure()
335 dwc_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL); in dwc_hdmi_phy_configure()
340 dwc_hdmi_phy_i2c_write(sc, 0x0000, HDMI_PHY_I2C_PLLPHBYCTRL); in dwc_hdmi_phy_configure()
341 dwc_hdmi_phy_i2c_write(sc, MSM_CTRL_FB_CLK, HDMI_PHY_I2C_MSM_CTRL); in dwc_hdmi_phy_configure()
343 dwc_hdmi_phy_i2c_write(sc, TXTERM_133, HDMI_PHY_I2C_TXTERM); in dwc_hdmi_phy_configure()
346 dwc_hdmi_phy_i2c_write(sc, CKCALCTRL_OVERRIDE, HDMI_PHY_I2C_CKCALCTRL); in dwc_hdmi_phy_configure()
348 if (sc->sc_mode.dot_clock*1000 > 148500000) { in dwc_hdmi_phy_configure()
349 dwc_hdmi_phy_i2c_write(sc,CKSYMTXCTRL_OVERRIDE | CKSYMTXCTRL_TX_SYMON | in dwc_hdmi_phy_configure()
351 dwc_hdmi_phy_i2c_write(sc, VLEVCTRL_TX_LVL(9) | VLEVCTRL_CK_LVL(9), in dwc_hdmi_phy_configure()
354 dwc_hdmi_phy_i2c_write(sc,CKSYMTXCTRL_OVERRIDE | CKSYMTXCTRL_TX_SYMON | in dwc_hdmi_phy_configure()
356 dwc_hdmi_phy_i2c_write(sc, VLEVCTRL_TX_LVL(13) | VLEVCTRL_CK_LVL(13), in dwc_hdmi_phy_configure()
360 dwc_hdmi_phy_enable_power(sc, 1); in dwc_hdmi_phy_configure()
363 dwc_hdmi_phy_enable_tmds(sc, 0); in dwc_hdmi_phy_configure()
364 dwc_hdmi_phy_enable_tmds(sc, 1); in dwc_hdmi_phy_configure()
367 dwc_hdmi_phy_gen2_txpwron(sc, 1); in dwc_hdmi_phy_configure()
368 dwc_hdmi_phy_gen2_pddq(sc, 0); in dwc_hdmi_phy_configure()
372 val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; in dwc_hdmi_phy_configure()
376 device_printf(sc->sc_dev, "PHY PLL not locked\n"); in dwc_hdmi_phy_configure()
379 val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; in dwc_hdmi_phy_configure()
386 dwc_hdmi_phy_init(struct dwc_hdmi_softc *sc) in dwc_hdmi_phy_init() argument
392 dwc_hdmi_phy_sel_data_en_pol(sc, 1); in dwc_hdmi_phy_init()
393 dwc_hdmi_phy_sel_interface_control(sc, 0); in dwc_hdmi_phy_init()
394 dwc_hdmi_phy_enable_tmds(sc, 0); in dwc_hdmi_phy_init()
395 dwc_hdmi_phy_enable_power(sc, 0); in dwc_hdmi_phy_init()
398 dwc_hdmi_phy_configure(sc); in dwc_hdmi_phy_init()
403 dwc_hdmi_enable_video_path(struct dwc_hdmi_softc *sc) in dwc_hdmi_enable_video_path() argument
411 WR1(sc, HDMI_FC_CTRLDUR, 12); in dwc_hdmi_enable_video_path()
412 WR1(sc, HDMI_FC_EXCTRLDUR, 32); in dwc_hdmi_enable_video_path()
413 WR1(sc, HDMI_FC_EXCTRLSPAC, 1); in dwc_hdmi_enable_video_path()
419 WR1(sc, HDMI_FC_CH0PREAM, 0x0B); in dwc_hdmi_enable_video_path()
420 WR1(sc, HDMI_FC_CH1PREAM, 0x16); in dwc_hdmi_enable_video_path()
421 WR1(sc, HDMI_FC_CH2PREAM, 0x21); in dwc_hdmi_enable_video_path()
424 clkdis = RD1(sc, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE; in dwc_hdmi_enable_video_path()
429 WR1(sc, HDMI_MC_CLKDIS, clkdis); in dwc_hdmi_enable_video_path()
432 WR1(sc, HDMI_MC_CLKDIS, clkdis); in dwc_hdmi_enable_video_path()
436 dwc_hdmi_configure_audio(struct dwc_hdmi_softc *sc) in dwc_hdmi_configure_audio() argument
441 if (sc->sc_has_audio == 0) in dwc_hdmi_configure_audio()
445 switch (sc->sc_mode.dot_clock) { in dwc_hdmi_configure_audio()
463 WR1(sc, HDMI_AUD_N1, (n >> 0) & 0xff); in dwc_hdmi_configure_audio()
464 WR1(sc, HDMI_AUD_N2, (n >> 8) & 0xff); in dwc_hdmi_configure_audio()
465 WR1(sc, HDMI_AUD_N3, (n >> 16) & 0xff); in dwc_hdmi_configure_audio()
467 val = RD1(sc, HDMI_AUD_CTS3); in dwc_hdmi_configure_audio()
469 WR1(sc, HDMI_AUD_CTS3, val); in dwc_hdmi_configure_audio()
471 val = RD1(sc, HDMI_AUD_CONF0); in dwc_hdmi_configure_audio()
476 WR1(sc, HDMI_AUD_CONF0, val); in dwc_hdmi_configure_audio()
478 val = RD1(sc, HDMI_AUD_CONF1); in dwc_hdmi_configure_audio()
483 WR1(sc, HDMI_AUD_CONF1, val); in dwc_hdmi_configure_audio()
485 WR1(sc, HDMI_AUD_INPUTCLKFS, HDMI_AUD_INPUTCLKFS_64); in dwc_hdmi_configure_audio()
487 WR1(sc, HDMI_FC_AUDICONF0, 1 << 4); /* CC=1 */ in dwc_hdmi_configure_audio()
488 WR1(sc, HDMI_FC_AUDICONF1, 0); in dwc_hdmi_configure_audio()
489 WR1(sc, HDMI_FC_AUDICONF2, 0); /* CA=0 */ in dwc_hdmi_configure_audio()
490 WR1(sc, HDMI_FC_AUDICONF3, 0); in dwc_hdmi_configure_audio()
491 WR1(sc, HDMI_FC_AUDSV, 0xee); /* channels valid */ in dwc_hdmi_configure_audio()
494 val = RD1(sc, HDMI_MC_CLKDIS); in dwc_hdmi_configure_audio()
496 WR1(sc, HDMI_MC_CLKDIS, val); in dwc_hdmi_configure_audio()
500 dwc_hdmi_video_packetize(struct dwc_hdmi_softc *sc) in dwc_hdmi_video_packetize() argument
513 WR1(sc, HDMI_VP_PR_CD, val); in dwc_hdmi_video_packetize()
515 val = RD1(sc, HDMI_VP_STUFF); in dwc_hdmi_video_packetize()
518 WR1(sc, HDMI_VP_STUFF, val); in dwc_hdmi_video_packetize()
520 val = RD1(sc, HDMI_VP_CONF); in dwc_hdmi_video_packetize()
525 WR1(sc, HDMI_VP_CONF, val); in dwc_hdmi_video_packetize()
527 val = RD1(sc, HDMI_VP_STUFF); in dwc_hdmi_video_packetize()
530 WR1(sc, HDMI_VP_STUFF, val); in dwc_hdmi_video_packetize()
532 WR1(sc, HDMI_VP_REMAP, remap_size); in dwc_hdmi_video_packetize()
535 val = RD1(sc, HDMI_VP_CONF); in dwc_hdmi_video_packetize()
542 WR1(sc, HDMI_VP_CONF, val); in dwc_hdmi_video_packetize()
544 val = RD1(sc, HDMI_VP_CONF); in dwc_hdmi_video_packetize()
551 WR1(sc, HDMI_VP_CONF, val); in dwc_hdmi_video_packetize()
553 val = RD1(sc, HDMI_VP_CONF); in dwc_hdmi_video_packetize()
560 WR1(sc, HDMI_VP_CONF, val); in dwc_hdmi_video_packetize()
565 val = RD1(sc, HDMI_VP_STUFF); in dwc_hdmi_video_packetize()
570 WR1(sc, HDMI_VP_STUFF, val); in dwc_hdmi_video_packetize()
572 val = RD1(sc, HDMI_VP_CONF); in dwc_hdmi_video_packetize()
575 WR1(sc, HDMI_VP_CONF, val); in dwc_hdmi_video_packetize()
579 dwc_hdmi_video_sample(struct dwc_hdmi_softc *sc) in dwc_hdmi_video_sample() argument
588 WR1(sc, HDMI_TX_INVID0, val); in dwc_hdmi_video_sample()
594 WR1(sc, HDMI_TX_INSTUFFING, val); in dwc_hdmi_video_sample()
595 WR1(sc, HDMI_TX_GYDATA0, 0x0); in dwc_hdmi_video_sample()
596 WR1(sc, HDMI_TX_GYDATA1, 0x0); in dwc_hdmi_video_sample()
597 WR1(sc, HDMI_TX_RCRDATA0, 0x0); in dwc_hdmi_video_sample()
598 WR1(sc, HDMI_TX_RCRDATA1, 0x0); in dwc_hdmi_video_sample()
599 WR1(sc, HDMI_TX_BCBDATA0, 0x0); in dwc_hdmi_video_sample()
600 WR1(sc, HDMI_TX_BCBDATA1, 0x0); in dwc_hdmi_video_sample()
604 dwc_hdmi_tx_hdcp_config(struct dwc_hdmi_softc *sc) in dwc_hdmi_tx_hdcp_config() argument
611 val = RD1(sc, HDMI_A_HDCPCFG0); in dwc_hdmi_tx_hdcp_config()
614 WR1(sc, HDMI_A_HDCPCFG0, val); in dwc_hdmi_tx_hdcp_config()
617 val = RD1(sc, HDMI_A_VIDPOLCFG); in dwc_hdmi_tx_hdcp_config()
620 WR1(sc, HDMI_A_VIDPOLCFG, val); in dwc_hdmi_tx_hdcp_config()
623 val = RD1(sc, HDMI_A_HDCPCFG1); in dwc_hdmi_tx_hdcp_config()
626 WR1(sc, HDMI_A_HDCPCFG1, val); in dwc_hdmi_tx_hdcp_config()
630 dwc_hdmi_set_mode(struct dwc_hdmi_softc *sc) in dwc_hdmi_set_mode() argument
634 sc->sc_has_audio = 1; in dwc_hdmi_set_mode()
636 dwc_hdmi_disable_overflow_interrupts(sc); in dwc_hdmi_set_mode()
637 dwc_hdmi_av_composer(sc); in dwc_hdmi_set_mode()
638 dwc_hdmi_phy_init(sc); in dwc_hdmi_set_mode()
639 dwc_hdmi_enable_video_path(sc); in dwc_hdmi_set_mode()
640 dwc_hdmi_configure_audio(sc); in dwc_hdmi_set_mode()
641 /* TODO: dwc_hdmi_config_avi(sc); */ in dwc_hdmi_set_mode()
642 dwc_hdmi_video_packetize(sc); in dwc_hdmi_set_mode()
643 /* TODO: dwc_hdmi_video_csc(sc); */ in dwc_hdmi_set_mode()
644 dwc_hdmi_video_sample(sc); in dwc_hdmi_set_mode()
645 dwc_hdmi_tx_hdcp_config(sc); in dwc_hdmi_set_mode()
646 dwc_hdmi_clear_overflow(sc); in dwc_hdmi_set_mode()
652 hdmi_edid_read(struct dwc_hdmi_softc *sc, int block, uint8_t **edid, in hdmi_edid_read() argument
667 { I2C_DDC_ADDR, IIC_M_RD, EDID_LENGTH, sc->sc_edid } in hdmi_edid_read()
674 if (sc->sc_get_i2c_dev != NULL) in hdmi_edid_read()
675 i2c_dev = sc->sc_get_i2c_dev(sc->sc_dev); in hdmi_edid_read()
677 device_printf(sc->sc_dev, "no DDC device found\n"); in hdmi_edid_read()
682 device_printf(sc->sc_dev, in hdmi_edid_read()
686 result = iicbus_request_bus(i2c_dev, sc->sc_dev, IIC_INTRWAIT); in hdmi_edid_read()
689 device_printf(sc->sc_dev, "failed to request i2c bus: %d\n", result); in hdmi_edid_read()
694 iicbus_release_bus(i2c_dev, sc->sc_dev); in hdmi_edid_read()
697 device_printf(sc->sc_dev, "i2c transfer failed: %d\n", result); in hdmi_edid_read()
700 *edid_len = sc->sc_edid_len; in hdmi_edid_read()
701 *edid = sc->sc_edid; in hdmi_edid_read()
710 struct dwc_hdmi_softc *sc; in dwc_hdmi_detect_cable() local
713 sc = arg; in dwc_hdmi_detect_cable()
715 stat = RD1(sc, HDMI_IH_PHY_STAT0); in dwc_hdmi_detect_cable()
717 EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev, in dwc_hdmi_detect_cable()
722 config_intrhook_disestablish(&sc->sc_mode_hook); in dwc_hdmi_detect_cable()
728 struct dwc_hdmi_softc *sc; in dwc_hdmi_init() local
731 sc = device_get_softc(dev); in dwc_hdmi_init()
734 sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO); in dwc_hdmi_init()
735 sc->sc_edid_len = EDID_LENGTH; in dwc_hdmi_init()
737 device_printf(sc->sc_dev, "HDMI controller %02x:%02x:%02x:%02x\n", in dwc_hdmi_init()
738 RD1(sc, HDMI_DESIGN_ID), RD1(sc, HDMI_REVISION_ID), in dwc_hdmi_init()
739 RD1(sc, HDMI_PRODUCT_ID0), RD1(sc, HDMI_PRODUCT_ID1)); in dwc_hdmi_init()
741 WR1(sc, HDMI_PHY_POL0, HDMI_PHY_POL0_HPD); in dwc_hdmi_init()
742 WR1(sc, HDMI_IH_PHY_STAT0, HDMI_IH_PHY_STAT0_HPD); in dwc_hdmi_init()
744 sc->sc_mode_hook.ich_func = dwc_hdmi_detect_cable; in dwc_hdmi_init()
745 sc->sc_mode_hook.ich_arg = sc; in dwc_hdmi_init()
746 if (config_intrhook_establish(&sc->sc_mode_hook) != 0) { in dwc_hdmi_init()
754 free(sc->sc_edid, M_DEVBUF); in dwc_hdmi_init()
755 sc->sc_edid = NULL; in dwc_hdmi_init()
798 dwc_hdmi_detect_hdmi(struct dwc_hdmi_softc *sc) in dwc_hdmi_detect_hdmi() argument
804 sc->sc_has_audio = 0; in dwc_hdmi_detect_hdmi()
807 for (block = 1; block <= sc->sc_edid_info.edid_ext_block_count; in dwc_hdmi_detect_hdmi()
809 if (hdmi_edid_read(sc, block, &edid, &edid_len) != 0) in dwc_hdmi_detect_hdmi()
813 device_printf(sc->sc_dev, in dwc_hdmi_detect_hdmi()
815 sc->sc_has_audio = in dwc_hdmi_detect_hdmi()
825 struct dwc_hdmi_softc *sc; in dwc_hdmi_get_edid() local
828 sc = device_get_softc(dev); in dwc_hdmi_get_edid()
830 memset(&sc->sc_edid_info, 0, sizeof(sc->sc_edid_info)); in dwc_hdmi_get_edid()
832 error = hdmi_edid_read(sc, 0, edid, edid_len); in dwc_hdmi_get_edid()
836 edid_parse(*edid, &sc->sc_edid_info); in dwc_hdmi_get_edid()
844 struct dwc_hdmi_softc *sc; in dwc_hdmi_set_videomode() local
846 sc = device_get_softc(dev); in dwc_hdmi_set_videomode()
847 memcpy(&sc->sc_mode, mode, sizeof(*mode)); in dwc_hdmi_set_videomode()
849 dwc_hdmi_detect_hdmi(sc); in dwc_hdmi_set_videomode()
851 dwc_hdmi_set_mode(sc); in dwc_hdmi_set_videomode()