Lines Matching +full:pin +full:- +full:val
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 #define CHVGPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
77 #define CHVGPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
79 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
81 #define CHVGPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
82 #define CHVGPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
83 #define CHVGPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
112 chvgpio_pad_cfg0_offset(int pin) in chvgpio_pad_cfg0_offset() argument
114 return (CHVGPIO_PAD_CFG0 + 1024 * (pin / 15) + 8 * (pin % 15)); in chvgpio_pad_cfg0_offset()
118 chvgpio_read_pad_cfg0(struct chvgpio_softc *sc, int pin) in chvgpio_read_pad_cfg0() argument
120 return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin)); in chvgpio_read_pad_cfg0()
124 chvgpio_write_pad_cfg0(struct chvgpio_softc *sc, int pin, uint32_t val) in chvgpio_write_pad_cfg0() argument
126 bus_write_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin), val); in chvgpio_write_pad_cfg0()
130 chvgpio_read_pad_cfg1(struct chvgpio_softc *sc, int pin) in chvgpio_read_pad_cfg1() argument
132 return bus_read_4(sc->sc_mem_res, chvgpio_pad_cfg0_offset(pin) + 4); in chvgpio_read_pad_cfg1()
142 return (sc->sc_busdev); in chvgpio_get_bus()
152 *maxpin = sc->sc_npins - 1; in chvgpio_pin_max()
158 chvgpio_valid_pin(struct chvgpio_softc *sc, int pin) in chvgpio_valid_pin() argument
160 if (pin < 0) in chvgpio_valid_pin()
162 if ((pin / 15) >= sc->sc_ngroups) in chvgpio_valid_pin()
164 if ((pin % 15) >= sc->sc_pins[pin / 15]) in chvgpio_valid_pin()
170 chvgpio_pin_getname(device_t dev, uint32_t pin, char *name) in chvgpio_pin_getname() argument
175 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_getname()
178 /* return pin name from datasheet */ in chvgpio_pin_getname()
179 snprintf(name, GPIOMAXNAME, "%s", sc->sc_pin_names[pin]); in chvgpio_pin_getname()
180 name[GPIOMAXNAME - 1] = '\0'; in chvgpio_pin_getname()
185 chvgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) in chvgpio_pin_getcaps() argument
190 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_getcaps()
194 if (chvgpio_valid_pin(sc, pin)) in chvgpio_pin_getcaps()
201 chvgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) in chvgpio_pin_getflags() argument
204 uint32_t val; in chvgpio_pin_getflags() local
207 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_getflags()
212 /* Get the current pin state */ in chvgpio_pin_getflags()
214 val = chvgpio_read_pad_cfg0(sc, pin); in chvgpio_pin_getflags()
216 if (val & CHVGPIO_PAD_CFG0_GPIOCFG_GPIO || in chvgpio_pin_getflags()
217 val & CHVGPIO_PAD_CFG0_GPIOCFG_GPO) in chvgpio_pin_getflags()
220 if (val & CHVGPIO_PAD_CFG0_GPIOCFG_GPIO || in chvgpio_pin_getflags()
221 val & CHVGPIO_PAD_CFG0_GPIOCFG_GPI) in chvgpio_pin_getflags()
224 val = chvgpio_read_pad_cfg1(sc, pin); in chvgpio_pin_getflags()
231 chvgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) in chvgpio_pin_setflags() argument
234 uint32_t val; in chvgpio_pin_setflags() local
238 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_setflags()
257 val = chvgpio_read_pad_cfg0(sc, pin); in chvgpio_pin_setflags()
259 val = val & CHVGPIO_PAD_CFG0_GPIOCFG_GPI; in chvgpio_pin_setflags()
261 val = val & CHVGPIO_PAD_CFG0_GPIOCFG_GPO; in chvgpio_pin_setflags()
262 chvgpio_write_pad_cfg0(sc, pin, val); in chvgpio_pin_setflags()
269 chvgpio_pin_set(device_t dev, uint32_t pin, unsigned int value) in chvgpio_pin_set() argument
272 uint32_t val; in chvgpio_pin_set() local
275 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_set()
279 val = chvgpio_read_pad_cfg0(sc, pin); in chvgpio_pin_set()
281 val = val & ~CHVGPIO_PAD_CFG0_GPIOTXSTATE; in chvgpio_pin_set()
283 val = val | CHVGPIO_PAD_CFG0_GPIOTXSTATE; in chvgpio_pin_set()
284 chvgpio_write_pad_cfg0(sc, pin, val); in chvgpio_pin_set()
291 chvgpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) in chvgpio_pin_get() argument
294 uint32_t val; in chvgpio_pin_get() local
297 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_get()
302 /* Read pin value */ in chvgpio_pin_get()
303 val = chvgpio_read_pad_cfg0(sc, pin); in chvgpio_pin_get()
304 if (val & CHVGPIO_PAD_CFG0_GPIORXSTATE) in chvgpio_pin_get()
315 chvgpio_pin_toggle(device_t dev, uint32_t pin) in chvgpio_pin_toggle() argument
318 uint32_t val; in chvgpio_pin_toggle() local
321 if (chvgpio_valid_pin(sc, pin) != 0) in chvgpio_pin_toggle()
326 /* Toggle the pin */ in chvgpio_pin_toggle()
327 val = chvgpio_read_pad_cfg0(sc, pin); in chvgpio_pin_toggle()
328 val = val ^ CHVGPIO_PAD_CFG0_GPIOTXSTATE; in chvgpio_pin_toggle()
329 chvgpio_write_pad_cfg0(sc, pin, val); in chvgpio_pin_toggle()
364 sc->sc_dev = dev; in chvgpio_attach()
365 sc->sc_handle = acpi_get_handle(dev); in chvgpio_attach()
367 status = acpi_GetInteger(sc->sc_handle, "_UID", &uid); in chvgpio_attach()
377 sc->sc_bank_prefix = SW_BANK_PREFIX; in chvgpio_attach()
378 sc->sc_pins = chv_southwest_pins; in chvgpio_attach()
379 sc->sc_pin_names = chv_southwest_pin_names; in chvgpio_attach()
382 sc->sc_bank_prefix = N_BANK_PREFIX; in chvgpio_attach()
383 sc->sc_pins = chv_north_pins; in chvgpio_attach()
384 sc->sc_pin_names = chv_north_pin_names; in chvgpio_attach()
387 sc->sc_bank_prefix = E_BANK_PREFIX; in chvgpio_attach()
388 sc->sc_pins = chv_east_pins; in chvgpio_attach()
389 sc->sc_pin_names = chv_east_pin_names; in chvgpio_attach()
392 sc->sc_bank_prefix = SE_BANK_PREFIX; in chvgpio_attach()
393 sc->sc_pins = chv_southeast_pins; in chvgpio_attach()
394 sc->sc_pin_names = chv_southeast_pin_names; in chvgpio_attach()
401 for (i = 0; sc->sc_pins[i] >= 0; i++) { in chvgpio_attach()
402 sc->sc_npins += sc->sc_pins[i]; in chvgpio_attach()
403 sc->sc_ngroups++; in chvgpio_attach()
406 sc->sc_mem_rid = 0; in chvgpio_attach()
407 sc->sc_mem_res = bus_alloc_resource_any(sc->sc_dev, SYS_RES_MEMORY, in chvgpio_attach()
408 &sc->sc_mem_rid, RF_ACTIVE); in chvgpio_attach()
409 if (sc->sc_mem_res == NULL) { in chvgpio_attach()
415 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, in chvgpio_attach()
416 &sc->sc_irq_rid, RF_ACTIVE); in chvgpio_attach()
418 if (!sc->sc_irq_res) { in chvgpio_attach()
421 sc->sc_mem_rid, sc->sc_mem_res); in chvgpio_attach()
426 error = bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, in chvgpio_attach()
427 NULL, chvgpio_intr, sc, &sc->intr_handle); in chvgpio_attach()
431 device_printf(sc->sc_dev, "unable to setup irq: error %d\n", error); in chvgpio_attach()
434 sc->sc_mem_rid, sc->sc_mem_res); in chvgpio_attach()
436 sc->sc_irq_rid, sc->sc_irq_res); in chvgpio_attach()
441 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_MASK, 0); in chvgpio_attach()
442 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 0xffff); in chvgpio_attach()
444 sc->sc_busdev = gpiobus_attach_bus(dev); in chvgpio_attach()
445 if (sc->sc_busdev == NULL) { in chvgpio_attach()
448 sc->sc_mem_rid, sc->sc_mem_res); in chvgpio_attach()
450 sc->sc_irq_rid, sc->sc_irq_res); in chvgpio_attach()
464 reg = bus_read_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS); in chvgpio_intr()
468 bus_write_4(sc->sc_mem_res, CHVGPIO_INTERRUPT_STATUS, 1 << line); in chvgpio_intr()
478 if (sc->sc_busdev) in chvgpio_detach()
481 if (sc->intr_handle != NULL) in chvgpio_detach()
482 bus_teardown_intr(sc->sc_dev, sc->sc_irq_res, sc->intr_handle); in chvgpio_detach()
483 if (sc->sc_irq_res != NULL) in chvgpio_detach()
484 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, sc->sc_irq_res); in chvgpio_detach()
485 if (sc->sc_mem_res != NULL) in chvgpio_detach()
486 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, sc->sc_mem_res); in chvgpio_detach()