Lines Matching +full:0 +full:x00000004
37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
51 #define GEM_CONFIG_BURST_INF 0x00000001 /* infinite for entire packet */
52 #define GEM_CONFIG_TXDMA_LIMIT 0x0000003e
53 #define GEM_CONFIG_RXDMA_LIMIT 0x000007c0
55 #define GEM_CONFIG_RONPAULBIT 0x00000800 /* after infinite burst use */
58 #define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */
64 #define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */
69 * Bits 0-6 auto-clear when read.
71 #define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */
72 #define GEM_INTR_TX_EMPTY 0x00000002 /* TX ring empty */
73 #define GEM_INTR_TX_DONE 0x00000004 /* TX complete */
74 #define GEM_INTR_RX_DONE 0x00000010 /* Got a packet */
75 #define GEM_INTR_RX_NOBUF 0x00000020
76 #define GEM_INTR_RX_TAG_ERR 0x00000040
77 #define GEM_INTR_PERR 0x00000080 /* Parity error */
78 #define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */
79 #define GEM_INTR_TX_MAC 0x00004000
80 #define GEM_INTR_RX_MAC 0x00008000
81 #define GEM_INTR_MAC_CONTROL 0x00010000 /* MAC control interrupt */
82 #define GEM_INTR_MIF 0x00020000
83 #define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */
85 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \
86 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \
87 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \
88 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0"
91 #define GEM_PCI_ERROR_STATUS 0x1000 /* PCI error status */
92 #define GEM_PCI_ERROR_MASK 0x1004 /* PCI error mask */
93 #define GEM_PCI_BIF_CONFIG 0x1008 /* PCI BIF configuration */
94 #define GEM_PCI_BIF_DIAG 0x100c /* PCI BIF diagnostic */
96 #define GEM_RESET 0x0010 /* software reset */
99 #define GEM_PCI_ERR_STAT_BADACK 0x00000001 /* No ACK64# */
100 #define GEM_PCI_ERR_STAT_DTRTO 0x00000002 /* Delayed xaction timeout */
101 #define GEM_PCI_ERR_STAT_OTHERS 0x00000004
102 #define GEM_PCI_ERR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0"
105 #define GEM_PCI_BIF_CNF_SLOWCLK 0x00000001 /* Parity error timing */
106 #define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */
107 #define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */
108 #define GEM_PCI_BIF_CNF_M66EN 0x00000008
109 #define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \
110 "b\2B64DIS\0b\3M66EN\0\0"
113 #define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */
114 #define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */
117 #define GEM_RESET_TX 0x00000001 /* Reset TX half. */
118 #define GEM_RESET_RX 0x00000002 /* Reset RX half. */
119 #define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */
122 #define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */
123 #define GEM_TX_CONFIG 0x2004
124 #define GEM_TX_RING_PTR_LO 0x2008
125 #define GEM_TX_RING_PTR_HI 0x200c
127 #define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */
128 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */
129 #define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */
130 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */
131 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */
133 #define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */
134 #define GEM_TX_DATA_PTR_LO 0x2030
135 #define GEM_TX_DATA_PTR_HI 0x2034
137 #define GEM_TX_COMPLETION 0x2100
138 #define GEM_TX_FIFO_ADDRESS 0x2104
139 #define GEM_TX_FIFO_TAG 0x2108
140 #define GEM_TX_FIFO_DATA_LO 0x210c
141 #define GEM_TX_FIFO_DATA_HI_T1 0x2110
142 #define GEM_TX_FIFO_DATA_HI_T0 0x2114
143 #define GEM_TX_FIFO_SIZE 0x2118
144 #define GEM_TX_DEBUG 0x3028
147 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
148 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */
149 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */
150 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */
152 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */
163 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */
166 #define GEM_RX_CONFIG 0x4000
167 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */
168 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */
170 #define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */
171 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */
172 #define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */
173 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */
175 #define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */
176 #define GEM_RX_PAUSE_THRESH 0x4020
178 #define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */
179 #define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */
181 #define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */
182 #define GEM_RX_COMPLETION 0x4104 /* First pending desc */
183 #define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */
185 #define GEM_RX_FIFO_ADDRESS 0x410c
186 #define GEM_RX_FIFO_TAG 0x4110
187 #define GEM_RX_FIFO_DATA_LO 0x4114
188 #define GEM_RX_FIFO_DATA_HI_T1 0x4118
189 #define GEM_RX_FIFO_DATA_HI_T0 0x411c
190 #define GEM_RX_FIFO_SIZE 0x4120
193 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
194 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
195 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */
196 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */
197 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */
198 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */
200 #define GEM_THRSH_64 0
212 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff
213 #define GEM_RX_PTH_XON_THRESH 0x001ff000
216 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
217 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
222 #define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */
223 #define GEM_MAC_RXRESET 0x6004 /* ditto */
224 #define GEM_MAC_SEND_PAUSE_CMD 0x6008
225 #define GEM_MAC_TX_STATUS 0x6010
226 #define GEM_MAC_RX_STATUS 0x6014
227 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */
228 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */
229 #define GEM_MAC_RX_MASK 0x6024
230 #define GEM_MAC_CONTROL_MASK 0x6028
231 #define GEM_MAC_TX_CONFIG 0x6030
232 #define GEM_MAC_RX_CONFIG 0x6034
233 #define GEM_MAC_CONTROL_CONFIG 0x6038
234 #define GEM_MAC_XIF_CONFIG 0x603c
235 #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */
236 #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */
237 #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */
238 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */
239 #define GEM_MAC_MAC_MIN_FRAME 0x6050
240 #define GEM_MAC_MAC_MAX_FRAME 0x6054
241 #define GEM_MAC_PREAMBLE_LEN 0x6058
242 #define GEM_MAC_JAM_SIZE 0x605c
243 #define GEM_MAC_ATTEMPT_LIMIT 0x6060
244 #define GEM_MAC_CONTROL_TYPE 0x6064
246 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */
247 #define GEM_MAC_ADDR1 0x6084
248 #define GEM_MAC_ADDR2 0x6088
249 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */
250 #define GEM_MAC_ADDR4 0x6090
251 #define GEM_MAC_ADDR5 0x6094
252 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */
253 #define GEM_MAC_ADDR7 0x609c
254 #define GEM_MAC_ADDR8 0x60a0
256 #define GEM_MAC_ADDR_FILTER0 0x60a4
257 #define GEM_MAC_ADDR_FILTER1 0x60a8
258 #define GEM_MAC_ADDR_FILTER2 0x60ac
259 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */
260 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */
262 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */
263 #define GEM_MAC_HASH1 0x60c4
264 #define GEM_MAC_HASH2 0x60c8
265 #define GEM_MAC_HASH3 0x60cc
266 #define GEM_MAC_HASH4 0x60d0
267 #define GEM_MAC_HASH5 0x60d4
268 #define GEM_MAC_HASH6 0x60d8
269 #define GEM_MAC_HASH7 0x60dc
270 #define GEM_MAC_HASH8 0x60e0
271 #define GEM_MAC_HASH9 0x60e4
272 #define GEM_MAC_HASH10 0x60e8
273 #define GEM_MAC_HASH11 0x60ec
274 #define GEM_MAC_HASH12 0x60f0
275 #define GEM_MAC_HASH13 0x60f4
276 #define GEM_MAC_HASH14 0x60f8
277 #define GEM_MAC_HASH15 0x60fc
279 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */
280 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */
281 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */
282 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */
283 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */
284 #define GEM_MAC_PEAK_ATTEMPTS 0x6114
285 #define GEM_MAC_RX_FRAME_COUNT 0x6118
286 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c
287 #define GEM_MAC_RX_ALIGN_ERR 0x6120
288 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124
289 #define GEM_MAC_RX_CODE_VIOL 0x6128
290 #define GEM_MAC_RANDOM_SEED 0x6130
291 #define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */
294 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff
295 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000
298 #define GEM_MAC_TX_XMIT_DONE 0x00000001
299 #define GEM_MAC_TX_UNDERRUN 0x00000002
300 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004
301 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */
302 #define GEM_MAC_TX_ECC_EXP 0x00000010
303 #define GEM_MAC_TX_LCC_EXP 0x00000020
304 #define GEM_MAC_TX_FCC_EXP 0x00000040
305 #define GEM_MAC_TX_DEFER_EXP 0x00000080
306 #define GEM_MAC_TX_PEAK_EXP 0x00000100
309 #define GEM_MAC_RX_DONE 0x00000001
310 #define GEM_MAC_RX_OVERFLOW 0x00000002
311 #define GEM_MAC_RX_FRAME_CNT 0x00000004
312 #define GEM_MAC_RX_ALIGN_EXP 0x00000008
313 #define GEM_MAC_RX_CRC_EXP 0x00000010
314 #define GEM_MAC_RX_LEN_EXP 0x00000020
315 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */
318 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */
319 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */
320 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */
321 #define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */
322 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0"
329 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */
330 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */
331 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */
332 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */
333 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */
334 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */
335 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */
336 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \
337 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \
338 "b\6FDLED\0\0"
345 #define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200
346 #define GEM_MAC_SLOT_TIME_NORMAL 0x40
349 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */
350 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */
351 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */
352 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */
353 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */
354 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
355 #define GEM_MAC_TX_NO_BACKOFF 0x00000040
356 #define GEM_MAC_TX_SLOWDOWN 0x00000080
357 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */
358 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */
361 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \
362 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \
363 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \
364 "b\x9TXCARREXT\0\0"
367 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */
368 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */
369 #define GEM_MAC_RX_STRIP_CRC 0x00000004
370 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */
371 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */
372 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */
373 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */
374 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */
375 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
381 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \
382 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \
383 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0"
386 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */
387 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */
388 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */
389 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0"
395 #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */
396 #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */
397 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208
398 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */
399 #define GEM_MIF_CONFIG 0x6210
400 #define GEM_MIF_MASK 0x6214
401 #define GEM_MIF_STATUS 0x6218
402 #define GEM_MIF_STATE_MACHINE 0x621c
405 #define GEM_MIF_FRAME_DATA 0x0000ffff
406 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA LSB, 1 for completion */
407 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA MSB, 1 for instruction */
408 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000
409 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address */
410 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */
411 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */
413 #define GEM_MIF_FRAME_READ 0x60020000
414 #define GEM_MIF_FRAME_WRITE 0x50020000
420 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0: MDIO_0 */
421 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */
422 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */
423 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */
424 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 attached/data */
425 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 attached/data */
426 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
427 /* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */
428 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \
429 "b\x8MDIO0\0b\x9MDIO1\0\0"
432 #define GEM_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */
433 #define GEM_MIF_POLL_STATUS_SHFT 0
434 #define GEM_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */
443 #define GEM_MII_CONTROL 0x9000
444 #define GEM_MII_STATUS 0x9004
445 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */
446 #define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */
447 #define GEM_MII_CONFIG 0x9010
448 #define GEM_MII_STATE_MACHINE 0x9014
449 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */
450 #define GEM_MII_DATAPATH_MODE 0x9050
451 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */
452 #define GEM_MII_OUTPUT_SELECT 0x9058
453 #define GEM_MII_SLINK_STATUS 0x905c /* Serialink status */
456 #define GEM_MII_CONTROL_1000M 0x00000040 /* 1000Mbps speed select */
457 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */
458 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */
459 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */
460 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY from MII */
461 #define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down */
462 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */
463 #define GEM_MII_CONTROL_10_100M 0x00002000 /* 10/100Mbps speed select */
464 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
465 #define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS. */
466 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \
467 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \
468 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0"
471 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability */
472 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */
473 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */
474 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */
475 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */
476 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
477 #define GEM_MII_STATUS_EXTENDED 0x00000100 /* extended status */
478 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \
479 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0\0"
482 #define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */
483 #define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */
484 #define GEM_MII_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */
485 #define GEM_MII_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */
486 #define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
487 #define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
490 #define GEM_MII_ANEG_ACK 0x00004000 /* acknowledge */
491 #define GEM_MII_ANEG_NP 0x00008000 /* next page */
492 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \
493 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \
494 "\b\xfNPBIT\0\0"
497 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS. */
498 #define GEM_MII_CONFIG_SDO 0x00000002 /* signal detect override */
499 #define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */
500 #define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */
501 #define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */
502 #define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */
505 #define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */
506 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0"
512 #define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */
515 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serialink */
516 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
517 #define GEM_MII_DATAPATH_MII 0x00000004 /* GMII/MII */
518 #define GEM_MII_DATAPATH_GMIIOE 0x00000008 /* serial output on GMII en. */
520 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3GMIIOE\0\0"
523 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at SL, logic
525 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
526 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock to reference clock */
527 #define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */
528 #define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */
529 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink. */
530 #define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink. */
531 #define GEM_MII_SLINK_RX_POLE 0x00003000 /* PLL input to Serialink. */
532 #define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink. */
533 #define GEM_MII_SLINK_TX_POLE 0x00030000 /* PLL input to Serialink. */
535 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \
536 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0"
539 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */
540 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us w/ lockrefn */
541 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */
542 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */
549 #define GEM_PCI_ROM_OFFSET 0x100000
550 #define GEM_PCI_ROM_SIZE 0x10000
554 #define GEM_PHYAD_EXTERNAL 0
569 #define GEM_TD_BUFSIZE 0x0000000000007fffULL
570 #define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */
572 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */
574 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */
575 #define GEM_TD_END_OF_PACKET 0x0000000040000000ULL
576 #define GEM_TD_START_OF_PACKET 0x0000000080000000ULL
577 #define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */
578 #define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */
581 #define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */
582 #define GEM_RD_BUFSIZE 0x000000007fff0000ULL
583 #define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */
584 #define GEM_RD_HASHVAL 0x0ffff00000000000ULL
585 #define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */
586 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */
587 #define GEM_RD_BAD_CRC 0x4000000000000000ULL