Lines Matching refs:db_tr
498 struct fwohcidb_tr *db_tr; local
579 for (i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb;
580 i++, db_tr = STAILQ_NEXT(db_tr, link)) {
581 db_tr->xfer = NULL;
583 for (i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb;
584 i++, db_tr = STAILQ_NEXT(db_tr, link)) {
585 db_tr->xfer = NULL;
828 struct fwohcidb_tr *db_tr; local
833 db_tr = (struct fwohcidb_tr *)arg;
834 db = &db_tr->db[db_tr->dbcnt];
846 db_tr->dbcnt++;
867 struct fwohcidb_tr *db_tr; local
886 db_tr = dbch->top;
898 db_tr->xfer = xfer;
904 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
928 db = &db_tr->db[0];
946 db_tr->dbcnt = 2;
947 db = &db_tr->db[db_tr->dbcnt];
952 err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
954 fwohci_execute_db, db_tr,
958 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
960 fwohci_execute_db2, db_tr,
983 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
986 for (i = 2; i < db_tr->dbcnt; i++)
987 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
991 if (maxdesc < db_tr->dbcnt) {
992 maxdesc = db_tr->dbcnt;
997 LAST_DB(db_tr, db);
1001 STAILQ_NEXT(db_tr, link)->bus_addr);
1004 fsegment = db_tr->dbcnt;
1007 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1010 dbch->pdb_tr = db_tr;
1011 db_tr = STAILQ_NEXT(db_tr, link);
1012 if (db_tr != dbch->bottom) {
1034 dbch->top = db_tr;
1196 struct fwohcidb_tr *db_tr; local
1202 for (db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1203 db_tr = STAILQ_NEXT(db_tr, link), idb++) {
1205 db_tr->buf != NULL) {
1206 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1207 db_tr->buf, dbch->xferq.psize);
1208 db_tr->buf = NULL;
1209 } else if (db_tr->dma_map != NULL)
1210 bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1213 db_tr = STAILQ_FIRST(&dbch->db_trq);
1215 free(db_tr, M_FW);
1224 struct fwohcidb_tr *db_tr; local
1248 db_tr = (struct fwohcidb_tr *)
1257 free(db_tr, M_FW);
1262 db_tr->dbcnt = 0;
1263 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1264 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1268 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1274 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1278 ].start = (caddr_t)db_tr;
1281 ].end = (caddr_t)db_tr;
1283 db_tr++;
1341 struct fwohcidb_tr *db_tr; local
1365 db_tr = dbch->top;
1367 fwohci_add_tx_buf(dbch, db_tr, idb);
1368 if (STAILQ_NEXT(db_tr, link) == NULL) {
1371 db = db_tr->db;
1372 ldesc = db_tr->dbcnt - 1;
1374 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1387 db_tr = STAILQ_NEXT(db_tr, link);
1400 struct fwohcidb_tr *db_tr; local
1434 db_tr = dbch->top;
1436 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1437 if (STAILQ_NEXT(db_tr, link) == NULL)
1439 db = db_tr->db;
1440 ldesc = db_tr->dbcnt - 1;
1442 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1453 db_tr = STAILQ_NEXT(db_tr, link);
1456 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1626 struct fwohcidb_tr *db_tr; local
1665 db_tr = (struct fwohcidb_tr *)(chunk->start);
1666 db_tr->dbcnt = 1;
1667 err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1668 chunk->mbuf, fwohci_execute_db2, db_tr,
1670 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
2184 struct fwohcidb_tr *db_tr; local
2200 db_tr = (struct fwohcidb_tr *)chunk->end;
2201 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2207 bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2209 bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2381 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, argument
2411 (uintmax_t)db_tr->bus_addr,
2500 struct fwohcidb_tr *db_tr; local
2516 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2519 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2522 db = db_tr->db;
2523 fp = (struct fw_pkt *)db_tr->buf;
2544 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2549 bulkxfer->end = (caddr_t)db_tr;
2550 db_tr = STAILQ_NEXT(db_tr, link);
2561 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2563 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, …
2569 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, argument
2572 struct fwohcidb *db = db_tr->db;
2581 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2582 db_tr->dbcnt = 3;
2601 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, argument
2604 struct fwohcidb *db = db_tr->db;
2612 if (db_tr->buf == NULL) {
2613 db_tr->buf = fwdma_malloc_size(dbch->dmat,
2614 &db_tr->dma_map, ir->psize, &dbuf[0],
2616 if (db_tr->buf == NULL)
2619 db_tr->dbcnt = 1;
2621 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2624 db_tr->dbcnt = 0;
2626 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2627 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2629 dsiz[db_tr->dbcnt] = ir->psize;
2631 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2632 dbuf[db_tr->dbcnt] = fwdma_bus_addr(ir->buf, poffset);
2634 db_tr->dbcnt++;
2636 for (i = 0; i < db_tr->dbcnt; i++) {
2644 ldesc = db_tr->dbcnt - 1;
2735 struct fwohcidb_tr *db_tr, uint32_t off, int wake) argument
2737 struct fwohcidb *db = &db_tr->db[0];
2743 dbch->bottom = db_tr;
2752 struct fwohcidb_tr *db_tr; local
2777 db_tr = dbch->top;
2784 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2785 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2791 db_tr->bus_addr, status, resCount);
2794 ld = (uint8_t *)db_tr->buf;
2800 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2828 bcopy(db_tr->buf, p, rlen);
2854 dbch->pdb_tr = db_tr;
2878 dbch->pdb_tr = db_tr;
2895 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2960 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
2963 if (dbch->pdb_tr != db_tr)
2965 db_tr = STAILQ_NEXT(db_tr, link);
2966 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2968 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2971 dbch->top = db_tr;
2993 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
2994 db_tr = STAILQ_NEXT(db_tr, link);
2995 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2999 dbch->top = db_tr;