Lines Matching refs:sc
197 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
198 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
199 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
200 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
201 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
202 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
203 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
205 static void ffec_init_locked(struct ffec_softc *sc);
206 static void ffec_stop_locked(struct ffec_softc *sc);
207 static void ffec_txstart_locked(struct ffec_softc *sc);
208 static void ffec_txfinish_locked(struct ffec_softc *sc);
211 RD2(struct ffec_softc *sc, bus_size_t off)
214 return (bus_read_2(sc->mem_res, off));
218 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
221 bus_write_2(sc->mem_res, off, val);
225 RD4(struct ffec_softc *sc, bus_size_t off)
228 return (bus_read_4(sc->mem_res, off));
232 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
235 bus_write_4(sc->mem_res, off, val);
239 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
246 next_txidx(struct ffec_softc *sc, uint32_t curidx)
262 ffec_miigasket_setup(struct ffec_softc *sc)
270 switch (sc->fectype)
278 switch (sc->phy_conn_type)
294 WR2(sc, FEC_MIIGSK_ENR, 0);
295 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
298 WR2(sc, FEC_MIIGSK_CFGR, ifmode);
300 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
301 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
306 ffec_miibus_iowait(struct ffec_softc *sc)
311 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
320 struct ffec_softc *sc;
323 sc = device_get_softc(dev);
325 WR4(sc, FEC_IER_REG, FEC_IER_MII);
327 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
332 if (!ffec_miibus_iowait(sc)) {
337 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
345 struct ffec_softc *sc;
347 sc = device_get_softc(dev);
349 WR4(sc, FEC_IER_REG, FEC_IER_MII);
351 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
357 if (!ffec_miibus_iowait(sc)) {
368 struct ffec_softc *sc;
377 sc = device_get_softc(dev);
379 FFEC_ASSERT_LOCKED(sc);
381 mii = sc->mii_softc;
384 sc->link_is_up = true;
386 sc->link_is_up = false;
388 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
389 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
391 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
394 switch (sc->phy_conn_type) {
420 sc->link_is_up = false;
423 sc->link_is_up = false;
437 WR4(sc, FEC_RCR_REG, rcr);
438 WR4(sc, FEC_TCR_REG, tcr);
439 WR4(sc, FEC_ECR_REG, ecr);
445 struct ffec_softc *sc;
449 sc = if_getsoftc(ifp);
450 mii = sc->mii_softc;
451 FFEC_LOCK(sc);
455 FFEC_UNLOCK(sc);
459 ffec_media_change_locked(struct ffec_softc *sc)
462 return (mii_mediachg(sc->mii_softc));
468 struct ffec_softc *sc;
471 sc = if_getsoftc(ifp);
473 FFEC_LOCK(sc);
474 error = ffec_media_change_locked(sc);
475 FFEC_UNLOCK(sc);
479 static void ffec_clear_stats(struct ffec_softc *sc)
483 mibc = RD4(sc, FEC_MIBC_REG);
490 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) {
491 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
492 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR);
494 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS);
496 WR4(sc, FEC_IEEE_R_DROP, 0);
497 WR4(sc, FEC_IEEE_R_MACERR, 0);
498 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
499 WR4(sc, FEC_RMON_R_FRAG, 0);
500 WR4(sc, FEC_RMON_R_JAB, 0);
501 WR4(sc, FEC_RMON_R_MC_PKT, 0);
502 WR4(sc, FEC_RMON_R_OVERSIZE, 0);
503 WR4(sc, FEC_RMON_R_PACKETS, 0);
504 WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
505 WR4(sc, FEC_RMON_T_COL, 0);
506 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
507 WR4(sc, FEC_RMON_T_FRAG, 0);
508 WR4(sc, FEC_RMON_T_JAB, 0);
509 WR4(sc, FEC_RMON_T_MC_PKT, 0);
510 WR4(sc, FEC_RMON_T_OVERSIZE , 0);
511 WR4(sc, FEC_RMON_T_PACKETS, 0);
512 WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
514 WR4(sc, FEC_MIBC_REG, mibc);
519 ffec_harvest_stats(struct ffec_softc *sc)
523 ifp = sc->ifp;
530 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
531 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
533 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
534 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
535 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP));
537 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR));
539 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
540 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
542 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
543 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
544 RD4(sc, FEC_RMON_T_JAB));
546 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
548 ffec_clear_stats(sc);
554 struct ffec_softc *sc;
558 sc = arg;
560 FFEC_ASSERT_LOCKED(sc);
562 ifp = sc->ifp;
572 if (sc->tx_watchdog_count > 0) {
573 if (--sc->tx_watchdog_count == 0) {
574 ffec_txfinish_locked(sc);
579 ffec_harvest_stats(sc);
582 link_was_up = sc->link_is_up;
583 mii_tick(sc->mii_softc);
584 if (sc->link_is_up && !link_was_up)
585 ffec_txstart_locked(sc);
588 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
592 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
598 nidx = next_txidx(sc, idx);
603 --sc->txcount;
606 ++sc->txcount;
616 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
617 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
623 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
633 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
638 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
641 sc->txbuf_map[idx].mbuf = m;
642 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
649 ffec_txstart_locked(struct ffec_softc *sc)
655 FFEC_ASSERT_LOCKED(sc);
657 if (!sc->link_is_up)
660 ifp = sc->ifp;
668 if (sc->txcount == (TX_DESC_COUNT-1)) {
675 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
680 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
686 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
687 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
688 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
695 struct ffec_softc *sc = if_getsoftc(ifp);
697 FFEC_LOCK(sc);
698 ffec_txstart_locked(sc);
699 FFEC_UNLOCK(sc);
703 ffec_txfinish_locked(struct ffec_softc *sc)
710 FFEC_ASSERT_LOCKED(sc);
713 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
714 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
715 ifp = sc->ifp;
717 while (sc->tx_idx_tail != sc->tx_idx_head) {
718 desc = &sc->txdesc_ring[sc->tx_idx_tail];
722 bmap = &sc->txbuf_map[sc->tx_idx_tail];
723 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
725 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
728 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
729 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
738 ffec_txstart_locked(sc);
742 if (sc->tx_idx_tail == sc->tx_idx_head) {
743 sc->tx_watchdog_count = 0;
748 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
757 nidx = next_rxidx(sc, idx);
758 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
759 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
766 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
771 if (!(sc->fecflags & FECFLAG_RACC)) {
780 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
783 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
789 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
792 sc->rxbuf_map[idx].mbuf = m;
793 ffec_setup_rxdesc(sc, idx, seg.ds_addr);
799 ffec_alloc_mbufcl(struct ffec_softc *sc)
811 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
823 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
824 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
825 ffec_setup_rxdesc(sc, sc->rx_idx,
826 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
830 FFEC_UNLOCK(sc);
832 bmap = &sc->rxbuf_map[sc->rx_idx];
834 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
835 bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
840 m->m_pkthdr.rcvif = sc->ifp;
852 if (sc->fecflags & FECFLAG_RACC) {
860 if_input(sc->ifp, m);
862 FFEC_LOCK(sc);
864 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
865 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
872 ffec_rxfinish_locked(struct ffec_softc *sc)
878 FFEC_ASSERT_LOCKED(sc);
881 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
882 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
885 desc = &sc->rxdesc_ring[sc->rx_idx];
894 ffec_setup_rxdesc(sc, sc->rx_idx,
895 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
906 device_printf(sc->dev,
908 ffec_setup_rxdesc(sc, sc->rx_idx,
909 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
918 ffec_setup_rxdesc(sc, sc->rx_idx,
919 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
924 ffec_rxfinish_onebuf(sc, len);
926 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
930 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE);
931 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
932 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE);
937 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
950 palr = RD4(sc, FEC_PALR_REG);
951 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
970 device_printf(sc->dev,
991 ffec_setup_rxfilter(struct ffec_softc *sc)
997 FFEC_ASSERT_LOCKED(sc);
999 ifp = sc->ifp;
1010 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
1011 WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
1025 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
1026 WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
1032 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1034 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1038 ffec_stop_locked(struct ffec_softc *sc)
1045 FFEC_ASSERT_LOCKED(sc);
1047 ifp = sc->ifp;
1049 sc->tx_watchdog_count = 0;
1055 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1056 WR4(sc, FEC_IEM_REG, 0x00000000);
1057 WR4(sc, FEC_IER_REG, 0xffffffff);
1066 callout_stop(&sc->ffec_callout);
1075 idx = sc->tx_idx_tail;
1076 while (idx != sc->tx_idx_head) {
1077 desc = &sc->txdesc_ring[idx];
1078 bmap = &sc->txbuf_map[idx];
1080 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1083 ffec_setup_txdesc(sc, idx, 0, 0);
1085 idx = next_txidx(sc, idx);
1095 desc = &sc->rxdesc_ring[idx];
1096 ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1101 ffec_init_locked(struct ffec_softc *sc)
1103 if_t ifp = sc->ifp;
1106 FFEC_ASSERT_LOCKED(sc);
1125 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align);
1132 WR4(sc, FEC_IEM_REG, 0x00000000);
1133 WR4(sc, FEC_IER_REG, 0xffffffff);
1138 ffec_setup_rxfilter(sc);
1150 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1156 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1164 WR4(sc, FEC_TCR_REG, 0);
1171 WR4(sc, FEC_OPD_REG, 0x00010020);
1195 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1202 WR4(sc, FEC_FTRL_REG, maxfl);
1211 sc->rx_idx = 0;
1212 sc->tx_idx_head = sc->tx_idx_tail = 0;
1213 sc->txcount = 0;
1214 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1215 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1224 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1230 regval = RD4(sc, FEC_MIBC_REG);
1231 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1232 ffec_clear_stats(sc);
1233 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1235 if (sc->fecflags & FECFLAG_RACC) {
1239 regval = RD4(sc, FEC_RACC_REG);
1240 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16);
1252 regval = RD4(sc, FEC_ECR_REG);
1257 WR4(sc, FEC_ECR_REG, regval);
1265 mii_mediachg(sc->mii_softc);
1266 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1272 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1278 struct ffec_softc *sc = if_softc;
1280 FFEC_LOCK(sc);
1281 ffec_init_locked(sc);
1282 FFEC_UNLOCK(sc);
1288 struct ffec_softc *sc;
1291 sc = arg;
1293 FFEC_LOCK(sc);
1295 ier = RD4(sc, FEC_IER_REG);
1298 WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1299 ffec_txfinish_locked(sc);
1303 WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1304 ffec_rxfinish_locked(sc);
1316 WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1317 device_printf(sc->dev,
1319 ffec_stop_locked(sc);
1320 ffec_init_locked(sc);
1323 FFEC_UNLOCK(sc);
1330 struct ffec_softc *sc;
1335 sc = if_getsoftc(ifp);
1341 FFEC_LOCK(sc);
1344 if ((if_getflags(ifp) ^ sc->if_flags) &
1346 ffec_setup_rxfilter(sc);
1348 if (!sc->is_detaching)
1349 ffec_init_locked(sc);
1353 ffec_stop_locked(sc);
1355 sc->if_flags = if_getflags(ifp);
1356 FFEC_UNLOCK(sc);
1362 FFEC_LOCK(sc);
1363 ffec_setup_rxfilter(sc);
1364 FFEC_UNLOCK(sc);
1370 mii = sc->mii_softc;
1393 struct ffec_softc *sc;
1402 sc = device_get_softc(dev);
1404 if (sc->is_attached) {
1405 FFEC_LOCK(sc);
1406 sc->is_detaching = true;
1407 ffec_stop_locked(sc);
1408 FFEC_UNLOCK(sc);
1409 callout_drain(&sc->ffec_callout);
1410 ether_ifdetach(sc->ifp);
1417 if ((map = sc->rxbuf_map[idx].map) != NULL) {
1418 bus_dmamap_unload(sc->rxbuf_tag, map);
1419 bus_dmamap_destroy(sc->rxbuf_tag, map);
1420 m_freem(sc->rxbuf_map[idx].mbuf);
1423 if (sc->rxbuf_tag != NULL)
1424 bus_dma_tag_destroy(sc->rxbuf_tag);
1425 if (sc->rxdesc_map != NULL) {
1426 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1427 bus_dmamem_free(sc->rxdesc_tag, sc->rxdesc_ring,
1428 sc->rxdesc_map);
1430 if (sc->rxdesc_tag != NULL)
1431 bus_dma_tag_destroy(sc->rxdesc_tag);
1435 if ((map = sc->txbuf_map[idx].map) != NULL) {
1437 bus_dmamap_destroy(sc->txbuf_tag, map);
1440 if (sc->txbuf_tag != NULL)
1441 bus_dma_tag_destroy(sc->txbuf_tag);
1442 if (sc->txdesc_map != NULL) {
1443 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1444 bus_dmamem_free(sc->txdesc_tag, sc->txdesc_ring,
1445 sc->txdesc_map);
1447 if (sc->txdesc_tag != NULL)
1448 bus_dma_tag_destroy(sc->txdesc_tag);
1452 if (sc->intr_cookie[irq] != NULL) {
1453 bus_teardown_intr(dev, sc->irq_res[irq],
1454 sc->intr_cookie[irq]);
1457 bus_release_resources(dev, irq_res_spec, sc->irq_res);
1459 if (sc->mem_res != NULL)
1460 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1462 FFEC_LOCK_DESTROY(sc);
1469 struct ffec_softc *sc;
1479 sc = device_get_softc(dev);
1480 sc->dev = dev;
1482 FFEC_LOCK_INIT(sc);
1489 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK);
1490 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK);
1492 if (sc->fecflags & FECFLAG_AVB) {
1493 sc->rxbuf_align = 64;
1494 sc->txbuf_align = 1;
1496 sc->rxbuf_align = 16;
1497 sc->txbuf_align = 16;
1509 sc->phy_conn_type = mii_fdt_get_contype(ofw_node);
1510 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) {
1511 device_printf(sc->dev, "No valid 'phy-mode' "
1517 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1521 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1523 if (sc->mem_res == NULL) {
1529 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
1548 &sc->txdesc_tag);
1550 device_printf(sc->dev,
1555 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1556 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1558 device_printf(sc->dev,
1563 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1564 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1566 device_printf(sc->dev,
1573 sc->txbuf_align, 0, /* alignment, boundary */
1581 &sc->txbuf_tag);
1583 device_printf(sc->dev,
1589 error = bus_dmamap_create(sc->txbuf_tag, 0,
1590 &sc->txbuf_map[idx].map);
1592 device_printf(sc->dev,
1596 ffec_setup_txdesc(sc, idx, 0, 0);
1612 &sc->rxdesc_tag);
1614 device_printf(sc->dev,
1619 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1620 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1622 device_printf(sc->dev,
1627 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1628 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1630 device_printf(sc->dev,
1645 &sc->rxbuf_tag);
1647 device_printf(sc->dev,
1653 error = bus_dmamap_create(sc->rxbuf_tag, 0,
1654 &sc->rxbuf_map[idx].map);
1656 device_printf(sc->dev,
1660 if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1665 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1666 device_printf(sc->dev,
1673 ffec_get_hwaddr(sc, eaddr);
1686 if (sc->fecflags & FECFLAG_AVB)
1687 WR4(sc, FEC_ECR_REG, 0);
1689 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1693 if (sc->irq_res[irq] != NULL) {
1694 error = bus_setup_intr(dev, sc->irq_res[irq],
1695 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc,
1696 &sc->intr_cookie[irq]);
1736 WR4(sc, FEC_MSCR_REG, mscr);
1739 sc->ifp = ifp = if_alloc(IFT_ETHER);
1741 if_setsoftc(ifp, sc);
1754 if_setlinkmib(ifp, &sc->mibdata);
1755 if_setlinkmiblen(ifp, sizeof(sc->mibdata));
1759 ffec_miigasket_setup(sc);
1765 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1767 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1772 sc->mii_softc = device_get_softc(sc->miibus);
1776 sc->is_attached = true;