Lines Matching +full:0 +full:xa0000
33 #define MDA_BUF_BASE 0xb0000
34 #define MDA_BUF_SIZE 0x08000
36 #define CGA_BUF_BASE 0xb8000
37 #define CGA_BUF_SIZE 0x08000
39 #define EGA_BUF_BASE 0xa0000
40 #define EGA_BUF_SIZE 0x20000
42 #define GRAPHICS_BUF_BASE 0xa0000
43 #define GRAPHICS_BUF_SIZE 0x10000
46 #define VIDEO_BUF_BASE 0xa0000
47 #define VIDEO_BUF_SIZE 0x20000
50 #define MONO_CRTC (IO_MDA + 0x04) /* crt controller base mono */
51 #define COLOR_CRTC (IO_CGA + 0x04) /* crt controller base color */
52 #define MISC (IO_VGA + 0x02) /* misc output register */
53 #define ATC (IO_VGA + 0x00) /* attribute controller */
54 #define TSIDX (IO_VGA + 0x04) /* timing sequencer idx */
55 #define TSREG (IO_VGA + 0x05) /* timing sequencer data */
56 #define PIXMASK (IO_VGA + 0x06) /* pixel write mask */
57 #define PALRADR (IO_VGA + 0x07) /* palette read address */
58 #define PALWADR (IO_VGA + 0x08) /* palette write address */
59 #define PALDATA (IO_VGA + 0x09) /* palette data register */
60 #define GDCIDX (IO_VGA + 0x0E) /* graph data controller idx */
61 #define GDCREG (IO_VGA + 0x0F) /* graph data controller data */