Lines Matching +full:0 +full:xfff

30 #define	MTKSWITCH_ATC	0x0080
33 #define		ATC_AC_CMD_CLEAN	(2u<<0)
35 #define	MTKSWITCH_VTCR	0x0090
37 #define		VTCR_FUNC_VID_READ	(0u<<12)
42 #define		VTCR_VID_MASK		0xfff
44 #define	MTKSWITCH_VAWD1	0x0094
49 #define		VAWD1_MEMBER_MASK	0xff
51 #define		VAWD1_VALID		(1u<<0)
53 #define	MTKSWITCH_VAWD2	0x0098
54 #define		VAWD2_PORT_UNTAGGED(p)	(0u<<((p)*2))
58 #define	MTKSWITCH_VTIM(v)	((((v) >> 1) * 4) + 0x100)
59 #define		VTIM_OFF(v)	(((v) & 1) ? 12 : 0)
60 #define		VTIM_MASK	0xfff
62 #define	MTKSWITCH_PIAC	0x7004
69 #define		PIAC_MDIO_RW_DATA_MASK	0xffff
71 #define	MTKSWITCH_PORTREG(r, p)	((r) + ((p) * 0x100))
73 #define	MTKSWITCH_PCR(x)	MTKSWITCH_PORTREG(0x2004, (x))
74 #define		PCR_PORT_VLAN_SECURE	(3u<<0)
76 #define	MTKSWITCH_PVC(x)	MTKSWITCH_PORTREG(0x2010, (x))
79 #define	MTKSWITCH_PPBV1(x)	MTKSWITCH_PORTREG(0x2014, (x))
80 #define	MTKSWITCH_PPBV2(x)	MTKSWITCH_PORTREG(0x2018, (x))
82 #define		PPBV_VID_FROM_REG(x)	((x) & 0xfff)
83 #define		PPBV_VID_MASK		0xfff
85 #define	MTKSWITCH_PMCR(x)	MTKSWITCH_PORTREG(0x3000, (x))
86 #define		PMCR_FORCE_LINK		(1u<<0)
102 #define	MTKSWITCH_PMSR(x)	MTKSWITCH_PORTREG(0x3008, (x))
103 #define		PMSR_MAC_LINK_STS	(1u<<0)
106 #define		PMSR_MAC_SPD(x)		(((x)>>2) & 0x3)
107 #define		PMSR_MAC_SPD_10		0
113 #define	MTKSWITCH_REG_ADDR(r)	(((r) >> 6) & 0x3ff)
114 #define	MTKSWITCH_REG_LO(r)	(((r) >> 2) & 0xf)
116 #define MTKSWITCH_VAL_LO(v)	((v) & 0xffff)
117 #define MTKSWITCH_VAL_HI(v)	(((v) >> 16) & 0xffff)
121 #define	MTKSWITCH_LAN_VID	0x001
122 #define	MTKSWITCH_WAN_VID	0x002
123 #define	MTKSWITCH_INVALID_VID	0xfff