Lines Matching +full:0 +full:x010000

34 #define FELIX_MDIO_BASE					0x1C00
36 #define	FELIX_DEVCPU_GCB_RST				0x70004
37 #define	FELIX_DEVCPU_GCB_RST_EN				BIT(0)
39 #define	FELIX_ANA_VT					0x287F34
41 #define	FELIX_ANA_VT_PORTMASK_MASK			0x7F
42 #define	FELIX_ANA_VT_STS				(BIT(0) | BIT(1))
43 #define	FELIX_ANA_VT_RESET				(BIT(0) | BIT(1))
45 #define	FELIX_ANA_VT_READ				BIT(0)
46 #define	FELIX_ANA_VT_IDLE				0
47 #define	FELIX_ANA_VTIDX					0x287F38
49 #define	FELIX_ANA_PORT_BASE				0x287800
50 #define	FELIX_ANA_PORT_OFFSET				0x100
51 #define	FELIX_ANA_PORT_VLAN_CFG				0x0
52 #define	FELIX_ANA_PORT_VLAN_CFG_VID_MASK		0xFFF
55 #define	FELIX_ANA_PORT_DROP_CFG				0x4
56 #define	FELIX_ANA_PORT_DROP_CFG_MULTI			BIT(0)
57 #define	FELIX_ANA_PORT_DROP_CFG_NULL			BIT(1)	/* SRC, or DST MAC == 0 */
58 #define	FELIX_ANA_PORT_DROP_CFG_CTAGGED_PRIO		BIT(2)	/* 0x8100, VID == 0 */
59 #define	FELIX_ANA_PORT_DROP_CFG_STAGGED_PRIO		BIT(3)	/* 0x88A8, VID == 0 */
60 #define	FELIX_ANA_PORT_DROP_CFG_CTAGGED			BIT(4)	/* 0x8100 */
61 #define	FELIX_ANA_PORT_DROP_CFG_STAGGED			BIT(5)	/* 0x88A8 */
69 #define	FELIX_DEVGMII_BASE				0x100000
70 #define	FELIX_DEVGMII_PORT_OFFSET			0x010000
72 #define	FELIX_DEVGMII_CLK_CFG				0x0
77 #define	FELIX_DEVGMII_MAC_CFG				0x1c
78 #define	FELIX_DEVGMII_MAC_CFG_TX_ENA			BIT(0)
81 #define FELIX_DEVGMII_VLAN_CFG				0x28
82 #define FELIX_DEVGMII_VLAN_CFG_ENA			BIT(0)	/* Accept 0x8100 only. */
83 #define FELIX_DEVGMII_VLAN_CFG_DOUBLE_ENA		BIT(1)	/* Inner tag can only be 0x8100. */
86 #define FELIX_REW_PORT_BASE				0x030000
87 #define FELIX_REW_PORT_OFFSET				0x80
88 #define FELIX_REW_PORT_TAG_CFG				0x4
90 #define FELIX_REW_PORT_TAG_CFG_DIS			(0 << 7) /* Port tagging disabled */
91 #define FELIX_REW_PORT_TAG_CFG_ALL			(2 << 7) /* Tag frames if pvid != 0 */
93 #define	FELIX_SYS_RAM_CTRL				0x10F24
96 #define	FELIX_SYS_CFG					0x10E00
97 #define	FELIX_SYS_CFG_CORE_EN				BIT(0)
99 #define	FELIX_QSYS_PORT_MODE(port)			(0x20F480 + 4*(port))