Lines Matching +full:0 +full:x3e0

44 #define	MV88E6141	0x3400
45 #define	MV88E6341	0x3410
46 #define	MV88E6352	0x3520
47 #define	MV88E6172	0x1720
48 #define	MV88E6176	0x1760
49 #define	MV88E6190	0x1900
52 #define	MVSWITCH_MULTICHIP(_sc)	((_sc)->sw_addr != 0)
57 #define	REG_GLOBAL			0x1b
58 #define	REG_GLOBAL2			0x1c
59 #define	REG_PORT(_sc, p)		((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p))
66 #define	PORT_STATUS			0x0
67 #define	PORT_STATUS_SPEED_MASK		0x300
68 #define	PORT_STATUS_SPEED_10		0
75 #define	PSC_CONTROL			0x1
86 #define	PSC_CONTROL_SPD10G		0x3
88 #define	PSC_CONTROL_SPD1000		0x2
89 #define	SWITCH_ID			0x3
90 #define	PORT_CONTROL			0x4
91 #define	PORT_CONTROL1			0x5
93 #define	 PORT_CONTROL1_LAG_ID_MASK	0xf
95 #define	 PORT_CONTROL1_FID_MASK		0xf
96 #define	PORT_VLAN_MAP			0x6
97 #define	PORT_VID			0x7
98 #define	PORT_CONTROL2			0x8
99 #define	PORT_ASSOCIATION_VECTOR		0xb
100 #define	PORT_ATU_CTRL			0xc
101 #define	RX_COUNTER			0x12
102 #define	TX_COUNTER			0x13
104 #define	PORT_MASK(_sc)			0x7f
105 #define	PORT_VID_DEF_VID		0
106 #define	PORT_VID_DEF_VID_MASK		0xfff
107 #define	PORT_VID_PRIORITY_MASK		0xc00
109 #define	PORT_CONTROL_DISABLED		0
114 #define	PORT_CONTROL_FRAME		0x0300
115 #define	PORT_CONTROL_EGRESS		0x3000
116 #define	PORT_CONTROL2_DOT1Q		0x0c00
122 #define	PORT_VLAN_MAP_FID_MASK		0xf000
127 #define	SWITCH_GLOBAL_STATUS		0
141 #define	VTU_FID_MASK(_sc)		(MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff)
143 #define	VTU_PORT_UNMODIFIED		0
152 #define	VTU_VID_MASK			0xfff
156 #define	VTU_NOP				(0 << 12)
177 #define	ATU_PORT_MASK(_sc)		(MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0)
179 #define	ATU_LAG_MASK                    0xf0
181 #define	ATU_STATE_MASK                  0xf
183 #define	ENTRY_STATE			0xf
187 #define	ATU_CONTROL_AGETIME_MASK	0xff0
192 #define	NO_OPERATION                    (0 << 12)
204 #define	COUNT_ALL			(0 << 0)
216 #define	MGMT_EN_ALL			0xffff
223 #define	SWITCH_MGMT_PRI			0
236 #define	SMI_CMD				0
244 #define	EEPROM_CMD			0x14
249 #define	 EEPROM_DATA_MASK		0xff
250 #define	EEPROM_ADDR			0x15
253 #define	SMI_PHY_CMD_REG			0x18
262 #define	 SMI_CMD_C45			(0 << 12)
263 #define	 SMI_CMD_C45_ADDR		(0 << 10)
273 #define	 SMI_CMD_DEV_ADDR_MASK		0x3e0
274 #define	 SMI_CMD_REG_ADDR_MASK		0x1f
275 #define	SMI_PHY_DATA_REG		0x19
276 #define	 PHY_DATA_MASK			0xffff
284 #define	SCR_AND_MISC_REG		0x1a
286 #define	SCR_AND_MISC_PTR_CFG		0x7000
287 #define	SCR_AND_MISC_DATA_CFG_MASK	0xf0
291 #define	E6000SW_SERDES_PCS_CTL1		0x1000
292 #define	E6000SW_SERDES_SGMII_CTL	0x2000