1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
5  * Copyright (c) 2011-2012 Stefan Bethke.
9  * Redistribution and use in source and binary forms, with or without
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
63 	if (arswitch_waitreg(sc->sc_dev, AR8X16_REG_VLAN_CTRL,  in ar8xxx_vlan_op()
69 		err = arswitch_writereg(sc->sc_dev, AR8X16_REG_VLAN_DATA,  in ar8xxx_vlan_op()
78 	arswitch_writereg(sc->sc_dev, AR8X16_REG_VLAN_CTRL, op);  in ar8xxx_vlan_op()
81 	if (arswitch_waitreg(sc->sc_dev, AR8X16_REG_VLAN_CTRL,  in ar8xxx_vlan_op()
105 ar8xxx_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports,  in ar8xxx_get_dot1q_vlan()  argument
116 	reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_VLAN_DATA);  in ar8xxx_get_dot1q_vlan()
118 		*ports = 0;  in ar8xxx_get_dot1q_vlan()
121 	reg &= ((1 << (sc->numphys + 1)) - 1);  in ar8xxx_get_dot1q_vlan()
122 	*ports = reg;  in ar8xxx_get_dot1q_vlan()
128 ar8xxx_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports,  in ar8xxx_set_dot1q_vlan()  argument
134 	err = ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_LOAD, vid, ports);  in ar8xxx_set_dot1q_vlan()
141 ar8xxx_get_port_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)  in ar8xxx_get_port_vlan()  argument
149 	reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port));  in ar8xxx_get_port_vlan()
150 	*ports = (reg >> AR8X16_PORT_VLAN_DEST_PORTS_SHIFT);  in ar8xxx_get_port_vlan()
151 	*ports &= AR8X16_VLAN_MEMBER;  in ar8xxx_get_port_vlan()
156 ar8xxx_set_port_vlan(struct arswitch_softc *sc, uint32_t ports, int vid)  in ar8xxx_set_port_vlan()  argument
163 	err = arswitch_modifyreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port),  in ar8xxx_set_port_vlan()
165 	    (ports & AR8X16_VLAN_MEMBER) << AR8X16_PORT_VLAN_DEST_PORTS_SHIFT);  in ar8xxx_set_port_vlan()
177 	uint32_t ports;  in ar8xxx_reset_vlans()  local
185 	memset(sc->vid, 0, sizeof(sc->vid));  in ar8xxx_reset_vlans()
187 	/* Disable the QinQ and egress filters for all ports. */  in ar8xxx_reset_vlans()
188 	for (i = 0; i <= sc->numphys; i++) {  in ar8xxx_reset_vlans()
189 		if (arswitch_modifyreg(sc->sc_dev, AR8X16_REG_PORT_CTRL(i),  in ar8xxx_reset_vlans()
197 	if (sc->hal.arswitch_flush_dot1q_vlan(sc)) {  in ar8xxx_reset_vlans()
202 	if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {  in ar8xxx_reset_vlans()
205 		 * ingress filter for all ports.  in ar8xxx_reset_vlans()
207 		ports = 0;  in ar8xxx_reset_vlans()
208 		for (i = 0; i <= sc->numphys; i++)  in ar8xxx_reset_vlans()
209 			arswitch_modifyreg(sc->sc_dev,  in ar8xxx_reset_vlans()
218 		 * Setup vlan 1 as PVID for all switch ports.  Add all ports  in ar8xxx_reset_vlans()
221 		sc->vid[0] = 1;  in ar8xxx_reset_vlans()
223 		for (i = 0; i <= sc->numphys; i++)  in ar8xxx_reset_vlans()
224 			sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]);  in ar8xxx_reset_vlans()
225 		ports = 0;  in ar8xxx_reset_vlans()
226 		for (i = 0; i <= sc->numphys; i++)  in ar8xxx_reset_vlans()
227 			ports |= (1 << i);  in ar8xxx_reset_vlans()
228 		sc->hal.arswitch_set_dot1q_vlan(sc, ports, sc->vid[0], sc->vid[0]);  in ar8xxx_reset_vlans()
229 		sc->vid[0] |= ETHERSWITCH_VID_VALID;  in ar8xxx_reset_vlans()
230 	} else if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {  in ar8xxx_reset_vlans()
232 		for (i = 0; i <= sc->numphys; i++) {  in ar8xxx_reset_vlans()
233 			sc->vid[i] = i | ETHERSWITCH_VID_VALID;  in ar8xxx_reset_vlans()
234 			ports = 0;  in ar8xxx_reset_vlans()
235 			for (j = 0; j <= sc->numphys; j++)  in ar8xxx_reset_vlans()
236 				ports |= (1 << j);  in ar8xxx_reset_vlans()
237 			arswitch_modifyreg(sc->sc_dev,  in ar8xxx_reset_vlans()
242 			    ports << AR8X16_PORT_VLAN_DEST_PORTS_SHIFT |  in ar8xxx_reset_vlans()
249 		for (i = 0; i <= sc->numphys; i++)  in ar8xxx_reset_vlans()
250 			arswitch_modifyreg(sc->sc_dev,  in ar8xxx_reset_vlans()
270 	if (vg->es_vlangroup > sc->info.es_nvlangroups)  in ar8xxx_getvgroup()
273 	/* Reset the members ports. */  in ar8xxx_getvgroup()
274 	vg->es_untagged_ports = 0;  in ar8xxx_getvgroup()
275 	vg->es_member_ports = 0;  in ar8xxx_getvgroup()
278 	vg->es_fid = 0;  in ar8xxx_getvgroup()
282 	vg->es_vid = sc->vid[vg->es_vlangroup];  in ar8xxx_getvgroup()
283 	if ((vg->es_vid & ETHERSWITCH_VID_VALID) == 0) {  in ar8xxx_getvgroup()
288 	/* Member Ports. */  in ar8xxx_getvgroup()
289 	switch (sc->vlan_mode) {  in ar8xxx_getvgroup()
291 		err = sc->hal.arswitch_get_dot1q_vlan(sc, &vg->es_member_ports,  in ar8xxx_getvgroup()
292 		    &vg->es_untagged_ports,  in ar8xxx_getvgroup()
293 		    vg->es_vid);  in ar8xxx_getvgroup()
296 		err = sc->hal.arswitch_get_port_vlan(sc, &vg->es_member_ports,  in ar8xxx_getvgroup()
297 		    vg->es_vid);  in ar8xxx_getvgroup()
298 		vg->es_untagged_ports = vg->es_member_ports;  in ar8xxx_getvgroup()
301 		vg->es_member_ports = 0;  in ar8xxx_getvgroup()
302 		vg->es_untagged_ports = 0;  in ar8xxx_getvgroup()
303 		err = -1;  in ar8xxx_getvgroup()
318 	if (sc->vlan_mode == 0)  in ar8xxx_setvgroup()
326 	vid = sc->vid[vg->es_vlangroup];  in ar8xxx_setvgroup()
327 	if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q &&  in ar8xxx_setvgroup()
330 	    (vg->es_vid & ETHERSWITCH_VID_MASK)) {  in ar8xxx_setvgroup()
331 		err = sc->hal.arswitch_purge_dot1q_vlan(sc, vid);  in ar8xxx_setvgroup()
339 	if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {  in ar8xxx_setvgroup()
340 		sc->vid[vg->es_vlangroup] = vg->es_vid & ETHERSWITCH_VID_MASK;  in ar8xxx_setvgroup()
342 		if (sc->vid[vg->es_vlangroup] == 0) {  in ar8xxx_setvgroup()
346 		sc->vid[vg->es_vlangroup] |= ETHERSWITCH_VID_VALID;  in ar8xxx_setvgroup()
347 		vid = sc->vid[vg->es_vlangroup];  in ar8xxx_setvgroup()
350 	/* Member Ports. */  in ar8xxx_setvgroup()
351 	switch (sc->vlan_mode) {  in ar8xxx_setvgroup()
353 		err = sc->hal.arswitch_set_dot1q_vlan(sc, vg->es_member_ports,  in ar8xxx_setvgroup()
354 		    vg->es_untagged_ports, vid);  in ar8xxx_setvgroup()
357 		err = sc->hal.arswitch_set_port_vlan(sc, vg->es_member_ports, vid);  in ar8xxx_setvgroup()
360 		err = -1;  in ar8xxx_setvgroup()
372 	reg = arswitch_readreg(sc->sc_dev, AR8X16_REG_PORT_VLAN(port));  in ar8xxx_get_pvid()
382 	return (arswitch_modifyreg(sc->sc_dev,  in ar8xxx_set_pvid()