Lines Matching +full:cpu +full:- +full:cfg
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
74 * which means both CPU ports can see each other and that will quickly
117 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1, in ar8327_vlan_op()
126 err = arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC0, data); in ar8327_vlan_op()
140 arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC1, op); in ar8327_vlan_op()
143 * Finally - wait for it to load. in ar8327_vlan_op()
145 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1, in ar8327_vlan_op()
156 device_printf(sc->sc_dev, in ar8327_phy_fixup()
159 sc->chip_rev); in ar8327_phy_fixup()
160 switch (sc->chip_rev) { in ar8327_phy_fixup()
163 arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea); in ar8327_phy_fixup()
165 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0); in ar8327_phy_fixup()
169 arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c); in ar8327_phy_fixup()
170 arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0); in ar8327_phy_fixup()
173 arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d); in ar8327_phy_fixup()
174 arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f); in ar8327_phy_fixup()
176 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860); in ar8327_phy_fixup()
177 arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46); in ar8327_phy_fixup()
178 arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000); in ar8327_phy_fixup()
184 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) in ar8327_get_pad_cfg() argument
188 if (!cfg) in ar8327_get_pad_cfg()
192 switch (cfg->mode) { in ar8327_get_pad_cfg()
198 if (cfg->rxclk_sel) in ar8327_get_pad_cfg()
200 if (cfg->txclk_sel) in ar8327_get_pad_cfg()
206 if (cfg->rxclk_sel) in ar8327_get_pad_cfg()
208 if (cfg->txclk_sel) in ar8327_get_pad_cfg()
221 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; in ar8327_get_pad_cfg()
222 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; in ar8327_get_pad_cfg()
223 if (cfg->rxclk_delay_en) in ar8327_get_pad_cfg()
225 if (cfg->txclk_delay_en) in ar8327_get_pad_cfg()
228 if (cfg->sgmii_delay_en) in ar8327_get_pad_cfg()
235 if (cfg->rxclk_sel) in ar8327_get_pad_cfg()
237 if (cfg->txclk_sel) in ar8327_get_pad_cfg()
243 if (cfg->pipe_rxclk_sel) in ar8327_get_pad_cfg()
245 if (cfg->rxclk_sel) in ar8327_get_pad_cfg()
247 if (cfg->txclk_sel) in ar8327_get_pad_cfg()
253 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; in ar8327_get_pad_cfg()
254 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; in ar8327_get_pad_cfg()
255 if (cfg->rxclk_delay_en) in ar8327_get_pad_cfg()
257 if (cfg->txclk_delay_en) in ar8327_get_pad_cfg()
278 * Map the hard-coded port config from the switch setup to
282 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg) in ar8327_get_port_init_status() argument
286 if (!cfg->force_link) in ar8327_get_port_init_status()
290 t |= cfg->duplex ? AR8X16_PORT_STS_DUPLEX : 0; in ar8327_get_port_init_status()
291 t |= cfg->rxpause ? AR8X16_PORT_STS_RXFLOW : 0; in ar8327_get_port_init_status()
292 t |= cfg->txpause ? AR8X16_PORT_STS_TXFLOW : 0; in ar8327_get_port_init_status()
294 switch (cfg->speed) { in ar8327_get_port_init_status()
329 (void) resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_port()
330 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_port()
334 pcfg->force_link = 1; in ar8327_fetch_pdata_port()
338 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_port()
339 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_port()
343 pcfg->speed = AR8327_PORT_SPEED_10; in ar8327_fetch_pdata_port()
346 pcfg->speed = AR8327_PORT_SPEED_100; in ar8327_fetch_pdata_port()
349 pcfg->speed = AR8327_PORT_SPEED_1000; in ar8327_fetch_pdata_port()
352 device_printf(sc->sc_dev, in ar8327_fetch_pdata_port()
362 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_port()
363 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_port()
365 pcfg->duplex = val; in ar8327_fetch_pdata_port()
368 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_port()
369 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_port()
371 pcfg->txpause = val; in ar8327_fetch_pdata_port()
374 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_port()
375 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_port()
377 pcfg->rxpause = val; in ar8327_fetch_pdata_port()
380 device_printf(sc->sc_dev, in ar8327_fetch_pdata_port()
384 pcfg->speed, in ar8327_fetch_pdata_port()
385 pcfg->duplex, in ar8327_fetch_pdata_port()
386 pcfg->txpause, in ar8327_fetch_pdata_port()
387 pcfg->rxpause); in ar8327_fetch_pdata_port()
422 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
423 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
428 pc->mode = val; in ar8327_fetch_pdata_pad()
431 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
432 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
434 pc->rxclk_sel = val; in ar8327_fetch_pdata_pad()
437 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
438 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
440 pc->txclk_sel = val; in ar8327_fetch_pdata_pad()
443 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
444 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
446 pc->txclk_delay_sel = val; in ar8327_fetch_pdata_pad()
449 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
450 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
452 pc->rxclk_delay_sel = val; in ar8327_fetch_pdata_pad()
455 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
456 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
458 pc->txclk_delay_en = val; in ar8327_fetch_pdata_pad()
461 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
462 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
464 pc->rxclk_delay_en = val; in ar8327_fetch_pdata_pad()
467 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
468 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
470 pc->sgmii_delay_en = val; in ar8327_fetch_pdata_pad()
473 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_pad()
474 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_pad()
476 pc->pipe_rxclk_sel = val; in ar8327_fetch_pdata_pad()
479 device_printf(sc->sc_dev, in ar8327_fetch_pdata_pad()
485 pc->mode, in ar8327_fetch_pdata_pad()
486 pc->rxclk_sel, in ar8327_fetch_pdata_pad()
487 pc->txclk_sel, in ar8327_fetch_pdata_pad()
488 pc->txclk_delay_sel, in ar8327_fetch_pdata_pad()
489 pc->rxclk_delay_sel, in ar8327_fetch_pdata_pad()
490 pc->txclk_delay_en, in ar8327_fetch_pdata_pad()
491 pc->rxclk_delay_en, in ar8327_fetch_pdata_pad()
492 pc->sgmii_delay_en, in ar8327_fetch_pdata_pad()
493 pc->pipe_rxclk_sel); in ar8327_fetch_pdata_pad()
510 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_sgmii()
511 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_sgmii()
514 scfg->sgmii_ctrl = val; in ar8327_fetch_pdata_sgmii()
518 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_sgmii()
519 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_sgmii()
522 scfg->serdes_aen = val; in ar8327_fetch_pdata_sgmii()
537 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_led()
538 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_led()
541 lcfg->led_ctrl0 = val; in ar8327_fetch_pdata_led()
544 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_led()
545 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_led()
548 lcfg->led_ctrl1 = val; in ar8327_fetch_pdata_led()
551 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_led()
552 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_led()
555 lcfg->led_ctrl2 = val; in ar8327_fetch_pdata_led()
558 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_led()
559 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_led()
562 lcfg->led_ctrl3 = val; in ar8327_fetch_pdata_led()
565 if (resource_int_value(device_get_name(sc->sc_dev), in ar8327_fetch_pdata_led()
566 device_get_unit(sc->sc_dev), in ar8327_fetch_pdata_led()
569 lcfg->open_drain = val; in ar8327_fetch_pdata_led()
589 sc->ar8327.port0_status = 0; in ar8327_init_pdata()
591 sc->ar8327.port0_status = ar8327_get_port_init_status(&port_cfg); in ar8327_init_pdata()
595 sc->ar8327.port6_status = 0; in ar8327_init_pdata()
597 sc->ar8327.port6_status = ar8327_get_port_init_status(&port_cfg); in ar8327_init_pdata()
608 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD0_MODE, t); in ar8327_init_pdata()
615 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD5_MODE, t); in ar8327_init_pdata()
622 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD6_MODE, t); in ar8327_init_pdata()
624 pos = arswitch_readreg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP); in ar8327_init_pdata()
635 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL0, in ar8327_init_pdata()
637 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL1, in ar8327_init_pdata()
639 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL2, in ar8327_init_pdata()
641 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL3, in ar8327_init_pdata()
651 device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__); in ar8327_init_pdata()
653 if (sc->chip_rev == 1) in ar8327_init_pdata()
662 arswitch_writereg(sc->sc_dev, AR8327_REG_SGMII_CTRL, t); in ar8327_init_pdata()
670 arswitch_writereg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP, new_pos); in ar8327_init_pdata()
707 device_printf(sc->sc_dev, "%s: TODO!\n", __func__); in ar8327_atu_learn_default()
721 /* enable CPU port and disable mirror port */ in ar8327_hw_global_setup()
724 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL0, t); in ar8327_hw_global_setup()
726 /* forward multicast and broadcast frames to CPU */ in ar8327_hw_global_setup()
730 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL1, t); in ar8327_hw_global_setup()
733 /* XXX need to macro-shift the value! */ in ar8327_hw_global_setup()
734 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MAX_FRAME_SIZE, in ar8327_hw_global_setup()
738 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MODULE_EN, in ar8327_hw_global_setup()
742 t = arswitch_readreg(sc->sc_dev, AR8327_REG_EEE_CTRL); in ar8327_hw_global_setup()
748 arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t); in ar8327_hw_global_setup()
751 /* GMAC0 (CPU), GMAC1..5 (PHYs), GMAC6 (CPU) */ in ar8327_hw_global_setup()
752 sc->info.es_nports = 7; in ar8327_hw_global_setup()
771 t = sc->ar8327.port0_status; in ar8327_port_init()
773 t = sc->ar8327.port6_status; in ar8327_port_init()
777 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_STATUS(port), t); in ar8327_port_init()
778 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_HEADER(port), 0); in ar8327_port_init()
785 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t); in ar8327_port_init()
788 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(port), t); in ar8327_port_init()
792 * bits 0-6 control which ports a frame coming into this port in ar8327_port_init()
803 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t); in ar8327_port_init()
810 /* Check: ADDTAG/STRIPTAG - exclusive */ in ar8327_port_vlan_setup()
815 if (p->es_pvid != 0) in ar8327_port_vlan_setup()
816 sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid); in ar8327_port_vlan_setup()
837 sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid); in ar8327_port_vlan_get()
854 arswitch_modifyreg(sc->sc_dev, in ar8327_port_disable_mirror()
858 arswitch_modifyreg(sc->sc_dev, in ar8327_port_disable_mirror()
875 memset(sc->vid, 0, sizeof(sc->vid)); in ar8327_reset_vlans()
880 arswitch_modifyreg(sc->sc_dev, AR8327_REG_FWD_CTRL0, in ar8327_reset_vlans()
885 * XXX TODO: disable any Q-in-Q port configuration, in ar8327_reset_vlans()
891 * flows. All ports can see other ports. There are two CPU GMACs in ar8327_reset_vlans()
904 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { in ar8327_reset_vlans()
905 sc->vid[i] = i | ETHERSWITCH_VID_VALID; in ar8327_reset_vlans()
910 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { in ar8327_reset_vlans()
923 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(i), t); in ar8327_reset_vlans()
927 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t); in ar8327_reset_vlans()
936 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(i), t); in ar8327_reset_vlans()
947 * If dot1q - set pvid; dot1q, etc. in ar8327_reset_vlans()
949 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { in ar8327_reset_vlans()
950 sc->vid[0] = 1; in ar8327_reset_vlans()
952 /* Each port - pvid 1 */ in ar8327_reset_vlans()
953 sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]); in ar8327_reset_vlans()
955 /* Initialise vlan1 - all ports, untagged */ in ar8327_reset_vlans()
956 sc->hal.arswitch_set_dot1q_vlan(sc, ports, ports, sc->vid[0]); in ar8327_reset_vlans()
957 sc->vid[0] |= ETHERSWITCH_VID_VALID; in ar8327_reset_vlans()
973 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port)); in ar8327_vlan_get_port()
988 err = arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), in ar8327_vlan_set_port()
1022 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port)); in ar8327_get_pvid()
1040 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t); in ar8327_set_pvid()
1050 ret = arswitch_waitreg(sc->sc_dev, in ar8327_atu_wait_ready()
1069 device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__); in ar8327_atu_flush()
1072 arswitch_writereg(sc->sc_dev, in ar8327_atu_flush()
1088 device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__); in ar8327_atu_flush_port()
1094 arswitch_writereg(sc->sc_dev, in ar8327_atu_flush_port()
1119 arswitch_writereg(sc->sc_dev, in ar8327_atu_fetch_table()
1121 arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_DATA0, 0); in ar8327_atu_fetch_table()
1122 arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_DATA1, 0); in ar8327_atu_fetch_table()
1123 arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_DATA2, 0); in ar8327_atu_fetch_table()
1135 val = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_FUNC); in ar8327_atu_fetch_table()
1137 arswitch_writereg(sc->sc_dev, AR8327_REG_ATU_FUNC, val); in ar8327_atu_fetch_table()
1143 ret0 = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_DATA0); in ar8327_atu_fetch_table()
1144 ret1 = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_DATA1); in ar8327_atu_fetch_table()
1145 ret2 = arswitch_readreg(sc->sc_dev, AR8327_REG_ATU_DATA2); in ar8327_atu_fetch_table()
1149 return (-1); in ar8327_atu_fetch_table()
1152 e->es_macaddr[5] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR3); in ar8327_atu_fetch_table()
1153 e->es_macaddr[4] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR2); in ar8327_atu_fetch_table()
1154 e->es_macaddr[3] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR1); in ar8327_atu_fetch_table()
1155 e->es_macaddr[2] = MS(ret0, AR8327_ATU_DATA0_MAC_ADDR0); in ar8327_atu_fetch_table()
1156 e->es_macaddr[0] = MS(ret1, AR8327_ATU_DATA1_MAC_ADDR5); in ar8327_atu_fetch_table()
1157 e->es_macaddr[1] = MS(ret1, AR8327_ATU_DATA1_MAC_ADDR4); in ar8327_atu_fetch_table()
1160 e->es_portmask = MS(ret1, AR8327_ATU_DATA1_DEST_PORT); in ar8327_atu_fetch_table()
1166 e->es_macaddr, ":", e->es_portmask); in ar8327_atu_fetch_table()
1169 return (-1); in ar8327_atu_fetch_table()
1171 return (-1); in ar8327_atu_fetch_table()
1199 /* XXX TODO: the VTU here stores egress mode - keep, tag, untagged, none */ in ar8327_get_dot1q_vlan()
1202 device_printf(sc->sc_dev, "%s: %d: op failed\n", __func__, vid); in ar8327_get_dot1q_vlan()
1205 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_VTU_FUNC0); in ar8327_get_dot1q_vlan()
1246 * Mark it as valid; and that it should use per-VLAN MAC table, in ar8327_set_dot1q_vlan()
1269 sc->hal.arswitch_hw_setup = ar8327_hw_setup; in ar8327_attach()
1270 sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup; in ar8327_attach()
1272 sc->hal.arswitch_port_init = ar8327_port_init; in ar8327_attach()
1274 sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup; in ar8327_attach()
1275 sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup; in ar8327_attach()
1276 sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup; in ar8327_attach()
1277 sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get; in ar8327_attach()
1278 sc->hal.arswitch_flush_dot1q_vlan = ar8327_flush_dot1q_vlan; in ar8327_attach()
1279 sc->hal.arswitch_purge_dot1q_vlan = ar8327_purge_dot1q_vlan; in ar8327_attach()
1280 sc->hal.arswitch_set_dot1q_vlan = ar8327_set_dot1q_vlan; in ar8327_attach()
1281 sc->hal.arswitch_get_dot1q_vlan = ar8327_get_dot1q_vlan; in ar8327_attach()
1283 sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans; in ar8327_attach()
1284 sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid; in ar8327_attach()
1285 sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid; in ar8327_attach()
1287 sc->hal.arswitch_get_port_vlan = ar8327_vlan_get_port; in ar8327_attach()
1288 sc->hal.arswitch_set_port_vlan = ar8327_vlan_set_port; in ar8327_attach()
1290 sc->hal.arswitch_atu_learn_default = ar8327_atu_learn_default; in ar8327_attach()
1291 sc->hal.arswitch_atu_flush = ar8327_atu_flush; in ar8327_attach()
1292 sc->hal.arswitch_atu_flush_port = ar8327_atu_flush_port; in ar8327_attach()
1293 sc->hal.arswitch_atu_fetch_table = ar8327_atu_fetch_table; in ar8327_attach()
1303 sc->hal.arswitch_phy_read = arswitch_readphy_external; in ar8327_attach()
1304 sc->hal.arswitch_phy_write = arswitch_writephy_external; in ar8327_attach()
1307 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q | in ar8327_attach()
1309 sc->info.es_nvlangroups = AR8X16_MAX_VLANS; in ar8327_attach()