Lines Matching +full:0 +full:x1b4
31 #define AR40XX_PORT_LINK_DOWN 0
33 #define AR40XX_QM_EMPTY 0
39 PORT_WRAPPER_PSGMII = 0,
48 #define AR40XX_PORT_CPU 0
50 #define AR40XX_PSGMII_MODE_CONTROL 0x1b4
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
53 #define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
55 #define AR40XX_MII_ATH_MMD_ADDR 0x0d
56 #define AR40XX_MII_ATH_MMD_DATA 0x0e
57 #define AR40XX_MII_ATH_DBG_ADDR 0x1d
58 #define AR40XX_MII_ATH_DBG_DATA 0x1e
60 #define AR40XX_STATS_RXBROAD 0x00
61 #define AR40XX_STATS_RXPAUSE 0x04
62 #define AR40XX_STATS_RXMULTI 0x08
63 #define AR40XX_STATS_RXFCSERR 0x0c
64 #define AR40XX_STATS_RXALIGNERR 0x10
65 #define AR40XX_STATS_RXRUNT 0x14
66 #define AR40XX_STATS_RXFRAGMENT 0x18
67 #define AR40XX_STATS_RX64BYTE 0x1c
68 #define AR40XX_STATS_RX128BYTE 0x20
69 #define AR40XX_STATS_RX256BYTE 0x24
70 #define AR40XX_STATS_RX512BYTE 0x28
71 #define AR40XX_STATS_RX1024BYTE 0x2c
72 #define AR40XX_STATS_RX1518BYTE 0x30
73 #define AR40XX_STATS_RXMAXBYTE 0x34
74 #define AR40XX_STATS_RXTOOLONG 0x38
75 #define AR40XX_STATS_RXGOODBYTE 0x3c
76 #define AR40XX_STATS_RXBADBYTE 0x44
77 #define AR40XX_STATS_RXOVERFLOW 0x4c
78 #define AR40XX_STATS_FILTERED 0x50
79 #define AR40XX_STATS_TXBROAD 0x54
80 #define AR40XX_STATS_TXPAUSE 0x58
81 #define AR40XX_STATS_TXMULTI 0x5c
82 #define AR40XX_STATS_TXUNDERRUN 0x60
83 #define AR40XX_STATS_TX64BYTE 0x64
84 #define AR40XX_STATS_TX128BYTE 0x68
85 #define AR40XX_STATS_TX256BYTE 0x6c
86 #define AR40XX_STATS_TX512BYTE 0x70
87 #define AR40XX_STATS_TX1024BYTE 0x74
88 #define AR40XX_STATS_TX1518BYTE 0x78
89 #define AR40XX_STATS_TXMAXBYTE 0x7c
90 #define AR40XX_STATS_TXOVERSIZE 0x80
91 #define AR40XX_STATS_TXBYTE 0x84
92 #define AR40XX_STATS_TXCOLLISION 0x8c
93 #define AR40XX_STATS_TXABORTCOL 0x90
94 #define AR40XX_STATS_TXMULTICOL 0x94
95 #define AR40XX_STATS_TXSINGLECOL 0x98
96 #define AR40XX_STATS_TXEXCDEFER 0x9c
97 #define AR40XX_STATS_TXDEFER 0xa0
98 #define AR40XX_STATS_TXLATECOL 0xa4
100 #define AR40XX_REG_MODULE_EN 0x030
101 #define AR40XX_MODULE_EN_MIB BIT(0)
103 #define AR40XX_REG_MIB_FUNC 0x034
108 #define AR40XX_MIB_FUNC_NO_OP 0x0
109 #define AR40XX_MIB_FUNC_FLUSH 0x1
111 #define AR40XX_ESS_SERVICE_TAG 0x48
114 #define AR40XX_REG_SW_MAC_ADDR0 0x60
117 #define AR40XX_REG_SW_MAC_ADDR0_BYTE5 BITS(0, 8)
118 #define AR40XX_REG_SW_MAC_ADDR0_BYTE5_S 0
120 #define AR40XX_REG_SW_MAC_ADDR1 0x64
127 #define AR40XX_REG_SW_MAC_ADDR1_BYTE3 BITS(0, 8)
128 #define AR40XX_REG_SW_MAC_ADDR1_BYTE3_S 0
130 #define AR40XX_REG_MAX_FRAME_SIZE 0x078
131 #define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
133 #define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
134 #define AR40XX_PORT_SPEED BITS(0, 2)
135 #define AR40XX_PORT_STATUS_SPEED_S 0
146 #define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
148 #define AR40XX_REG_EEE_CTRL 0x100
151 #define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
152 #define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
153 #define AR40XX_PORT_VLAN0_DEF_SVID_S 0
157 #define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
163 #define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
168 #define AR40XX_REG_ATU_DATA0 0x600
169 #define AR40XX_ATU_DATA0_MAC_ADDR3 BITS(0, 8)
170 #define AR40XX_ATU_DATA0_MAC_ADDR3_S 0
178 #define AR40XX_REG_ATU_DATA1 0x604
179 #define AR40XX_ATU_DATA1_MAC_ADDR4 BITS(0, 8)
180 #define AR40XX_ATU_DATA1_MAC_ADDR4_S 0
193 #define AR40XX_REG_ATU_DATA2 0x608
194 #define AR40XX_ATU_FUNC_DATA2_STATUS BITS(0, 4)
195 #define AR40XX_ATU_FUNC_DATA2_STATUS_S 0
203 #define AR40XX_REG_ATU_FUNC 0x60c
204 #define AR40XX_ATU_FUNC_OP BITS(0, 4)
205 #define AR40XX_ATU_FUNC_OP_NOOP 0x0
206 #define AR40XX_ATU_FUNC_OP_FLUSH 0x1
207 #define AR40XX_ATU_FUNC_OP_LOAD 0x2
208 #define AR40XX_ATU_FUNC_OP_PURGE 0x3
209 #define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
210 #define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
211 #define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
212 #define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
213 #define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
220 #define AR40XX_REG_VTU_FUNC0 0x0610
223 #define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
230 #define AR40XX_REG_VTU_FUNC1 0x0614
231 #define AR40XX_VTU_FUNC1_OP BITS(0, 3)
232 #define AR40XX_VTU_FUNC1_OP_NOOP 0
246 #define AR40XX_REG_FWD_CTRL0 0x620
251 #define AR40XX_REG_FWD_CTRL1 0x624
252 #define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
253 #define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
261 #define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
262 #define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
271 #define AR40XX_REG_QM_DEBUG_ADDR 0x820
272 #define AR40XX_REG_QM_DEBUG_VALUE 0x824
273 #define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
274 #define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
276 #define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
279 #define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
280 #define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
281 #define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
283 #define AR40XX_PHY_DEBUG_0 0
288 #define AR40XX_PHY_SPEC_STATUS 0x11
295 AR40XX_PORT_STATE_DISABLED = 0,
304 AR40XX_IN_PORT_ONLY = 0,
312 AR40XX_OUT_KEEP = 0,
319 AR40XX_PORT_SPEED_10M = 0,
329 #define AR40XX_MIB_FUNC_CAPTURE 0x3
331 #define AR40XX_REG_PORT_STATS_START 0x1000
332 #define AR40XX_REG_PORT_STATS_LEN 0x100
334 #define AR40XX_PORTS_ALL 0x3f
338 #define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
339 #define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
340 #define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
341 #define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
342 #define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
343 #define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
344 #define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
345 #define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a