88 	    0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE);  in ar40xx_hw_psgmii_reg_write()
97 	    0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ);  in ar40xx_hw_psgmii_reg_read()
109 		    0x2200);  in ar40xx_hw_psgmii_set_mac_mode()
111 		    0x8380);  in ar40xx_hw_psgmii_set_mac_mode()
117 	return (0);  in ar40xx_hw_psgmii_set_mac_mode()
130 	MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x9000);  in ar40xx_hw_psgmii_single_phy_testing()
131 	MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x4140);  in ar40xx_hw_psgmii_single_phy_testing()
133 	for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {  in ar40xx_hw_psgmii_single_phy_testing()
136 	status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11);  in ar40xx_hw_psgmii_single_phy_testing()
151 	ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0000);  in ar40xx_hw_psgmii_single_phy_testing()
152 	ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0003);  in ar40xx_hw_psgmii_single_phy_testing()
155 	ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8020, 0xa000);  in ar40xx_hw_psgmii_single_phy_testing()
163 	tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e);  in ar40xx_hw_psgmii_single_phy_testing()
164 	tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d);  in ar40xx_hw_psgmii_single_phy_testing()
165 	tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f);  in ar40xx_hw_psgmii_single_phy_testing()
166 	rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b);  in ar40xx_hw_psgmii_single_phy_testing()
167 	rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a);  in ar40xx_hw_psgmii_single_phy_testing()
168 	rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c);  in ar40xx_hw_psgmii_single_phy_testing()
172 	if (tx_all_ok == 0x1000 && tx_error == 0) {  in ar40xx_hw_psgmii_single_phy_testing()
184 	MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x1840);  in ar40xx_hw_psgmii_single_phy_testing()
185 	return (0);  in ar40xx_hw_psgmii_single_phy_testing()
193 	MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x9000);  in ar40xx_hw_psgmii_all_phy_testing()
194 	MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x4140);  in ar40xx_hw_psgmii_all_phy_testing()
196 	for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {  in ar40xx_hw_psgmii_all_phy_testing()
197 		for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {  in ar40xx_hw_psgmii_all_phy_testing()
200 			status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11);  in ar40xx_hw_psgmii_all_phy_testing()
212 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8029, 0x0000);  in ar40xx_hw_psgmii_all_phy_testing()
213 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8029, 0x0003);  in ar40xx_hw_psgmii_all_phy_testing()
216 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8020, 0xa000);  in ar40xx_hw_psgmii_all_phy_testing()
223 	for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {  in ar40xx_hw_psgmii_all_phy_testing()
231 		tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e);  in ar40xx_hw_psgmii_all_phy_testing()
232 		tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d);  in ar40xx_hw_psgmii_all_phy_testing()
233 		tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f);  in ar40xx_hw_psgmii_all_phy_testing()
234 		rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b);  in ar40xx_hw_psgmii_all_phy_testing()
235 		rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a);  in ar40xx_hw_psgmii_all_phy_testing()
236 		rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c);  in ar40xx_hw_psgmii_all_phy_testing()
240 		if (tx_all_ok == 0x1000 && tx_error == 0) {  in ar40xx_hw_psgmii_all_phy_testing()
252 	device_printf(sc->sc_dev, "PHY all test 0x%x\n",  in ar40xx_hw_psgmii_all_phy_testing()
254 	return (0);  in ar40xx_hw_psgmii_all_phy_testing()
268 	MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x005b);  in ar40xx_hw_malibu_psgmii_ess_reset()
270 	MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x001b);  in ar40xx_hw_malibu_psgmii_ess_reset()
272 	MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x005b);  in ar40xx_hw_malibu_psgmii_ess_reset()
274 	for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {  in ar40xx_hw_malibu_psgmii_ess_reset()
277 		status = ar40xx_hw_phy_mmd_read(sc, 5, 1, 0x28);  in ar40xx_hw_malibu_psgmii_ess_reset()
278 		if (status & (1U << 0))  in ar40xx_hw_malibu_psgmii_ess_reset()
293 	MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x1a, 0x2230);  in ar40xx_hw_malibu_psgmii_ess_reset()
298 	for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {  in ar40xx_hw_malibu_psgmii_ess_reset()
301 		status = ar40xx_hw_psgmii_reg_read(sc, 0xa0);  in ar40xx_hw_malibu_psgmii_ess_reset()
302 		if (status & (1U << 0))  in ar40xx_hw_malibu_psgmii_ess_reset()
312 	MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x1a, 0x3230);  in ar40xx_hw_malibu_psgmii_ess_reset()
314 	MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x005f);  in ar40xx_hw_malibu_psgmii_ess_reset()
316 	return (0);  in ar40xx_hw_malibu_psgmii_ess_reset()
329 	MDIO_WRITEREG(sc->sc_mdio_dev, 4, 0x1f, 0x8500);  in ar40xx_hw_psgmii_self_test()
330 	for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {  in ar40xx_hw_psgmii_self_test()
332 		ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x801f);  in ar40xx_hw_psgmii_self_test()
336 	MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x1840);  in ar40xx_hw_psgmii_self_test()
339 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8021, 0x1000);  in ar40xx_hw_psgmii_self_test()
340 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8062, 0x05e0);  in ar40xx_hw_psgmii_self_test()
343 	MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x10, 0x6800);  in ar40xx_hw_psgmii_self_test()
344 	for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {  in ar40xx_hw_psgmii_self_test()
345 		sc->sc_psgmii.phy_t_status = 0;  in ar40xx_hw_psgmii_self_test()
347 		for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {  in ar40xx_hw_psgmii_self_test()
358 		for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)  in ar40xx_hw_psgmii_self_test()
377 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8021, 0x0);  in ar40xx_hw_psgmii_self_test()
379 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8029, 0x0);  in ar40xx_hw_psgmii_self_test()
381 	ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8020, 0x0);  in ar40xx_hw_psgmii_self_test()
383 	return (0);  in ar40xx_hw_psgmii_self_test()
395 	MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x10, 0x6860);  in ar40xx_hw_psgmii_self_test_clean()
396 	MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x9040);  in ar40xx_hw_psgmii_self_test_clean()
398         for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {  in ar40xx_hw_psgmii_self_test_clean()
406 		ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x001f);  in ar40xx_hw_psgmii_self_test_clean()
412 	return (0);  in ar40xx_hw_psgmii_self_test_clean()
428 	reg = ar40xx_hw_psgmii_reg_read(sc, 0x78c);  in ar40xx_hw_psgmii_init_config()
430 	    "%s: PSGMIIPHY_PLL_VCO_RELATED_CTRL=0x%08x\n", __func__, reg);  in ar40xx_hw_psgmii_init_config()
432 	reg = ar40xx_hw_psgmii_reg_read(sc, 0x09c);  in ar40xx_hw_psgmii_init_config()
434 	    "%s: PSGMIIPHY_VCO_CALIBRATION_CTRL=0x%08x\n", __func__, reg);  in ar40xx_hw_psgmii_init_config()
436 	return (0);  in ar40xx_hw_psgmii_init_config()