Lines Matching +full:0 +full:x00000400
57 #define ET_PCIR_DEVICE_CAPS 0x4C
58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
62 #define ET_PCIR_DEVICE_CTRL 0x50
63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
66 #define ET_PCIR_MAC_ADDR0 0xA4
67 #define ET_PCIR_MAC_ADDR1 0xA8
69 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */
70 #define ET_PCIM_EEPROM_STATUS_ERROR 0x4C
72 #define ET_PCIR_ACK_LATENCY 0xC0
76 #define ET_PCIR_REPLAY_TIMER 0xC2
81 #define ET_PCIR_L0S_L1_LATENCY 0xCF
86 #define ET_TXQUEUE_START 0x0000
87 #define ET_TXQUEUE_END 0x0004
88 #define ET_RXQUEUE_START 0x0008
89 #define ET_RXQUEUE_END 0x000C
91 #define ET_QUEUE_ADDR_START 0
94 #define ET_PM 0x0010
95 #define EM_PM_GIGEPHY_ENB 0x00000001
96 #define ET_PM_SYSCLK_GATE 0x00000008
97 #define ET_PM_TXCLK_GATE 0x00000010
98 #define ET_PM_RXCLK_GATE 0x00000020
99 #define ET_PM_PHY_SW_COMA 0x00000040
101 #define ET_INTR_STATUS 0x0018
102 #define ET_INTR_MASK 0x001C
104 #define ET_SWRST 0x0028
105 #define ET_SWRST_TXDMA 0x00000001
106 #define ET_SWRST_RXDMA 0x00000002
107 #define ET_SWRST_TXMAC 0x00000004
108 #define ET_SWRST_RXMAC 0x00000008
109 #define ET_SWRST_MAC 0x00000010
110 #define ET_SWRST_MAC_STAT 0x00000020
111 #define ET_SWRST_MMC 0x00000040
112 #define ET_SWRST_SELFCLR_DISABLE 0x80000000
114 #define ET_MSI_CFG 0x0030
116 #define ET_LOOPBACK 0x0034
118 #define ET_TIMER 0x0038
120 #define ET_TXDMA_CTRL 0x1000
121 #define ET_TXDMA_CTRL_HALT 0x00000001
122 #define ET_TXDMA_CTRL_CACHE_THR_MASK 0x000000F0
123 #define ET_TXDMA_CTRL_SINGLE_EPKT 0x00000100 /* ??? */
125 #define ET_TX_RING_HI 0x1004
126 #define ET_TX_RING_LO 0x1008
127 #define ET_TX_RING_CNT 0x100C
129 #define ET_TX_STATUS_HI 0x101C
130 #define ET_TX_STATUS_LO 0x1020
132 #define ET_TX_READY_POS 0x1024
133 #define ET_TX_READY_POS_INDEX_MASK 0x000003FF
134 #define ET_TX_READY_POS_WRAP 0x00000400
136 #define ET_TX_DONE_POS 0x1060
137 #define ET_TX_DONE_POS_INDEX_MASK 0x0000003FF
138 #define ET_TX_DONE_POS_WRAP 0x000000400
140 #define ET_RXDMA_CTRL 0x2000
141 #define ET_RXDMA_CTRL_HALT 0x00000001
142 #define ET_RXDMA_CTRL_RING0_SIZE_MASK 0x00000300
143 #define ET_RXDMA_CTRL_RING0_128 0x00000000 /* 127 */
144 #define ET_RXDMA_CTRL_RING0_256 0x00000100 /* 255 */
145 #define ET_RXDMA_CTRL_RING0_512 0x00000200 /* 511 */
146 #define ET_RXDMA_CTRL_RING0_1024 0x00000300 /* 1023 */
147 #define ET_RXDMA_CTRL_RING0_ENABLE 0x00000400
148 #define ET_RXDMA_CTRL_RING1_SIZE_MASK 0x00001800
149 #define ET_RXDMA_CTRL_RING1_2048 0x00000000 /* 2047 */
150 #define ET_RXDMA_CTRL_RING1_4096 0x00000800 /* 4095 */
151 #define ET_RXDMA_CTRL_RING1_8192 0x00001000 /* 8191 */
152 #define ET_RXDMA_CTRL_RING1_16384 0x00001800 /* 16383 (9022?) */
153 #define ET_RXDMA_CTRL_RING1_ENABLE 0x00002000
154 #define ET_RXDMA_CTRL_HALTED 0x00020000
156 #define ET_RX_STATUS_LO 0x2004
157 #define ET_RX_STATUS_HI 0x2008
159 #define ET_RX_INTR_NPKTS 0x200C
160 #define ET_RX_INTR_DELAY 0x2010
162 #define ET_RXSTAT_LO 0x2020
163 #define ET_RXSTAT_HI 0x2024
164 #define ET_RXSTAT_CNT 0x2028
166 #define ET_RXSTAT_POS 0x2030
167 #define ET_RXSTAT_POS_INDEX_MASK 0x00000FFF
168 #define ET_RXSTAT_POS_WRAP 0x00001000
170 #define ET_RXSTAT_MINCNT 0x2038
172 #define ET_RX_RING0_LO 0x203C
173 #define ET_RX_RING0_HI 0x2040
174 #define ET_RX_RING0_CNT 0x2044
176 #define ET_RX_RING0_POS 0x204C
177 #define ET_RX_RING0_POS_INDEX_MASK 0x000003FF
178 #define ET_RX_RING0_POS_WRAP 0x00000400
180 #define ET_RX_RING0_MINCNT 0x2054
182 #define ET_RX_RING1_LO 0x2058
183 #define ET_RX_RING1_HI 0x205C
184 #define ET_RX_RING1_CNT 0x2060
186 #define ET_RX_RING1_POS 0x2068
187 #define ET_RX_RING1_POS_INDEX 0x000003FF
188 #define ET_RX_RING1_POS_WRAP 0x00000400
190 #define ET_RX_RING1_MINCNT 0x2070
192 #define ET_TXMAC_CTRL 0x3000
193 #define ET_TXMAC_CTRL_ENABLE 0x00000001
194 #define ET_TXMAC_CTRL_FC_DISABLE 0x00000008
196 #define ET_TXMAC_FLOWCTRL 0x3010
197 #define ET_TXMAC_FLOWCTRL_CFPT_MASK 0x0000FFFF
198 #define ET_TXMAC_FLOWCTRL_CFEP_MASK 0xFFFF0000
199 #define ET_TXMAC_FLOWCTRL_CFPT_SHIFT 0
201 #define ET_TXMAC_BP_CTRL 0x3020
202 #define ET_TXMAC_BP_CTRL_XONXOFF 0x00000001
203 #define ET_TXMAC_BP_CTRL_REQ 0x00000002
205 #define ET_RXMAC_CTRL 0x4000
206 #define ET_RXMAC_CTRL_ENABLE 0x00000001
207 #define ET_RXMAC_CTRL_NO_PKTFILT 0x00000004
208 #define ET_RXMAC_CTRL_WOL_DISABLE 0x00000008
210 #define ET_WOL_CRC 0x4004
211 #define ET_WOL_SA_LO 0x4010
212 #define ET_WOL_SA_HI 0x4014
213 #define ET_WOL_MASK 0x4018
215 #define ET_UCAST_FILTADDR1 0x4068
216 #define ET_UCAST_FILTADDR2 0x406C
217 #define ET_UCAST_FILTADDR3 0x4070
219 #define ET_MULTI_HASH 0x4074
221 #define ET_PKTFILT 0x4084
222 #define ET_PKTFILT_BCAST 0x00000001
223 #define ET_PKTFILT_MCAST 0x00000002
224 #define ET_PKTFILT_UCAST 0x00000004
225 #define ET_PKTFILT_FRAG 0x00000008
226 #define ET_PKTFILT_MINLEN_MASK 0x007F0000
229 #define ET_RXMAC_MC_SEGSZ 0x4088
230 #define ET_RXMAC_MC_SEGSZ_ENABLE 0x00000001
231 #define ET_RXMAC_MC_SEGSZ_FC 0x00000002
232 #define ET_RXMAC_MC_SEGSZ_MAX_MASK 0x000003FC
236 #define ET_RXMAC_MC_WATERMARK 0x408C
237 #define ET_RXMAC_SPACE_AVL 0x4094
239 #define ET_RXMAC_MGT 0x4098
240 #define ET_RXMAC_MGT_PASS_ECRC 0x00000010
241 #define ET_RXMAC_MGT_PASS_ELEN 0x00000020
242 #define ET_RXMAC_MGT_PASS_ETRUNC 0x00010000
243 #define ET_RXMAC_MGT_CHECK_PKT 0x00020000
245 #define ET_MAC_CFG1 0x5000
246 #define ET_MAC_CFG1_TXEN 0x00000001
247 #define ET_MAC_CFG1_SYNC_TXEN 0x00000002
248 #define ET_MAC_CFG1_RXEN 0x00000004
249 #define ET_MAC_CFG1_SYNC_RXEN 0x00000008
250 #define ET_MAC_CFG1_TXFLOW 0x00000010
251 #define ET_MAC_CFG1_RXFLOW 0x00000020
252 #define ET_MAC_CFG1_LOOPBACK 0x00000100
253 #define ET_MAC_CFG1_RST_TXFUNC 0x00010000
254 #define ET_MAC_CFG1_RST_RXFUNC 0x00020000
255 #define ET_MAC_CFG1_RST_TXMC 0x00040000
256 #define ET_MAC_CFG1_RST_RXMC 0x00080000
257 #define ET_MAC_CFG1_SIM_RST 0x40000000
258 #define ET_MAC_CFG1_SOFT_RST 0x80000000
260 #define ET_MAC_CFG2 0x5004
261 #define ET_MAC_CFG2_FDX 0x00000001
262 #define ET_MAC_CFG2_CRC 0x00000002
263 #define ET_MAC_CFG2_PADCRC 0x00000004
264 #define ET_MAC_CFG2_LENCHK 0x00000010
265 #define ET_MAC_CFG2_BIGFRM 0x00000020
266 #define ET_MAC_CFG2_MODE_MII 0x00000100
267 #define ET_MAC_CFG2_MODE_GMII 0x00000200
268 #define ET_MAC_CFG2_PREAMBLE_LEN_MASK 0x0000F000
271 #define ET_IPG 0x5008
272 #define ET_IPG_B2B_MASK 0x0000007F
273 #define ET_IPG_MINIFG_MASK 0x0000FF00
274 #define ET_IPG_NONB2B_2_MASK 0x007F0000
275 #define ET_IPG_NONB2B_1_MASK 0x7F000000
276 #define ET_IPG_B2B_SHIFT 0
281 #define ET_MAC_HDX 0x500C
282 #define ET_MAC_HDX_COLLWIN_MASK 0x000003FF
283 #define ET_MAC_HDX_REXMIT_MAX_MASK 0x0000F000
284 #define ET_MAC_HDX_EXC_DEFER 0x00010000
285 #define ET_MAC_HDX_NOBACKOFF 0x00020000
286 #define ET_MAC_HDX_BP_NOBACKOFF 0x00040000
287 #define ET_MAC_HDX_ALT_BEB 0x00080000
288 #define ET_MAC_HDX_ALT_BEB_TRUNC_MASK 0x00F00000
289 #define ET_MAC_HDX_COLLWIN_SHIFT 0
293 #define ET_MAX_FRMLEN 0x5010
295 #define ET_MII_CFG 0x5020
296 #define ET_MII_CFG_CLKRST 0x00000007
297 #define ET_MII_CFG_PREAMBLE_SUP 0x00000010
298 #define ET_MII_CFG_SCAN_AUTOINC 0x00000020
299 #define ET_MII_CFG_RST 0x80000000
301 #define ET_MII_CMD 0x5024
302 #define ET_MII_CMD_READ 0x00000001
304 #define ET_MII_ADDR 0x5028
305 #define ET_MII_ADDR_REG_MASK 0x0000001F
306 #define ET_MII_ADDR_PHY_MASK 0x00001F00
307 #define ET_MII_ADDR_REG_SHIFT 0
310 #define ET_MII_CTRL 0x502C
311 #define ET_MII_CTRL_VALUE_MASK 0x0000FFFF
312 #define ET_MII_CTRL_VALUE_SHIFT 0
314 #define ET_MII_STAT 0x5030
315 #define ET_MII_STAT_VALUE_MASK 0x0000FFFF
317 #define ET_MII_IND 0x5034
318 #define ET_MII_IND_BUSY 0x00000001
319 #define ET_MII_IND_INVALID 0x00000004
321 #define ET_MAC_CTRL 0x5038
322 #define ET_MAC_CTRL_MODE_MII 0x01000000
323 #define ET_MAC_CTRL_LHDX 0x02000000
324 #define ET_MAC_CTRL_GHDX 0x04000000
326 #define ET_MAC_ADDR1 0x5040
327 #define ET_MAC_ADDR2 0x5044
330 #define ET_STAT_PKTS_64 0x6080
331 #define ET_STAT_PKTS_65_127 0x6084
332 #define ET_STAT_PKTS_128_255 0x6088
333 #define ET_STAT_PKTS_256_511 0x608C
334 #define ET_STAT_PKTS_512_1023 0x6090
335 #define ET_STAT_PKTS_1024_1518 0x6094
336 #define ET_STAT_PKTS_1519_1522 0x6098
337 #define ET_STAT_RX_BYTES 0x609C
338 #define ET_STAT_RX_FRAMES 0x60A0
339 #define ET_STAT_RX_CRC_ERR 0x60A4
340 #define ET_STAT_RX_MCAST 0x60A8
341 #define ET_STAT_RX_BCAST 0x60AC
342 #define ET_STAT_RX_CTL 0x60B0
343 #define ET_STAT_RX_PAUSE 0x60B4
344 #define ET_STAT_RX_UNKNOWN_CTL 0x60B8
345 #define ET_STAT_RX_ALIGN_ERR 0x60BC
346 #define ET_STAT_RX_LEN_ERR 0x60C0
347 #define ET_STAT_RX_CODE_ERR 0x60C4
348 #define ET_STAT_RX_CS_ERR 0x60C8
349 #define ET_STAT_RX_RUNT 0x60CC
350 #define ET_STAT_RX_OVERSIZE 0x60D0
351 #define ET_STAT_RX_FRAG 0x60D4
352 #define ET_STAT_RX_JABBER 0x60D8
353 #define ET_STAT_RX_DROP 0x60DC
354 #define ET_STAT_TX_BYTES 0x60E0
355 #define ET_STAT_TX_FRAMES 0x60E4
356 #define ET_STAT_TX_MCAST 0x60E8
357 #define ET_STAT_TX_BCAST 0x60EC
358 #define ET_STAT_TX_PAUSE 0x60F0
359 #define ET_STAT_TX_DEFER 0x60F4
360 #define ET_STAT_TX_EXCESS_DEFER 0x60F8
361 #define ET_STAT_TX_SINGLE_COL 0x60FC
362 #define ET_STAT_TX_MULTI_COL 0x6100
363 #define ET_STAT_TX_LATE_COL 0x6104
364 #define ET_STAT_TX_EXCESS_COL 0x6108
365 #define ET_STAT_TX_TOTAL_COL 0x610C
366 #define ET_STAT_TX_PAUSE_HONOR 0x6110
367 #define ET_STAT_TX_DROP 0x6114
368 #define ET_STAT_TX_JABBER 0x6118
369 #define ET_STAT_TX_CRC_ERR 0x611C
370 #define ET_STAT_TX_CTL 0x6120
371 #define ET_STAT_TX_OVERSIZE 0x6124
372 #define ET_STAT_TX_UNDERSIZE 0x6128
373 #define ET_STAT_TX_FRAG 0x612C
375 #define ET_MMC_CTRL 0x7000
376 #define ET_MMC_CTRL_ENABLE 0x00000001
377 #define ET_MMC_CTRL_ARB_DISABLE 0x00000002
378 #define ET_MMC_CTRL_RXMAC_DISABLE 0x00000004
379 #define ET_MMC_CTRL_TXMAC_DISABLE 0x00000008
380 #define ET_MMC_CTRL_TXDMA_DISABLE 0x00000010
381 #define ET_MMC_CTRL_RXDMA_DISABLE 0x00000020
382 #define ET_MMC_CTRL_FORCE_CE 0x00000040
387 #define ET_INTR_TXDMA 0x00000008
388 #define ET_INTR_TXDMA_ERROR 0x00000010
389 #define ET_INTR_RXDMA 0x00000020
390 #define ET_INTR_RXRING0_LOW 0x00000040
391 #define ET_INTR_RXRING1_LOW 0x00000080
392 #define ET_INTR_RXSTAT_LOW 0x00000100
393 #define ET_INTR_RXDMA_ERROR 0x00000200
394 #define ET_INTR_TIMER 0x00004000
395 #define ET_INTR_WOL 0x00008000
396 #define ET_INTR_PHY 0x00010000
397 #define ET_INTR_TXMAC 0x00020000
398 #define ET_INTR_RXMAC 0x00040000
399 #define ET_INTR_MAC_STATS 0x00080000
400 #define ET_INTR_SLAVE_TO 0x00100000
409 #define ET_RX_RING_POS_INDEX_MASK 0x000003FF
410 #define ET_RX_RING_POS_WRAP 0x00000400
415 #define PCI_VENDOR_LUCENT 0x11C1
416 #define PCI_PRODUCT_LUCENT_ET1310 0xED00 /* ET1310 10/100/1000M Ethernet */
417 #define PCI_PRODUCT_LUCENT_ET1310_FAST 0xED01 /* ET1310 10/100M Ethernet */