Lines Matching +full:0 +full:x0c10
38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
67 #define GMAC_MAC_RX_FLOW_CTRL 0x0090
68 #define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0)
69 #define GMAC_RXQ_CTRL0 0x00A0
70 #define GMAC_RXQ_CTRL0_EN_MASK 0x3
71 #define GMAC_RXQ_CTRL0_EN_DCB 0x2
72 #define GMAC_RXQ_CTRL1 0x00A4
73 #define GMAC_MAC_INTERRUPT_STATUS 0x00B0
74 #define GMAC_MAC_INTERRUPT_ENABLE 0x00B4
75 #define GMAC_MAC_RX_TX_STATUS 0x00B8
82 #define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0)
83 #define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0
84 #define GMAC_MAC_RWK_PACKET_FILTER 0x00C4
85 #define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0
86 #define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4
87 #define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8
88 #define GMAC_MAC_1US_TIC_COUNTER 0x00DC
89 #define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8
90 #define GMAC_MAC_VERSION 0x0110
92 #define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT)
93 #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU
94 #define GMAC_MAC_DEBUG 0x0114
95 #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n))
97 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
98 #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
99 #define GMAC_MAC_MDIO_ADDRESS 0x0200
103 #define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
104 #define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
117 #define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0)
118 #define GMAC_MAC_MDIO_DATA 0x0204
119 #define GMAC_MAC_CSR_SW_CTRL 0x0230
120 #define GMAC_MAC_ADDRESS0_HIGH 0x0300
121 #define GMAC_MAC_ADDRESS0_LOW 0x0304
122 #define GMAC_MMC_CONTROL 0x0700
129 #define GMAC_MMC_CONTROL_CNTRST (1U << 0)
130 #define GMAC_MMC_RX_INTERRUPT 0x0704
131 #define GMAC_MMC_TX_INTERRUPT 0x0708
132 #define GMAC_MMC_RX_INTERRUPT_MASK 0x070C
133 #define GMAC_MMC_TX_INTERRUPT_MASK 0x0710
134 #define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714
135 #define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718
136 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748
137 #define GMAC_TX_CARRIER_ERROR_PACKETS 0x0760
138 #define GMAC_TX_OCTET_COUNT_GOOD 0x0764
139 #define GMAC_TX_PACKET_COUNT_GOOD 0x0768
140 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD 0x0780
141 #define GMAC_RX_OCTET_COUNT_GOOD_BAD 0x0784
142 #define GMAC_RX_OCTET_COUNT_GOOD 0x0788
143 #define GMAC_RX_MULTICAST_PACKETS_GOOD 0x0790
144 #define GMAC_RX_CRC_ERROR_PACKETS 0x0794
145 #define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8
146 #define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4
147 #define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800
148 #define GMAC_MMC_IPC_RX_INTERRUPT 0x0808
149 #define GMAC_RXIPV4_GOOD_PACKETS 0x0810
150 #define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814
151 #define GMAC_RXIPV6_GOOD_PACKETS 0x0824
152 #define GMAC_RXIPV6_HEADER_ERROR_PACKETS 0x0828
153 #define GMAC_RXUDP_ERROR_PACKETS 0x0834
154 #define GMAC_RXTCP_ERROR_PACKETS 0x083C
155 #define GMAC_RXICMP_ERROR_PACKETS 0x0844
156 #define GMAC_RXIPV4_HEADER_ERROR_OCTETS 0x0854
157 #define GMAC_RXIPV6_HEADER_ERROR_OCTETS 0x0868
158 #define GMAC_RXUDP_ERROR_OCTETS 0x0874
159 #define GMAC_RXTCP_ERROR_OCTETS 0x087C
160 #define GMAC_RXICMP_ERROR_OCTETS 0x0884
161 #define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00
162 #define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04
163 #define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08
164 #define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C
165 #define GMAC_MAC_SYS_TIME_SECS_UPDATE 0x0B10
166 #define GMAC_MAC_SYS_TIME_NS_UPDATE 0x0B14
167 #define GMAC_MAC_TIMESTAMP_ADDEND 0x0B18
168 #define GMAC_MAC_TIMESTAMP_STATUS 0x0B20
169 #define GMAC_MAC_TX_TS_STATUS_NS 0x0B30
170 #define GMAC_MAC_TX_TS_STATUS_SECS 0x0B34
171 #define GMAC_MAC_AUXILIARY_CONTROL 0x0B40
172 #define GMAC_MAC_AUXILIARY_TS_NS 0x0B48
173 #define GMAC_MAC_AUXILIARY_TS_SECS 0x0B4C
174 #define GMAC_MAC_TS_INGRESS_CORR_NS 0x0B58
175 #define GMAC_MAC_TS_EGRESS_CORR_NS 0x0B5C
176 #define GMAC_MAC_TS_INGRESS_LATENCY 0x0B68
177 #define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C
178 #define GMAC_MAC_PPS_CONTROL 0x0B70
179 #define GMAC_MTL_DBG_CTL 0x0C08
180 #define GMAC_MTL_DBG_STS 0x0C0C
181 #define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10
182 #define GMAC_MTL_INTERRUPT_STATUS 0x0C20
184 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0)
185 #define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00
187 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
190 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0)
191 #define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04
192 #define GMAC_MTL_TXQ0_DEBUG 0x0D08
193 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C
197 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0)
198 #define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30
202 #define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34
203 #define GMAC_MTL_RXQ0_DEBUG 0x0D38
204 #define GMAC_DMA_MODE 0x1000
205 #define GMAC_DMA_MODE_SWR (1U << 0)
206 #define GMAC_DMA_SYSBUS_MODE 0x1004
208 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)
210 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)
216 #define GMAC_DMA_SYSBUS_MODE_FB (1U << 0)
217 #define GMAC_DMA_INTERRUPT_STATUS 0x1008
218 #define GMAC_DMA_DEBUG_STATUS0 0x100C
219 #define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040
220 #define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n))
221 #define GMAC_RWK_FILTER01_CRC 0x10D0
222 #define GMAC_RWK_FILTER23_CRC 0x10D4
223 #define GMAC_RWK_FILTER_OFFSET 0x10D8
224 #define GMAC_RWK_FILTER_COMMAND 0x10DC
225 #define GMAC_DMA_CHAN0_CONTROL 0x1100
227 #define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT)
229 #define GMAC_DMA_CHAN0_TX_CONTROL 0x1104
231 #define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0)
232 #define GMAC_DMA_CHAN0_RX_CONTROL 0x1108
234 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT)
235 #define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0)
236 #define GMAC_DMA_CHAN0_TX_BASE_ADDR_HI 0x1110
237 #define GMAC_DMA_CHAN0_TX_BASE_ADDR 0x1114
238 #define GMAC_DMA_CHAN0_RX_BASE_ADDR_HI 0x1118
239 #define GMAC_DMA_CHAN0_RX_BASE_ADDR 0x111C
240 #define GMAC_DMA_CHAN0_TX_END_ADDR 0x1120
241 #define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128
242 #define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C
243 #define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130
244 #define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134
257 #define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0)
258 #define GMAC_DMA_CHAN0_RX_WATCHDOG 0x1138
259 #define GMAC_DMA_CHAN0_SLOT_CTRL_STATUS 0x113C
260 #define GMAC_DMA_CHAN0_CUR_TX_DESC 0x1144
261 #define GMAC_DMA_CHAN0_CUR_RX_DESC 0x114C
262 #define GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR 0x1154
263 #define GMAC_DMA_CHAN0_CUR_RX_BUF_ADDR 0x115C
264 #define GMAC_DMA_CHAN0_STATUS 0x1160
277 #define GMAC_DMA_CHAN0_STATUS_TI (1U << 0)
293 #define EQOS_RDES3_LENGTH_MASK 0x7FFFU