Lines Matching +full:- +full:u
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
28 * $Id: eqos_reg.h 921 2022-08-09 18:38:11Z sos $
32 * DesignWare Ethernet Quality-of-Service controller
39 #define GMAC_MAC_CONFIGURATION_CST (1U << 21)
40 #define GMAC_MAC_CONFIGURATION_ACS (1U << 20)
41 #define GMAC_MAC_CONFIGURATION_BE (1U << 18)
42 #define GMAC_MAC_CONFIGURATION_JD (1U << 17)
43 #define GMAC_MAC_CONFIGURATION_JE (1U << 16)
44 #define GMAC_MAC_CONFIGURATION_PS (1U << 15)
45 #define GMAC_MAC_CONFIGURATION_FES (1U << 14)
46 #define GMAC_MAC_CONFIGURATION_DM (1U << 13)
47 #define GMAC_MAC_CONFIGURATION_DCRS (1U << 9)
48 #define GMAC_MAC_CONFIGURATION_TE (1U << 1)
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
52 #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10)
53 #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6)
54 #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6)
55 #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5)
56 #define GMAC_MAC_PACKET_FILTER_PM (1U << 4)
57 #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2)
58 #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1)
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
66 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1)
68 #define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0)
76 #define GMAC_MAC_RX_TX_STATUS_RWT (1U << 8)
77 #define GMAC_MAC_RX_TX_STATUS_EXCOL (1U << 5)
78 #define GMAC_MAC_RX_TX_STATUS_LCOL (1U << 4)
79 #define GMAC_MAC_RX_TX_STATUS_EXDEF (1U << 3)
80 #define GMAC_MAC_RX_TX_STATUS_LCARR (1U << 2)
81 #define GMAC_MAC_RX_TX_STATUS_NCARR (1U << 1)
82 #define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0)
104 #define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
105 #define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
106 #define GMAC_MAC_MDIO_ADDRESS_CR_20_35 (2U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
107 #define GMAC_MAC_MDIO_ADDRESS_CR_35_60 (3U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
108 #define GMAC_MAC_MDIO_ADDRESS_CR_150_250 (4U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
109 #define GMAC_MAC_MDIO_ADDRESS_CR_250_300 (5U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
110 #define GMAC_MAC_MDIO_ADDRESS_CR_300_500 (6U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
111 #define GMAC_MAC_MDIO_ADDRESS_CR_500_800 (7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
112 #define GMAC_MAC_MDIO_ADDRESS_SKAP (1U << 4)
114 #define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
115 #define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
116 #define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1)
117 #define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0)
123 #define GMAC_MMC_CONTROL_UCDBC (1U << 8)
124 #define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5)
125 #define GMAC_MMC_CONTROL_CNTPRST (1U << 4)
126 #define GMAC_MMC_CONTROL_CNTFREEZ (1U << 3)
127 #define GMAC_MMC_CONTROL_RSTONRD (1U << 2)
128 #define GMAC_MMC_CONTROL_CNTSTOPRO (1U << 1)
129 #define GMAC_MMC_CONTROL_CNTRST (1U << 0)
183 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS (1U << 17)
184 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0)
188 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
189 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1)
190 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0)
194 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24)
195 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16)
196 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8)
197 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0)
199 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5)
200 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4)
201 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3)
205 #define GMAC_DMA_MODE_SWR (1U << 0)
211 #define GMAC_DMA_SYSBUS_MODE_MB (1U << 14)
212 #define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11)
213 #define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3)
214 #define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2)
215 #define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1)
216 #define GMAC_DMA_SYSBUS_MODE_FB (1U << 0)
228 #define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16)
230 #define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4)
231 #define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0)
235 #define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0)
246 #define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15)
247 #define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14)
248 #define GMAC_DMA_CHAN0_INTR_ENABLE_CDE (1U << 13)
249 #define GMAC_DMA_CHAN0_INTR_ENABLE_FBE (1U << 12)
250 #define GMAC_DMA_CHAN0_INTR_ENABLE_ERI (1U << 11)
251 #define GMAC_DMA_CHAN0_INTR_ENABLE_ETI (1U << 10)
252 #define GMAC_DMA_CHAN0_INTR_ENABLE_RWT (1U << 9)
253 #define GMAC_DMA_CHAN0_INTR_ENABLE_RPS (1U << 8)
254 #define GMAC_DMA_CHAN0_INTR_ENABLE_RBU (1U << 7)
255 #define GMAC_DMA_CHAN0_INTR_ENABLE_RIE (1U << 6)
256 #define GMAC_DMA_CHAN0_INTR_ENABLE_TPU (1U << 2)
257 #define GMAC_DMA_CHAN0_INTR_ENABLE_TPS (1U << 1)
258 #define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0)
266 #define GMAC_DMA_CHAN0_STATUS_NIS (1U << 15)
267 #define GMAC_DMA_CHAN0_STATUS_AIS (1U << 14)
268 #define GMAC_DMA_CHAN0_STATUS_CDE (1U << 13)
269 #define GMAC_DMA_CHAN0_STATUS_FB (1U << 12)
270 #define GMAC_DMA_CHAN0_STATUS_ERI (1U << 11)
271 #define GMAC_DMA_CHAN0_STATUS_ETI (1U << 10)
272 #define GMAC_DMA_CHAN0_STATUS_RWT (1U << 9)
273 #define GMAC_DMA_CHAN0_STATUS_RPS (1U << 8)
274 #define GMAC_DMA_CHAN0_STATUS_RBU (1U << 7)
275 #define GMAC_DMA_CHAN0_STATUS_RI (1U << 6)
276 #define GMAC_DMA_CHAN0_STATUS_TPU (1U << 2)
277 #define GMAC_DMA_CHAN0_STATUS_TPS (1U << 1)
278 #define GMAC_DMA_CHAN0_STATUS_TI (1U << 0)
280 #define EQOS_TDES2_IOC (1U << 31)
281 #define EQOS_TDES3_OWN (1U << 31)
282 #define EQOS_TDES3_FD (1U << 29)
283 #define EQOS_TDES3_LD (1U << 28)
284 #define EQOS_TDES3_DE (1U << 23)
285 #define EQOS_TDES3_OE (1U << 21)
286 #define EQOS_TDES3_ES (1U << 15)
288 #define EQOS_RDES3_OWN (1U << 31)
289 #define EQOS_RDES3_IOC (1U << 30)
290 #define EQOS_RDES3_BUF1V (1U << 24)
291 #define EQOS_RDES3_GP (1U << 23)
292 #define EQOS_RDES3_OE (1U << 21)
293 #define EQOS_RDES3_RE (1U << 20)