10 void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,  in vnic_cq_init()  argument
18 	paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;  in vnic_cq_init()
19 	ENIC_BUS_WRITE_8(cq->ctrl, CQ_RING_BASE, paddr);  in vnic_cq_init()
20 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_RING_SIZE, cq->ring.desc_count);  in vnic_cq_init()
21 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_FLOW_CONTROL_ENABLE, flow_control_enable);  in vnic_cq_init()
22 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_COLOR_ENABLE, color_enable);  in vnic_cq_init()
23 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, cq_head);  in vnic_cq_init()
24 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, cq_tail);  in vnic_cq_init()
25 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, cq_tail_color);  in vnic_cq_init()
26 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_ENABLE, interrupt_enable);  in vnic_cq_init()
27 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_ENTRY_ENABLE, cq_entry_enable);  in vnic_cq_init()
28 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_MESSAGE_ENABLE, cq_message_enable);  in vnic_cq_init()
29 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_OFFSET, interrupt_offset);  in vnic_cq_init()
30 	ENIC_BUS_WRITE_8(cq->ctrl, CQ_MESSAGE_ADDR, cq_message_addr);  in vnic_cq_init()
32 	cq->interrupt_offset = interrupt_offset;  in vnic_cq_init()
35 void vnic_cq_clean(struct vnic_cq *cq)  in vnic_cq_clean()  argument
37 	cq->to_clean = 0;  in vnic_cq_clean()
38 	cq->last_color = 0;  in vnic_cq_clean()
40 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, 0);  in vnic_cq_clean()
41 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, 0);  in vnic_cq_clean()
42 	ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, 1);  in vnic_cq_clean()