2986 	u32 rctl, rxdctl;  in em_flush_rx_ring()  local
2993 	rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));  in em_flush_rx_ring()
2995 	rxdctl &= 0xffffc000;  in em_flush_rx_ring()
3001 	rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);  in em_flush_rx_ring()
3002 	E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);  in em_flush_rx_ring()
3916 		u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));  in em_initialize_receive_unit()  local
3917 		E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);  in em_initialize_receive_unit()
3920 			u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));  in em_initialize_receive_unit()  local
3921 			rxdctl |= 0x20; /* PTHRESH */  in em_initialize_receive_unit()
3922 			rxdctl |= 4 << 8; /* HTHRESH */  in em_initialize_receive_unit()
3923 			rxdctl |= 4 << 16;/* WTHRESH */  in em_initialize_receive_unit()
3924 			rxdctl |= 1 << 24; /* Switch to granularity */  in em_initialize_receive_unit()
3925 			E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);  in em_initialize_receive_unit()
3963 			u32 rxdctl;  in em_initialize_receive_unit()  local
3981 			rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));  in em_initialize_receive_unit()
3982 			rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;  in em_initialize_receive_unit()
3983 			rxdctl &= 0xFFF00000;  in em_initialize_receive_unit()
3984 			rxdctl |= IGB_RX_PTHRESH;  in em_initialize_receive_unit()
3985 			rxdctl |= IGB_RX_HTHRESH << 8;  in em_initialize_receive_unit()
3986 			rxdctl |= IGB_RX_WTHRESH << 16;  in em_initialize_receive_unit()
3987 			E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);  in em_initialize_receive_unit()