Lines Matching +full:lf +full:- +full:buffer +full:- +full:low +full:- +full:power

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
40 static const char em_driver_version[] = "7.7.8-fbsd";
41 static const char igb_driver_version[] = "2.5.28-fbsd";
55 /* Intel(R) - lem-class legacy devices */
136 /* Intel(R) - em-class devices */
185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
189 "Intel(R) 82566DM-2 ICH9 AMT"),
190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
214 "Intel(R) I218-LM LPTLP"),
215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
223 "Intel(R) I219-LM SPT-H(2)"),
225 "Intel(R) I219-V SPT-H(2)"),
227 "Intel(R) I219-LM LBG(3)"),
229 "Intel(R) I219-LM SPT(4)"),
230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
232 "Intel(R) I219-LM SPT(5)"),
233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
235 "Intel(R) I219-LM CNP(6)"),
236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
238 "Intel(R) I219-LM CNP(7)"),
239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
241 "Intel(R) I219-LM ICP(8)"),
242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
244 "Intel(R) I219-LM ICP(9)"),
245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
247 "Intel(R) I219-LM CMP(10)"),
249 "Intel(R) I219-V CMP(10)"),
251 "Intel(R) I219-LM CMP(11)"),
253 "Intel(R) I219-V CMP(11)"),
255 "Intel(R) I219-LM CMP(12)"),
257 "Intel(R) I219-V CMP(12)"),
259 "Intel(R) I219-LM TGP(13)"),
261 "Intel(R) I219-V TGP(13)"),
263 "Intel(R) I219-LM TGP(14)"),
265 "Intel(R) I219-V GTP(14)"),
267 "Intel(R) I219-LM TGP(15)"),
269 "Intel(R) I219-V TGP(15)"),
271 "Intel(R) I219-LM ADL(16)"),
273 "Intel(R) I219-V ADL(16)"),
275 "Intel(R) I219-LM ADL(17)"),
277 "Intel(R) I219-V ADL(17)"),
279 "Intel(R) I219-LM MTP(18)"),
281 "Intel(R) I219-V MTP(18)"),
283 "Intel(R) I219-LM ADL(19)"),
285 "Intel(R) I219-V ADL(19)"),
287 "Intel(R) I219-LM LNL(20)"),
289 "Intel(R) I219-V LNL(20)"),
291 "Intel(R) I219-LM LNL(21)"),
293 "Intel(R) I219-V LNL(21)"),
295 "Intel(R) I219-LM RPL(22)"),
297 "Intel(R) I219-V RPL(22)"),
299 "Intel(R) I219-LM RPL(23)"),
301 "Intel(R) I219-V RPL(23)"),
303 "Intel(R) I219-LM ARL(24)"),
305 "Intel(R) I219-V ARL(24)"),
307 "Intel(R) I219-LM PTP(25)"),
309 "Intel(R) I219-V PTP(25)"),
311 "Intel(R) I219-LM PTP(26)"),
313 "Intel(R) I219-V PTP(26)"),
315 "Intel(R) I219-LM PTP(27)"),
317 "Intel(R) I219-V PTP(27)"),
324 /* Intel(R) - igb-class devices */
354 "Intel(R) I340-T2 82580 (Dual Copper)"),
356 "Intel(R) I340-F4 82580 (Quad Fiber)"),
360 "Intel(R) I347-AT4 DH89XXCC"),
481 /* MSI-X handlers */
666 0, "Set to true to leave smart power down enabled on newer adapters");
677 /* Energy efficient ethernet - default to OFF */
771 struct e1000_hw *hw = &sc->hw; in em_get_regs()
851 if_softc_ctx_t scctx = sc->shared; in em_get_regs()
852 struct rx_ring *rxr = &rx_que->rxr; in em_get_regs()
853 struct tx_ring *txr = &tx_que->txr; in em_get_regs()
854 int ntxd = scctx->isc_ntxd[0]; in em_get_regs()
855 int nrxd = scctx->isc_nrxd[0]; in em_get_regs()
859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); in em_get_regs()
860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); in em_get_regs()
863 j, rxr->rx_base[j].read.buffer_addr, staterr, length); in em_get_regs()
867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; in em_get_regs()
872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, in em_get_regs()
873 buf->eop != -1 ? in em_get_regs()
874 txr->tx_base[buf->eop].upper.fields.status & in em_get_regs()
905 switch (sc->hw.mac.type) { in em_set_num_queues()
969 sc->ctx = sc->osdep.ctx = ctx; in em_if_attach_pre()
970 sc->dev = sc->osdep.dev = dev; in em_if_attach_pre()
971 scctx = sc->shared = iflib_get_softc_ctx(ctx); in em_if_attach_pre()
972 sc->media = iflib_get_media(ctx); in em_if_attach_pre()
973 hw = &sc->hw; in em_if_attach_pre()
986 sc->enable_aim = em_enable_aim; in em_if_attach_pre()
988 CTLFLAG_RW, &sc->enable_aim, 0, in em_if_attach_pre()
1012 if (hw->mac.type >= e1000_i350) { in em_if_attach_pre()
1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER; in em_if_attach_pre()
1037 scctx->isc_nrxqsets_max = in em_if_attach_pre()
1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); in em_if_attach_pre()
1041 scctx->isc_ntxqsets_max); in em_if_attach_pre()
1043 if (hw->mac.type >= igb_mac_min) { in em_if_attach_pre()
1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in em_if_attach_pre()
1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in em_if_attach_pre()
1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); in em_if_attach_pre()
1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); in em_if_attach_pre()
1050 scctx->isc_txrx = &igb_txrx; in em_if_attach_pre()
1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; in em_if_attach_pre()
1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; in em_if_attach_pre()
1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; in em_if_attach_pre()
1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; in em_if_attach_pre()
1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | in em_if_attach_pre()
1057 if (hw->mac.type != e1000_82575) in em_if_attach_pre()
1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; in em_if_attach_pre()
1064 scctx->isc_msix_bar = pci_msix_table_bar(dev); in em_if_attach_pre()
1065 } else if (hw->mac.type >= em_mac_min) { in em_if_attach_pre()
1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in em_if_attach_pre()
1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in em_if_attach_pre()
1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); in em_if_attach_pre()
1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); in em_if_attach_pre()
1072 scctx->isc_txrx = &em_txrx; in em_if_attach_pre()
1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; in em_if_attach_pre()
1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; in em_if_attach_pre()
1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; in em_if_attach_pre()
1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; in em_if_attach_pre()
1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | in em_if_attach_pre()
1081 scctx->isc_capenable &= ~IFCAP_TSO; in em_if_attach_pre()
1086 * i218-i219 Specification Update 1.5.4.5 in em_if_attach_pre()
1088 if (hw->mac.type == e1000_pch_spt) in em_if_attach_pre()
1089 scctx->isc_capenable &= ~IFCAP_TSO; in em_if_attach_pre()
1092 * We support MSI-X with 82574 only, but indicate to iflib(4) in em_if_attach_pre()
1095 if (hw->mac.type == e1000_82574) { in em_if_attach_pre()
1096 scctx->isc_msix_bar = pci_msix_table_bar(dev); in em_if_attach_pre()
1098 scctx->isc_msix_bar = -1; in em_if_attach_pre()
1099 scctx->isc_disable_msix = 1; in em_if_attach_pre()
1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * in em_if_attach_pre()
1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * in em_if_attach_pre()
1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); in em_if_attach_pre()
1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); in em_if_attach_pre()
1108 scctx->isc_txrx = &lem_txrx; in em_if_attach_pre()
1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; in em_if_attach_pre()
1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; in em_if_attach_pre()
1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; in em_if_attach_pre()
1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; in em_if_attach_pre()
1114 scctx->isc_capabilities |= IFCAP_TSO6; in em_if_attach_pre()
1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | in em_if_attach_pre()
1119 scctx->isc_capenable &= ~IFCAP_TSO; in em_if_attach_pre()
1122 if (hw->device_id == E1000_DEV_ID_82541ER || in em_if_attach_pre()
1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) { in em_if_attach_pre()
1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; in em_if_attach_pre()
1125 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1128 if (hw->mac.type == e1000_82542) { in em_if_attach_pre()
1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | in em_if_attach_pre()
1133 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1136 if (hw->mac.type < e1000_82544 || in em_if_attach_pre()
1137 hw->mac.type == e1000_82547 || in em_if_attach_pre()
1138 hw->mac.type == e1000_82547_rev_2) { in em_if_attach_pre()
1139 scctx->isc_capabilities &= in em_if_attach_pre()
1141 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1144 if (hw->mac.type < e1000_82545){ in em_if_attach_pre()
1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; in em_if_attach_pre()
1146 scctx->isc_capenable = scctx->isc_capabilities; in em_if_attach_pre()
1149 * "PCI/PCI-X SDM 4.0" page 33 (b): in em_if_attach_pre()
1152 if (hw->mac.type == e1000_82547 || in em_if_attach_pre()
1153 hw->mac.type == e1000_82547_rev_2) in em_if_attach_pre()
1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM | in em_if_attach_pre()
1158 scctx->isc_msix_bar = 0; in em_if_attach_pre()
1174 if ((hw->mac.type == e1000_ich8lan) || in em_if_attach_pre()
1175 (hw->mac.type == e1000_ich9lan) || in em_if_attach_pre()
1176 (hw->mac.type == e1000_ich10lan) || in em_if_attach_pre()
1177 (hw->mac.type == e1000_pchlan) || in em_if_attach_pre()
1178 (hw->mac.type == e1000_pch2lan) || in em_if_attach_pre()
1179 (hw->mac.type == e1000_pch_lpt)) { in em_if_attach_pre()
1181 sc->flash = bus_alloc_resource_any(dev, in em_if_attach_pre()
1183 if (sc->flash == NULL) { in em_if_attach_pre()
1189 hw->flash_address = (u8 *)sc->flash; in em_if_attach_pre()
1190 sc->osdep.flash_bus_space_tag = in em_if_attach_pre()
1191 rman_get_bustag(sc->flash); in em_if_attach_pre()
1192 sc->osdep.flash_bus_space_handle = in em_if_attach_pre()
1193 rman_get_bushandle(sc->flash); in em_if_attach_pre()
1201 else if (hw->mac.type >= e1000_pch_spt) { in em_if_attach_pre()
1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; in em_if_attach_pre()
1203 sc->osdep.flash_bus_space_handle = in em_if_attach_pre()
1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; in em_if_attach_pre()
1220 if (hw->mac.type < igb_mac_min) { in em_if_attach_pre()
1222 "receive interrupt delay in usecs", &sc->rx_int_delay, in em_if_attach_pre()
1225 "transmit interrupt delay in usecs", &sc->tx_int_delay, in em_if_attach_pre()
1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { in em_if_attach_pre()
1231 &sc->rx_abs_int_delay, in em_if_attach_pre()
1235 &sc->tx_abs_int_delay, in em_if_attach_pre()
1239 hw->mac.autoneg = DO_AUTO_NEG; in em_if_attach_pre()
1240 hw->phy.autoneg_wait_to_complete = false; in em_if_attach_pre()
1241 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in em_if_attach_pre()
1243 if (hw->mac.type < em_mac_min) { in em_if_attach_pre()
1248 if (hw->phy.media_type == e1000_media_type_copper) { in em_if_attach_pre()
1249 hw->phy.mdix = AUTO_ALL_MODES; in em_if_attach_pre()
1250 hw->phy.disable_polarity_correction = false; in em_if_attach_pre()
1251 hw->phy.ms_type = EM_MASTER_SLAVE; in em_if_attach_pre()
1258 scctx->isc_max_frame_size = hw->mac.max_frame_size = in em_if_attach_pre()
1265 hw->mac.report_tx_early = 1; in em_if_attach_pre()
1268 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * in em_if_attach_pre()
1270 if (sc->mta == NULL) { in em_if_attach_pre()
1278 sc->tso_automasked = 0; in em_if_attach_pre()
1286 if (hw->mac.type < igb_mac_min) in em_if_attach_pre()
1287 hw->dev_spec.ich8lan.eee_disable = eee_setting; in em_if_attach_pre()
1289 hw->dev_spec._82575.eee_disable = eee_setting; in em_if_attach_pre()
1304 ** Some PCI-E parts fail the first check due to in em_if_attach_pre()
1324 if (!em_is_valid_ether_addr(hw->mac.addr)) { in em_if_attach_pre()
1325 if (sc->vf_ifp) { in em_if_attach_pre()
1327 (struct ether_addr *)hw->mac.addr); in em_if_attach_pre()
1341 * Get Wake-on-Lan and Management info for later use in em_if_attach_pre()
1346 scctx->isc_capenable &= ~IFCAP_WOL; in em_if_attach_pre()
1347 if (sc->wol != 0) in em_if_attach_pre()
1348 scctx->isc_capenable |= IFCAP_WOL_MAGIC; in em_if_attach_pre()
1350 iflib_set_mac(ctx, hw->mac.addr); in em_if_attach_pre()
1358 free(sc->mta, M_DEVBUF); in em_if_attach_pre()
1367 struct e1000_hw *hw = &sc->hw; in em_if_attach_post()
1373 device_printf(sc->dev, "Interface setup failed: %d\n", error); in em_if_attach_post()
1381 hw->mac.get_link_status = 1; in em_if_attach_post()
1385 /* Non-AMT based hardware can now take control from firmware */ in em_if_attach_post()
1386 if (sc->has_manage && !sc->has_amt) in em_if_attach_post()
1417 e1000_phy_hw_reset(&sc->hw); in em_if_detach()
1422 free(sc->mta, M_DEVBUF); in em_if_detach()
1423 sc->mta = NULL; in em_if_detach()
1459 if (sc->hw.mac.type == e1000_pch2lan) in em_if_resume()
1460 e1000_resume_workarounds_pchlan(&sc->hw); in em_if_resume()
1476 switch (sc->hw.mac.type) { in em_if_mtu_set()
1504 if (sc->hw.mac.type >= igb_mac_min) in em_if_mtu_set()
1509 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { in em_if_mtu_set()
1513 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = in em_if_mtu_set()
1531 if_softc_ctx_t scctx = sc->shared; in em_if_init()
1539 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); in em_if_init()
1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); in em_if_init()
1550 if (sc->hw.mac.type == e1000_82571) { in em_if_init()
1551 e1000_set_laa_state_82571(&sc->hw, true); in em_if_init()
1552 e1000_rar_set(&sc->hw, sc->hw.mac.addr, in em_if_init()
1553 E1000_RAR_ENTRIES - 1); in em_if_init()
1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; in em_if_init()
1562 struct tx_ring *txr = &tx_que->txr; in em_if_init()
1564 txr->tx_rs_cidx = txr->tx_rs_pidx; in em_if_init()
1568 * off-by-one error when calculating how many descriptors are in em_if_init()
1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; in em_if_init()
1575 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); in em_if_init()
1578 if (sc->hw.mac.type >= igb_mac_min) in em_if_init()
1579 e1000_rx_fifo_flush_base(&sc->hw); in em_if_init()
1590 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); in em_if_init()
1598 e1000_clear_hw_cntrs_base_generic(&sc->hw); in em_if_init()
1600 /* MSI-X configuration for 82574 */ in em_if_init()
1601 if (sc->hw.mac.type == e1000_82574) { in em_if_init()
1602 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_if_init()
1605 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); in em_if_init()
1606 /* Set the IVAR - interrupt vector routing. */ in em_if_init()
1607 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); in em_if_init()
1608 } else if (sc->intr_type == IFLIB_INTR_MSIX) { in em_if_init()
1614 E1000_READ_REG(&sc->hw, E1000_ICR); in em_if_init()
1615 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); in em_if_init()
1618 if (sc->has_manage && sc->has_amt) in em_if_init()
1622 if (sc->hw.mac.type >= igb_mac_min && in em_if_init()
1623 sc->hw.phy.media_type == e1000_media_type_copper) { in em_if_init()
1624 if (sc->hw.mac.type == e1000_i354) in em_if_init()
1625 e1000_set_eee_i354(&sc->hw, true, true); in em_if_init()
1627 e1000_set_eee_i350(&sc->hw, true, true); in em_if_init()
1646 struct e1000_hw *hw = &sc->hw; in em_newitr()
1654 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0)) in em_newitr()
1659 if (sc->enable_aim) { in em_newitr()
1660 nextlatency = rxr->rx_nextlatency; in em_newitr()
1662 /* Use half default (4K) ITR if sub-gig */ in em_newitr()
1663 if (sc->link_speed != 1000) { in em_newitr()
1667 /* Want at least enough packet buffer for two frames to AIM */ in em_newitr()
1668 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { in em_newitr()
1670 sc->enable_aim = 0; in em_newitr()
1675 if (txr->tx_bytes && txr->tx_packets) { in em_newitr()
1676 bytes = txr->tx_bytes; in em_newitr()
1677 bytes_packets = txr->tx_bytes/txr->tx_packets; in em_newitr()
1678 packets = txr->tx_packets; in em_newitr()
1680 if (rxr->rx_bytes && rxr->rx_packets) { in em_newitr()
1681 bytes = max(bytes, rxr->rx_bytes); in em_newitr()
1683 max(bytes_packets, rxr->rx_bytes/rxr->rx_packets); in em_newitr()
1684 packets = max(packets, rxr->rx_packets); in em_newitr()
1724 device_printf(sc->dev, in em_newitr()
1730 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) in em_newitr()
1734 rxr->rx_nextlatency = nextlatency; in em_newitr()
1738 rxr->rx_nextlatency = nextlatency; in em_newitr()
1759 if (hw->mac.type >= igb_mac_min) { in em_newitr()
1762 if (hw->mac.type == e1000_82575) in em_newitr()
1767 if (newitr != que->itr_setting) { in em_newitr()
1768 que->itr_setting = newitr; in em_newitr()
1769 E1000_WRITE_REG(hw, E1000_EITR(que->msix), in em_newitr()
1770 que->itr_setting); in em_newitr()
1775 if (newitr != que->itr_setting) { in em_newitr()
1776 que->itr_setting = newitr; in em_newitr()
1777 if (hw->mac.type == e1000_82574 && que->msix) { in em_newitr()
1779 E1000_EITR_82574(que->msix), in em_newitr()
1780 que->itr_setting); in em_newitr()
1783 que->itr_setting); in em_newitr()
1798 struct e1000_hw *hw = &sc->hw; in em_intr()
1799 struct em_rx_queue *que = &sc->rx_queues[0]; in em_intr()
1800 struct tx_ring *txr = &sc->tx_queues[0].txr; in em_intr()
1801 struct rx_ring *rxr = &que->rxr; in em_intr()
1802 if_ctx_t ctx = sc->ctx; in em_intr()
1819 if (hw->mac.type >= e1000_82571 && in em_intr()
1824 * Only MSI-X interrupts have one-shot behavior by taking advantage in em_intr()
1836 sc->rx_overruns++; in em_intr()
1838 if (hw->mac.type >= e1000_82540) in em_intr()
1842 txr->tx_bytes = 0; in em_intr()
1843 txr->tx_packets = 0; in em_intr()
1844 rxr->rx_bytes = 0; in em_intr()
1845 rxr->rx_packets = 0; in em_intr()
1854 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; in em_if_rx_queue_intr_enable()
1856 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); in em_if_rx_queue_intr_enable()
1864 struct em_tx_queue *txq = &sc->tx_queues[txqid]; in em_if_tx_queue_intr_enable()
1866 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); in em_if_tx_queue_intr_enable()
1874 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; in igb_if_rx_queue_intr_enable()
1876 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); in igb_if_rx_queue_intr_enable()
1884 struct em_tx_queue *txq = &sc->tx_queues[txqid]; in igb_if_tx_queue_intr_enable()
1886 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); in igb_if_tx_queue_intr_enable()
1892 * MSI-X RX Interrupt Service routine
1899 struct e1000_softc *sc = que->sc; in em_msix_que()
1900 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; in em_msix_que()
1901 struct rx_ring *rxr = &que->rxr; in em_msix_que()
1903 ++que->irqs; in em_msix_que()
1908 txr->tx_bytes = 0; in em_msix_que()
1909 txr->tx_packets = 0; in em_msix_que()
1910 rxr->rx_bytes = 0; in em_msix_que()
1911 rxr->rx_packets = 0; in em_msix_que()
1918 * MSI-X Link Fast Interrupt Service routine
1927 ++sc->link_irq; in em_msix_link()
1928 MPASS(sc->hw.back != NULL); in em_msix_link()
1929 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); in em_msix_link()
1932 sc->rx_overruns++; in em_msix_link()
1935 em_handle_link(sc->ctx); in em_msix_link()
1937 /* Re-arm unconditionally */ in em_msix_link()
1938 if (sc->hw.mac.type >= igb_mac_min) { in em_msix_link()
1939 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); in em_msix_link()
1940 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); in em_msix_link()
1941 } else if (sc->hw.mac.type == e1000_82574) { in em_msix_link()
1942 E1000_WRITE_REG(&sc->hw, E1000_IMS, in em_msix_link()
1950 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); in em_msix_link()
1952 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); in em_msix_link()
1963 sc->hw.mac.get_link_status = 1; in em_handle_link()
1985 ifmr->ifm_status = IFM_AVALID; in em_if_media_status()
1986 ifmr->ifm_active = IFM_ETHER; in em_if_media_status()
1988 if (!sc->link_active) { in em_if_media_status()
1992 ifmr->ifm_status |= IFM_ACTIVE; in em_if_media_status()
1994 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || in em_if_media_status()
1995 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { in em_if_media_status()
1996 if (sc->hw.mac.type == e1000_82545) in em_if_media_status()
1998 switch (sc->link_speed) { in em_if_media_status()
2000 ifmr->ifm_active |= IFM_10_FL; in em_if_media_status()
2003 ifmr->ifm_active |= IFM_100_FX; in em_if_media_status()
2007 ifmr->ifm_active |= fiber_type | IFM_FDX; in em_if_media_status()
2011 switch (sc->link_speed) { in em_if_media_status()
2013 ifmr->ifm_active |= IFM_10_T; in em_if_media_status()
2016 ifmr->ifm_active |= IFM_100_TX; in em_if_media_status()
2019 ifmr->ifm_active |= IFM_1000_T; in em_if_media_status()
2024 if (sc->link_duplex == FULL_DUPLEX) in em_if_media_status()
2025 ifmr->ifm_active |= IFM_FDX; in em_if_media_status()
2027 ifmr->ifm_active |= IFM_HDX; in em_if_media_status()
2046 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) in em_if_media_change()
2049 switch (IFM_SUBTYPE(ifm->ifm_media)) { in em_if_media_change()
2051 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2052 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; in em_if_media_change()
2057 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2058 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; in em_if_media_change()
2061 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2062 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { in em_if_media_change()
2063 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; in em_if_media_change()
2064 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; in em_if_media_change()
2066 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; in em_if_media_change()
2067 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; in em_if_media_change()
2071 sc->hw.mac.autoneg = DO_AUTO_NEG; in em_if_media_change()
2072 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { in em_if_media_change()
2073 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; in em_if_media_change()
2074 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; in em_if_media_change()
2076 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; in em_if_media_change()
2077 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; in em_if_media_change()
2081 sc->hw.mac.autoneg = false; in em_if_media_change()
2082 sc->hw.phy.autoneg_advertised = 0; in em_if_media_change()
2083 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in em_if_media_change()
2084 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; in em_if_media_change()
2086 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; in em_if_media_change()
2089 sc->hw.mac.autoneg = false; in em_if_media_change()
2090 sc->hw.phy.autoneg_advertised = 0; in em_if_media_change()
2091 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) in em_if_media_change()
2092 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; in em_if_media_change()
2094 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; in em_if_media_change()
2097 device_printf(sc->dev, "Unsupported media type\n"); in em_if_media_change()
2113 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_set_promisc()
2123 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_set_promisc()
2131 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_set_promisc()
2136 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_set_promisc()
2174 mta = sc->mta; in em_if_multi_set()
2177 if (sc->hw.mac.type == e1000_82542 && in em_if_multi_set()
2178 sc->hw.revision_id == E1000_REVISION_2) { in em_if_multi_set()
2179 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_multi_set()
2180 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) in em_if_multi_set()
2181 e1000_pci_clear_mwi(&sc->hw); in em_if_multi_set()
2183 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_multi_set()
2190 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); in em_if_multi_set()
2192 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_multi_set()
2203 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_multi_set()
2205 if (sc->hw.mac.type == e1000_82542 && in em_if_multi_set()
2206 sc->hw.revision_id == E1000_REVISION_2) { in em_if_multi_set()
2207 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_if_multi_set()
2209 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); in em_if_multi_set()
2211 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) in em_if_multi_set()
2212 e1000_pci_set_mwi(&sc->hw); in em_if_multi_set()
2221 * controller-specific hardware patting.
2237 struct e1000_hw *hw = &sc->hw; in em_if_update_admin_status()
2244 switch (hw->phy.media_type) { in em_if_update_admin_status()
2246 if (hw->mac.get_link_status) { in em_if_update_admin_status()
2247 if (hw->mac.type == e1000_pch_spt) in em_if_update_admin_status()
2251 link_check = !hw->mac.get_link_status; in em_if_update_admin_status()
2265 link_check = hw->mac.serdes_has_link; in em_if_update_admin_status()
2270 link_check = !hw->mac.get_link_status; in em_if_update_admin_status()
2277 if (hw->mac.type == e1000_i350) { in em_if_update_admin_status()
2283 if (link_check && (sc->link_active == 0)) { in em_if_update_admin_status()
2284 e1000_get_speed_and_duplex(hw, &sc->link_speed, in em_if_update_admin_status()
2285 &sc->link_duplex); in em_if_update_admin_status()
2286 /* Check if we must disable SPEED_MODE bit on PCI-E */ in em_if_update_admin_status()
2287 if ((sc->link_speed != SPEED_1000) && in em_if_update_admin_status()
2288 ((hw->mac.type == e1000_82571) || in em_if_update_admin_status()
2289 (hw->mac.type == e1000_82572))) { in em_if_update_admin_status()
2297 sc->link_speed, in em_if_update_admin_status()
2298 ((sc->link_duplex == FULL_DUPLEX) ? in em_if_update_admin_status()
2300 sc->link_active = 1; in em_if_update_admin_status()
2301 sc->smartspeed = 0; in em_if_update_admin_status()
2307 if (((hw->mac.type == e1000_i210) || in em_if_update_admin_status()
2308 (hw->mac.type == e1000_i211)) && in em_if_update_admin_status()
2309 (hw->phy.id == I210_I_PHY_ID)) in em_if_update_admin_status()
2312 if (hw->dev_spec._82575.media_changed && in em_if_update_admin_status()
2313 hw->mac.type >= igb_mac_min) { in em_if_update_admin_status()
2314 hw->dev_spec._82575.media_changed = false; in em_if_update_admin_status()
2315 sc->flags |= IGB_MEDIA_RESET; in em_if_update_admin_status()
2319 if (hw->mac.type < igb_mac_min) in em_if_update_admin_status()
2325 IF_Mbps(sc->link_speed)); in em_if_update_admin_status()
2326 } else if (!link_check && (sc->link_active == 1)) { in em_if_update_admin_status()
2327 sc->link_speed = 0; in em_if_update_admin_status()
2328 sc->link_duplex = 0; in em_if_update_admin_status()
2329 sc->link_active = 0; in em_if_update_admin_status()
2335 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) in em_if_update_admin_status()
2336 e1000_rar_set(hw, hw->mac.addr, 0); in em_if_update_admin_status()
2338 if (hw->mac.type < em_mac_min) in em_if_update_admin_status()
2351 sc->watchdog_events++; in em_if_watchdog_reset()
2368 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) in em_if_stop()
2371 e1000_reset_hw(&sc->hw); in em_if_stop()
2372 if (sc->hw.mac.type >= e1000_82544) in em_if_stop()
2373 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); in em_if_stop()
2375 e1000_led_off(&sc->hw); in em_if_stop()
2376 e1000_cleanup_led(&sc->hw); in em_if_stop()
2391 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); in em_identify_hardware()
2394 sc->hw.vendor_id = pci_get_vendor(dev); in em_identify_hardware()
2395 sc->hw.device_id = pci_get_device(dev); in em_identify_hardware()
2396 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); in em_identify_hardware()
2397 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); in em_identify_hardware()
2398 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); in em_identify_hardware()
2401 if (e1000_set_mac_type(&sc->hw)) { in em_identify_hardware()
2407 if ((sc->hw.mac.type == e1000_vfadapt) || in em_identify_hardware()
2408 (sc->hw.mac.type == e1000_vfadapt_i350)) in em_identify_hardware()
2409 sc->vf_ifp = 1; in em_identify_hardware()
2411 sc->vf_ifp = 0; in em_identify_hardware()
2422 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in em_allocate_pci_resources()
2424 if (sc->memory == NULL) { in em_allocate_pci_resources()
2429 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); in em_allocate_pci_resources()
2430 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); in em_allocate_pci_resources()
2431 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; in em_allocate_pci_resources()
2434 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { in em_allocate_pci_resources()
2450 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, in em_allocate_pci_resources()
2452 if (sc->ioport == NULL) { in em_allocate_pci_resources()
2457 sc->hw.io_base = 0; in em_allocate_pci_resources()
2458 sc->osdep.io_bus_space_tag = in em_allocate_pci_resources()
2459 rman_get_bustag(sc->ioport); in em_allocate_pci_resources()
2460 sc->osdep.io_bus_space_handle = in em_allocate_pci_resources()
2461 rman_get_bushandle(sc->ioport); in em_allocate_pci_resources()
2464 sc->hw.back = &sc->osdep; in em_allocate_pci_resources()
2471 * Set up the MSI-X Interrupt handlers
2478 struct em_rx_queue *rx_que = sc->rx_queues; in em_if_msix_intr_assign()
2479 struct em_tx_queue *tx_que = sc->tx_queues; in em_if_msix_intr_assign()
2484 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { in em_if_msix_intr_assign()
2487 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, in em_if_msix_intr_assign()
2488 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); in em_if_msix_intr_assign()
2493 sc->rx_num_queues = i + 1; in em_if_msix_intr_assign()
2497 rx_que->msix = vector; in em_if_msix_intr_assign()
2501 * in E1000_IMS -- bits 20 and 21 in em_if_msix_intr_assign()
2503 * NOTHING to do with the MSI-X vector in em_if_msix_intr_assign()
2505 if (sc->hw.mac.type == e1000_82574) { in em_if_msix_intr_assign()
2506 rx_que->eims = 1 << (20 + i); in em_if_msix_intr_assign()
2507 sc->ims |= rx_que->eims; in em_if_msix_intr_assign()
2508 sc->ivars |= (8 | rx_que->msix) << (i * 4); in em_if_msix_intr_assign()
2509 } else if (sc->hw.mac.type == e1000_82575) in em_if_msix_intr_assign()
2510 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; in em_if_msix_intr_assign()
2512 rx_que->eims = 1 << vector; in em_if_msix_intr_assign()
2517 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { in em_if_msix_intr_assign()
2519 tx_que = &sc->tx_queues[i]; in em_if_msix_intr_assign()
2521 &sc->rx_queues[i % sc->rx_num_queues].que_irq, in em_if_msix_intr_assign()
2522 IFLIB_INTR_TX, tx_que, tx_que->me, buf); in em_if_msix_intr_assign()
2524 tx_que->msix = (vector % sc->rx_num_queues); in em_if_msix_intr_assign()
2528 * in E1000_IMS -- bits 22 and 23 in em_if_msix_intr_assign()
2530 * NOTHING to do with the MSI-X vector in em_if_msix_intr_assign()
2532 if (sc->hw.mac.type == e1000_82574) { in em_if_msix_intr_assign()
2533 tx_que->eims = 1 << (22 + i); in em_if_msix_intr_assign()
2534 sc->ims |= tx_que->eims; in em_if_msix_intr_assign()
2535 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); in em_if_msix_intr_assign()
2536 } else if (sc->hw.mac.type == e1000_82575) { in em_if_msix_intr_assign()
2537 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; in em_if_msix_intr_assign()
2539 tx_que->eims = 1 << i; in em_if_msix_intr_assign()
2545 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, in em_if_msix_intr_assign()
2553 sc->linkvec = rx_vectors; in em_if_msix_intr_assign()
2554 if (sc->hw.mac.type < igb_mac_min) { in em_if_msix_intr_assign()
2555 sc->ivars |= (8 | rx_vectors) << 16; in em_if_msix_intr_assign()
2556 sc->ivars |= 0x80000000; in em_if_msix_intr_assign()
2558 sc->ims |= E1000_IMS_OTHER; in em_if_msix_intr_assign()
2563 iflib_irq_free(ctx, &sc->irq); in em_if_msix_intr_assign()
2564 rx_que = sc->rx_queues; in em_if_msix_intr_assign()
2565 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) in em_if_msix_intr_assign()
2566 iflib_irq_free(ctx, &rx_que->que_irq); in em_if_msix_intr_assign()
2573 struct e1000_hw *hw = &sc->hw; in igb_configure_queues()
2579 if (hw->mac.type != e1000_82575) in igb_configure_queues()
2584 /* Turn on MSI-X */ in igb_configure_queues()
2585 switch (hw->mac.type) { in igb_configure_queues()
2594 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2597 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2600 ivar |= (rx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2604 ivar |= rx_que->msix | E1000_IVAR_VALID; in igb_configure_queues()
2609 for (int i = 0; i < sc->tx_num_queues; i++) { in igb_configure_queues()
2612 tx_que = &sc->tx_queues[i]; in igb_configure_queues()
2615 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2619 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2623 sc->que_mask |= tx_que->eims; in igb_configure_queues()
2627 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; in igb_configure_queues()
2628 sc->link_mask = 1 << sc->linkvec; in igb_configure_queues()
2633 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2636 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2639 ivar |= rx_que->msix | E1000_IVAR_VALID; in igb_configure_queues()
2642 ivar |= (rx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2646 sc->que_mask |= rx_que->eims; in igb_configure_queues()
2649 for (int i = 0; i < sc->tx_num_queues; i++) { in igb_configure_queues()
2652 tx_que = &sc->tx_queues[i]; in igb_configure_queues()
2655 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2659 ivar |= (tx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
2663 sc->que_mask |= tx_que->eims; in igb_configure_queues()
2667 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; in igb_configure_queues()
2668 sc->link_mask = 1 << sc->linkvec; in igb_configure_queues()
2673 /* enable MSI-X support*/ in igb_configure_queues()
2676 /* Auto-Mask interrupts upon ICR read. */ in igb_configure_queues()
2682 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2683 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2686 rx_que->eims = tmp; in igb_configure_queues()
2688 rx_que->eims); in igb_configure_queues()
2689 sc->que_mask |= rx_que->eims; in igb_configure_queues()
2693 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), in igb_configure_queues()
2695 sc->link_mask |= E1000_EIMS_OTHER; in igb_configure_queues()
2704 if (hw->mac.type == e1000_82575) in igb_configure_queues()
2709 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2710 rx_que = &sc->rx_queues[i]; in igb_configure_queues()
2711 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); in igb_configure_queues()
2722 struct em_rx_queue *que = sc->rx_queues; in em_free_pci_resources()
2725 /* Release all MSI-X queue resources */ in em_free_pci_resources()
2726 if (sc->intr_type == IFLIB_INTR_MSIX) in em_free_pci_resources()
2727 iflib_irq_free(ctx, &sc->irq); in em_free_pci_resources()
2730 for (int i = 0; i < sc->rx_num_queues; i++, que++) { in em_free_pci_resources()
2731 iflib_irq_free(ctx, &que->que_irq); in em_free_pci_resources()
2735 if (sc->memory != NULL) { in em_free_pci_resources()
2737 rman_get_rid(sc->memory), sc->memory); in em_free_pci_resources()
2738 sc->memory = NULL; in em_free_pci_resources()
2741 if (sc->flash != NULL) { in em_free_pci_resources()
2743 rman_get_rid(sc->flash), sc->flash); in em_free_pci_resources()
2744 sc->flash = NULL; in em_free_pci_resources()
2747 if (sc->ioport != NULL) { in em_free_pci_resources()
2749 rman_get_rid(sc->ioport), sc->ioport); in em_free_pci_resources()
2750 sc->ioport = NULL; in em_free_pci_resources()
2754 /* Set up MSI or MSI-X */
2760 if (sc->hw.mac.type == e1000_82574) { in em_setup_msix()
2776 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || in lem_smartspeed()
2777 sc->hw.mac.autoneg == 0 || in lem_smartspeed()
2778 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) in lem_smartspeed()
2781 if (sc->smartspeed == 0) { in lem_smartspeed()
2783 * we assume back-to-back */ in lem_smartspeed()
2784 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); in lem_smartspeed()
2787 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); in lem_smartspeed()
2789 e1000_read_phy_reg(&sc->hw, in lem_smartspeed()
2793 e1000_write_phy_reg(&sc->hw, in lem_smartspeed()
2795 sc->smartspeed++; in lem_smartspeed()
2796 if(sc->hw.mac.autoneg && in lem_smartspeed()
2797 !e1000_copper_link_autoneg(&sc->hw) && in lem_smartspeed()
2798 !e1000_read_phy_reg(&sc->hw, in lem_smartspeed()
2802 e1000_write_phy_reg(&sc->hw, in lem_smartspeed()
2808 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { in lem_smartspeed()
2810 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); in lem_smartspeed()
2812 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); in lem_smartspeed()
2813 if(sc->hw.mac.autoneg && in lem_smartspeed()
2814 !e1000_copper_link_autoneg(&sc->hw) && in lem_smartspeed()
2815 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { in lem_smartspeed()
2818 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); in lem_smartspeed()
2822 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) in lem_smartspeed()
2823 sc->smartspeed = 0; in lem_smartspeed()
2834 device_t dev = sc->dev; in igb_init_dmac()
2835 struct e1000_hw *hw = &sc->hw; in igb_init_dmac()
2840 if (hw->mac.type == e1000_i211) in igb_init_dmac()
2843 max_frame_size = sc->shared->isc_max_frame_size; in igb_init_dmac()
2844 if (hw->mac.type > e1000_82580) { in igb_init_dmac()
2846 if (sc->dmac == 0) { /* Disabling it */ in igb_init_dmac()
2855 hwm = 64 * pba - max_frame_size / 16; in igb_init_dmac()
2856 if (hwm < 64 * (pba - 6)) in igb_init_dmac()
2857 hwm = 64 * (pba - 6); in igb_init_dmac()
2865 dmac = pba - max_frame_size / 512; in igb_init_dmac()
2866 if (dmac < pba - 10) in igb_init_dmac()
2867 dmac = pba - 10; in igb_init_dmac()
2882 if (hw->mac.type == e1000_i354) { in igb_init_dmac()
2886 reg |= ((sc->dmac * 5) >> 6); in igb_init_dmac()
2888 reg |= (sc->dmac >> 5); in igb_init_dmac()
2890 reg |= (sc->dmac >> 5); in igb_init_dmac()
2899 if (hw->mac.type == e1000_i350) in igb_init_dmac()
2905 if (hw->mac.type == e1000_i354) { in igb_init_dmac()
2918 /* free space in tx packet buffer to wake from DMA coal */ in igb_init_dmac()
2919 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - in igb_init_dmac()
2922 /* make low power state decision controlled by DMA coal */ in igb_init_dmac()
2927 } else if (hw->mac.type == e1000_82580) { in igb_init_dmac()
2938 * em_flush_tx_ring - remove all descriptors from the tx_ring
2948 struct e1000_hw *hw = &sc->hw; in em_flush_tx_ring()
2949 struct tx_ring *txr = &sc->tx_queues->txr; in em_flush_tx_ring()
2957 txd = &txr->tx_base[txr->tx_cidx_processed]; in em_flush_tx_ring()
2959 /* Just use the ring as a dummy buffer addr */ in em_flush_tx_ring()
2960 txd->buffer_addr = txr->tx_paddr; in em_flush_tx_ring()
2961 txd->lower.data = htole32(txd_lower | size); in em_flush_tx_ring()
2962 txd->upper.data = 0; in em_flush_tx_ring()
2967 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); in em_flush_tx_ring()
2973 * em_flush_rx_ring - remove all descriptors from the rx_ring
2980 struct e1000_hw *hw = &sc->hw; in em_flush_rx_ring()
3007 * em_flush_desc_rings - remove all descriptors from the descriptor rings
3019 struct e1000_hw *hw = &sc->hw; in em_flush_desc_rings()
3020 device_t dev = sc->dev; in em_flush_desc_rings()
3055 struct e1000_hw *hw = &sc->hw; in em_reset()
3063 /* Set up smart power down as default off on newer adapters. */ in em_reset()
3064 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || in em_reset()
3065 hw->mac.type == e1000_82572)) { in em_reset()
3068 /* Speed up time to link by disabling smart power down. */ in em_reset()
3075 * Packet Buffer Allocation (PBA) in em_reset()
3076 * Writing PBA sets the receive portion of the buffer in em_reset()
3077 * the remainder is used for the transmit buffer. in em_reset()
3079 switch (hw->mac.type) { in em_reset()
3080 /* 82547: Total Packet Buffer is 40K */ in em_reset()
3083 if (hw->mac.max_frame_size > 8192) in em_reset()
3088 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ in em_reset()
3094 /* 82573: Total Packet Buffer is 32K */ in em_reset()
3108 if (hw->mac.max_frame_size > 4096) in em_reset()
3144 /* Remaining devices assumed to have Packet Buffer of 64K. */ in em_reset()
3145 if (hw->mac.max_frame_size > 8192) in em_reset()
3152 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { in em_reset()
3157 min_tx = (hw->mac.max_frame_size + in em_reset()
3158 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; in em_reset()
3161 min_rx = hw->mac.max_frame_size; in em_reset()
3165 ((min_tx - tx_space) < pba)) { in em_reset()
3166 pba = pba - (min_tx - tx_space); in em_reset()
3177 if (hw->mac.type < igb_mac_min) in em_reset()
3185 * - High water mark should allow for at least two frames to be in em_reset()
3187 * - Low water mark works best when it is very near the high water in em_reset()
3191 * restart after one full frame is pulled from the buffer. There in em_reset()
3192 * could be several smaller frames in the buffer and if so they will in em_reset()
3193 * not trigger the XON until their total number reduces the buffer in em_reset()
3195 * - The pause time is fairly large at 1000 x 512ns = 512 usec. in em_reset()
3198 hw->fc.high_water = rx_buffer_size - in em_reset()
3199 roundup2(hw->mac.max_frame_size, 1024); in em_reset()
3200 hw->fc.low_water = hw->fc.high_water - 1500; in em_reset()
3202 if (sc->fc) /* locally set flow control value? */ in em_reset()
3203 hw->fc.requested_mode = sc->fc; in em_reset()
3205 hw->fc.requested_mode = e1000_fc_full; in em_reset()
3207 if (hw->mac.type == e1000_80003es2lan) in em_reset()
3208 hw->fc.pause_time = 0xFFFF; in em_reset()
3210 hw->fc.pause_time = EM_FC_PAUSE_TIME; in em_reset()
3212 hw->fc.send_xon = true; in em_reset()
3215 switch (hw->mac.type) { in em_reset()
3218 hw->fc.requested_mode = e1000_fc_rx_pause; in em_reset()
3219 hw->fc.pause_time = 0xFFFF; /* override */ in em_reset()
3221 hw->fc.high_water = 0x3500; in em_reset()
3222 hw->fc.low_water = 0x1500; in em_reset()
3224 hw->fc.high_water = 0x5000; in em_reset()
3225 hw->fc.low_water = 0x3000; in em_reset()
3227 hw->fc.refresh_time = 0x1000; in em_reset()
3237 hw->fc.high_water = 0x5C20; in em_reset()
3238 hw->fc.low_water = 0x5048; in em_reset()
3239 hw->fc.pause_time = 0x0650; in em_reset()
3240 hw->fc.refresh_time = 0x0400; in em_reset()
3249 /* 8-byte granularity */ in em_reset()
3250 hw->fc.low_water = hw->fc.high_water - 8; in em_reset()
3259 /* 16-byte granularity */ in em_reset()
3260 hw->fc.low_water = hw->fc.high_water - 16; in em_reset()
3265 hw->fc.high_water = 0x2800; in em_reset()
3266 hw->fc.low_water = hw->fc.high_water - 8; in em_reset()
3271 if (hw->mac.type == e1000_80003es2lan) in em_reset()
3272 hw->fc.pause_time = 0xFFFF; in em_reset()
3277 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) in em_reset()
3282 if (hw->mac.type >= igb_mac_min) { in em_reset()
3288 if (sc->flags & IGB_MEDIA_RESET) { in em_reset()
3291 sc->flags &= ~IGB_MEDIA_RESET; in em_reset()
3293 /* and a re-init */ in em_reset()
3298 if (hw->mac.type >= igb_mac_min) in em_reset()
3302 sc->pba = pba; in em_reset()
3320 struct e1000_hw *hw = &sc->hw; in em_initialize_rss_mapping()
3341 q = (i % sc->rx_num_queues) << 7; in em_initialize_rss_mapping()
3359 struct e1000_hw *hw = &sc->hw; in igb_initialize_rss_mapping()
3366 if (hw->mac.type == e1000_82575) in igb_initialize_rss_mapping()
3375 * This just allocates buckets to queues using round-robin in igb_initialize_rss_mapping()
3400 queue_id = queue_id % sc->rx_num_queues; in igb_initialize_rss_mapping()
3402 queue_id = (i % sc->rx_num_queues); in igb_initialize_rss_mapping()
3408 * The low 8 bits are for hash value (n+0); in igb_initialize_rss_mapping()
3461 if_softc_ctx_t scctx = sc->shared; in em_setup_interface()
3466 if (sc->tx_num_queues == 1) { in em_setup_interface()
3467 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); in em_setup_interface()
3475 if (sc->hw.phy.media_type == e1000_media_type_fiber || in em_setup_interface()
3476 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { in em_setup_interface()
3479 if (sc->hw.mac.type == e1000_82545) in em_setup_interface()
3481 ifmedia_add(sc->media, in em_setup_interface()
3483 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); in em_setup_interface()
3485 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); in em_setup_interface()
3486 ifmedia_add(sc->media, in em_setup_interface()
3488 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); in em_setup_interface()
3489 ifmedia_add(sc->media, in em_setup_interface()
3491 if (sc->hw.phy.type != e1000_phy_ife) { in em_setup_interface()
3492 ifmedia_add(sc->media, in em_setup_interface()
3494 ifmedia_add(sc->media, in em_setup_interface()
3498 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); in em_setup_interface()
3499 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); in em_setup_interface()
3508 if_softc_ctx_t scctx = sc->shared; in em_if_tx_queues_alloc()
3513 MPASS(sc->tx_num_queues > 0); in em_if_tx_queues_alloc()
3514 MPASS(sc->tx_num_queues == ntxqsets); in em_if_tx_queues_alloc()
3517 if (!(sc->tx_queues = in em_if_tx_queues_alloc()
3519 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in em_if_tx_queues_alloc()
3525 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { in em_if_tx_queues_alloc()
3528 struct tx_ring *txr = &que->txr; in em_if_tx_queues_alloc()
3529 txr->sc = que->sc = sc; in em_if_tx_queues_alloc()
3530 que->me = txr->me = i; in em_if_tx_queues_alloc()
3533 if (!(txr->tx_rsq = in em_if_tx_queues_alloc()
3534 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], in em_if_tx_queues_alloc()
3541 for (j = 0; j < scctx->isc_ntxd[0]; j++) in em_if_tx_queues_alloc()
3542 txr->tx_rsq[j] = QIDX_INVALID; in em_if_tx_queues_alloc()
3544 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; in em_if_tx_queues_alloc()
3545 txr->tx_paddr = paddrs[i*ntxqs]; in em_if_tx_queues_alloc()
3550 "allocated for %d tx_queues\n", sc->tx_num_queues); in em_if_tx_queues_alloc()
3566 MPASS(sc->rx_num_queues > 0); in em_if_rx_queues_alloc()
3567 MPASS(sc->rx_num_queues == nrxqsets); in em_if_rx_queues_alloc()
3570 if (!(sc->rx_queues = in em_if_rx_queues_alloc()
3572 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { in em_if_rx_queues_alloc()
3579 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { in em_if_rx_queues_alloc()
3581 struct rx_ring *rxr = &que->rxr; in em_if_rx_queues_alloc()
3582 rxr->sc = que->sc = sc; in em_if_rx_queues_alloc()
3583 rxr->que = que; in em_if_rx_queues_alloc()
3584 que->me = rxr->me = i; in em_if_rx_queues_alloc()
3587 rxr->rx_base = in em_if_rx_queues_alloc()
3589 rxr->rx_paddr = paddrs[i*nrxqs]; in em_if_rx_queues_alloc()
3594 "allocated for %d rx_queues\n", sc->rx_num_queues); in em_if_rx_queues_alloc()
3606 struct em_tx_queue *tx_que = sc->tx_queues; in em_if_queues_free()
3607 struct em_rx_queue *rx_que = sc->rx_queues; in em_if_queues_free()
3610 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in em_if_queues_free()
3611 struct tx_ring *txr = &tx_que->txr; in em_if_queues_free()
3612 if (txr->tx_rsq == NULL) in em_if_queues_free()
3615 free(txr->tx_rsq, M_DEVBUF); in em_if_queues_free()
3616 txr->tx_rsq = NULL; in em_if_queues_free()
3618 free(sc->tx_queues, M_DEVBUF); in em_if_queues_free()
3619 sc->tx_queues = NULL; in em_if_queues_free()
3623 free(sc->rx_queues, M_DEVBUF); in em_if_queues_free()
3624 sc->rx_queues = NULL; in em_if_queues_free()
3637 if_softc_ctx_t scctx = sc->shared; in em_initialize_transmit_unit()
3640 struct e1000_hw *hw = &sc->hw; in em_initialize_transmit_unit()
3645 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in em_initialize_transmit_unit()
3649 que = &sc->tx_queues[i]; in em_initialize_transmit_unit()
3650 txr = &que->txr; in em_initialize_transmit_unit()
3651 bus_addr = txr->tx_paddr; in em_initialize_transmit_unit()
3654 offp = (caddr_t)&txr->csum_flags; in em_initialize_transmit_unit()
3656 bzero(offp, endp - offp); in em_initialize_transmit_unit()
3660 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); in em_initialize_transmit_unit()
3683 switch (hw->mac.type) { in em_initialize_transmit_unit()
3695 if (hw->phy.media_type == e1000_media_type_fiber || in em_initialize_transmit_unit()
3696 hw->phy.media_type == e1000_media_type_internal_serdes) in em_initialize_transmit_unit()
3704 if (hw->mac.type < igb_mac_min) { in em_initialize_transmit_unit()
3706 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); in em_initialize_transmit_unit()
3708 if (sc->tx_int_delay.value > 0) in em_initialize_transmit_unit()
3709 sc->txd_cmd |= E1000_TXD_CMD_IDE; in em_initialize_transmit_unit()
3712 if (hw->mac.type >= e1000_82540) in em_initialize_transmit_unit()
3713 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); in em_initialize_transmit_unit()
3715 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { in em_initialize_transmit_unit()
3719 } else if (hw->mac.type == e1000_80003es2lan) { in em_initialize_transmit_unit()
3727 } else if (hw->mac.type == e1000_82574) { in em_initialize_transmit_unit()
3730 if ( sc->tx_num_queues > 1) { in em_initialize_transmit_unit()
3744 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) in em_initialize_transmit_unit()
3751 if (hw->mac.type == e1000_pch_spt) { in em_initialize_transmit_unit()
3756 /* i218-i219 Specification Update 1.5.4.5 */ in em_initialize_transmit_unit()
3769 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3775 if_softc_ctx_t scctx = sc->shared; in em_initialize_receive_unit()
3777 struct e1000_hw *hw = &sc->hw; in em_initialize_receive_unit()
3790 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) in em_initialize_receive_unit()
3797 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); in em_initialize_receive_unit()
3813 if (hw->mac.type < igb_mac_min) { in em_initialize_receive_unit()
3814 if (hw->mac.type >= e1000_82540) { in em_initialize_receive_unit()
3816 sc->rx_abs_int_delay.value); in em_initialize_receive_unit()
3829 if (hw->mac.type == e1000_82573) in em_initialize_receive_unit()
3833 sc->rx_int_delay.value); in em_initialize_receive_unit()
3836 if (hw->mac.type >= em_mac_min) { in em_initialize_receive_unit()
3843 * When using MSI-X interrupts we need to throttle in em_initialize_receive_unit()
3846 if (hw->mac.type == e1000_82574) { in em_initialize_receive_unit()
3860 if (hw->mac.type > e1000_82575) in em_initialize_receive_unit()
3862 else if (hw->mac.type < em_mac_min && in em_initialize_receive_unit()
3867 if (hw->mac.type > e1000_82575) in em_initialize_receive_unit()
3869 else if (hw->mac.type < em_mac_min) in em_initialize_receive_unit()
3873 if (sc->rx_num_queues > 1) { in em_initialize_receive_unit()
3877 if (hw->mac.type >= igb_mac_min) in em_initialize_receive_unit()
3884 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { in em_initialize_receive_unit()
3885 struct rx_ring *rxr = &que->rxr; in em_initialize_receive_unit()
3887 u64 bus_addr = rxr->rx_paddr; in em_initialize_receive_unit()
3889 u32 rdt = sc->rx_num_queues -1; /* default */ in em_initialize_receive_unit()
3893 scctx->isc_nrxd[0] * in em_initialize_receive_unit()
3909 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || in em_initialize_receive_unit()
3910 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { in em_initialize_receive_unit()
3913 } else if (hw->mac.type == e1000_82574) { in em_initialize_receive_unit()
3914 for (int i = 0; i < sc->rx_num_queues; i++) { in em_initialize_receive_unit()
3922 } else if (hw->mac.type >= igb_mac_min) { in em_initialize_receive_unit()
3926 psize = scctx->isc_max_frame_size; in em_initialize_receive_unit()
3931 if (sc->vf_ifp) in em_initialize_receive_unit()
3937 /* Set maximum packet buffer len */ in em_initialize_receive_unit()
3938 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> in em_initialize_receive_unit()
3948 if ((sc->rx_num_queues > 1) && in em_initialize_receive_unit()
3949 (sc->fc == e1000_fc_none || in em_initialize_receive_unit()
3950 sc->fc == e1000_fc_rx_pause)) { in em_initialize_receive_unit()
3954 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; in em_initialize_receive_unit()
3956 struct rx_ring *rxr = &que->rxr; in em_initialize_receive_unit()
3957 u64 bus_addr = rxr->rx_paddr; in em_initialize_receive_unit()
3961 /* Configure for header split? -- ignore for now */ in em_initialize_receive_unit()
3962 rxr->hdr_split = igb_header_split; in em_initialize_receive_unit()
3968 scctx->isc_nrxd[0] * in em_initialize_receive_unit()
3984 } else if (hw->mac.type >= e1000_pch2lan) { in em_initialize_receive_unit()
3994 /* Set up packet buffer size, overridden by per queue srrctl on igb */ in em_initialize_receive_unit()
3995 if (hw->mac.type < igb_mac_min) { in em_initialize_receive_unit()
3996 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) in em_initialize_receive_unit()
3998 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) in em_initialize_receive_unit()
4000 else if (sc->rx_mbuf_sz > 8192) in em_initialize_receive_unit()
4032 sc->shadow_vfta[index] |= (1 << bit); in em_if_vlan_register()
4033 ++sc->num_vlans; in em_if_vlan_register()
4045 sc->shadow_vfta[index] &= ~(1 << bit); in em_if_vlan_unregister()
4046 --sc->num_vlans; in em_if_vlan_unregister()
4071 if (sc->shadow_vfta[i] != 0) in em_if_vlan_filter_used()
4080 struct e1000_hw *hw = &sc->hw; in em_if_vlan_filter_enable()
4092 struct e1000_hw *hw = &sc->hw; in em_if_vlan_filter_disable()
4103 struct e1000_hw *hw = &sc->hw; in em_if_vlan_filter_write()
4105 if (sc->vf_ifp) in em_if_vlan_filter_write()
4109 if (hw->mac.type < em_mac_min) in em_if_vlan_filter_write()
4110 em_if_intr_disable(sc->ctx); in em_if_vlan_filter_write()
4113 if (sc->shadow_vfta[i] != 0) { in em_if_vlan_filter_write()
4115 if (sc->vf_ifp) in em_if_vlan_filter_write()
4116 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], in em_if_vlan_filter_write()
4119 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); in em_if_vlan_filter_write()
4122 /* Re-enable interrupts for lem-class devices */ in em_if_vlan_filter_write()
4123 if (hw->mac.type < em_mac_min) in em_if_vlan_filter_write()
4124 em_if_intr_enable(sc->ctx); in em_if_vlan_filter_write()
4131 struct e1000_hw *hw = &sc->hw; in em_setup_vlan_hw_support()
4138 if (sc->vf_ifp) in em_setup_vlan_hw_support()
4174 struct e1000_hw *hw = &sc->hw; in em_if_intr_enable()
4177 if (sc->intr_type == IFLIB_INTR_MSIX) { in em_if_intr_enable()
4178 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); in em_if_intr_enable()
4179 ims_mask |= sc->ims; in em_if_intr_enable()
4190 struct e1000_hw *hw = &sc->hw; in em_if_intr_disable()
4192 if (sc->intr_type == IFLIB_INTR_MSIX) in em_if_intr_disable()
4202 struct e1000_hw *hw = &sc->hw; in igb_if_intr_enable()
4205 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igb_if_intr_enable()
4206 mask = (sc->que_mask | sc->link_mask); in igb_if_intr_enable()
4220 struct e1000_hw *hw = &sc->hw; in igb_if_intr_disable()
4222 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { in igb_if_intr_disable()
4240 if (sc->has_manage) { in em_init_manageability()
4241 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); in em_init_manageability()
4242 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); in em_init_manageability()
4253 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); in em_init_manageability()
4254 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); in em_init_manageability()
4265 if (sc->has_manage) { in em_release_manageability()
4266 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); in em_release_manageability()
4268 /* re-enable hardware interception of ARP */ in em_release_manageability()
4272 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); in em_release_manageability()
4287 if (sc->vf_ifp) in em_get_hw_control()
4290 if (sc->hw.mac.type == e1000_82573) { in em_get_hw_control()
4291 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); in em_get_hw_control()
4292 E1000_WRITE_REG(&sc->hw, E1000_SWSM, in em_get_hw_control()
4297 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_get_hw_control()
4298 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, in em_get_hw_control()
4313 if (!sc->has_manage) in em_release_hw_control()
4316 if (sc->hw.mac.type == e1000_82573) { in em_release_hw_control()
4317 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); in em_release_hw_control()
4318 E1000_WRITE_REG(&sc->hw, E1000_SWSM, in em_release_hw_control()
4323 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_release_hw_control()
4324 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, in em_release_hw_control()
4348 if (!em_unsupported_tso && sc->link_speed && in em_automask_tso()
4349 sc->link_speed != SPEED_1000 && in em_automask_tso()
4350 scctx->isc_capenable & IFCAP_TSO) { in em_automask_tso()
4351 device_printf(sc->dev, in em_automask_tso()
4353 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; in em_automask_tso()
4354 scctx->isc_capenable &= ~IFCAP_TSO; in em_automask_tso()
4359 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { in em_automask_tso()
4360 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); in em_automask_tso()
4361 scctx->isc_capenable |= sc->tso_automasked; in em_automask_tso()
4362 if_setcapenablebit(ifp, sc->tso_automasked, 0); in em_automask_tso()
4363 sc->tso_automasked = 0; in em_automask_tso()
4374 ** to both system management and wake-on-lan for
4384 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); in em_get_wakeup()
4387 switch (sc->hw.mac.type) { in em_get_wakeup()
4392 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4398 if (sc->hw.bus.func == 1) { in em_get_wakeup()
4399 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4403 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4408 sc->has_amt = true; in em_get_wakeup()
4413 if (sc->hw.bus.func == 1) { in em_get_wakeup()
4414 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4418 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4438 sc->has_amt = true; in em_get_wakeup()
4439 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); in em_get_wakeup()
4442 e1000_read_nvm(&sc->hw, in em_get_wakeup()
4447 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); in em_get_wakeup()
4456 sc->wol = 0; in em_get_wakeup()
4462 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & in em_get_wakeup()
4464 sc->wol = 0; in em_get_wakeup()
4469 sc->wol = 0; in em_get_wakeup()
4477 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & in em_get_wakeup()
4479 sc->wol = 0; in em_get_wakeup()
4486 sc->wol = 0; in em_get_wakeup()
4517 sc->wol &= ~E1000_WUFC_MAG; in em_enable_wakeup()
4520 sc->wol &= ~E1000_WUFC_EX; in em_enable_wakeup()
4523 sc->wol &= ~E1000_WUFC_MC; in em_enable_wakeup()
4525 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); in em_enable_wakeup()
4527 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); in em_enable_wakeup()
4530 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) in em_enable_wakeup()
4534 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); in em_enable_wakeup()
4536 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); in em_enable_wakeup()
4539 if (sc->hw.phy.media_type == e1000_media_type_fiber || in em_enable_wakeup()
4540 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { in em_enable_wakeup()
4541 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); in em_enable_wakeup()
4543 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); in em_enable_wakeup()
4546 if ((sc->hw.mac.type == e1000_ich8lan) || in em_enable_wakeup()
4547 (sc->hw.mac.type == e1000_pchlan) || in em_enable_wakeup()
4548 (sc->hw.mac.type == e1000_ich9lan) || in em_enable_wakeup()
4549 (sc->hw.mac.type == e1000_ich10lan)) in em_enable_wakeup()
4550 e1000_suspend_workarounds_ich8lan(&sc->hw); in em_enable_wakeup()
4552 if ( sc->hw.mac.type >= e1000_pchlan) { in em_enable_wakeup()
4558 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); in em_enable_wakeup()
4559 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); in em_enable_wakeup()
4562 if (sc->hw.phy.type == e1000_phy_igp_3) in em_enable_wakeup()
4563 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); in em_enable_wakeup()
4582 struct e1000_hw *hw = &sc->hw; in em_enable_phy_wakeup()
4590 for (int i = 0; i < hw->mac.mta_reg_count; i++) { in em_enable_phy_wakeup()
4620 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); in em_enable_phy_wakeup()
4623 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); in em_enable_phy_wakeup()
4627 ret = hw->phy.ops.acquire(hw); in em_enable_phy_wakeup()
4644 hw->phy.ops.release(hw); in em_enable_phy_wakeup()
4655 e1000_setup_led(&sc->hw); in em_if_led_func()
4656 e1000_led_on(&sc->hw); in em_if_led_func()
4658 e1000_led_off(&sc->hw); in em_if_led_func()
4659 e1000_cleanup_led(&sc->hw); in em_if_led_func()
4671 device_t dev = sc->dev; in em_disable_aspm()
4673 switch (sc->hw.mac.type) { in em_disable_aspm()
4702 u64 prev_xoffrxc = sc->stats.xoffrxc; in em_update_stats_counters()
4704 if(sc->hw.phy.media_type == e1000_media_type_copper || in em_update_stats_counters()
4705 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { in em_update_stats_counters()
4706 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); in em_update_stats_counters()
4707 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); in em_update_stats_counters()
4709 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); in em_update_stats_counters()
4710 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); in em_update_stats_counters()
4711 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); in em_update_stats_counters()
4712 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); in em_update_stats_counters()
4714 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); in em_update_stats_counters()
4715 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); in em_update_stats_counters()
4716 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); in em_update_stats_counters()
4717 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); in em_update_stats_counters()
4718 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); in em_update_stats_counters()
4719 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); in em_update_stats_counters()
4720 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); in em_update_stats_counters()
4721 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); in em_update_stats_counters()
4726 if (sc->stats.xoffrxc != prev_xoffrxc) in em_update_stats_counters()
4727 sc->shared->isc_pause_frames = 1; in em_update_stats_counters()
4728 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); in em_update_stats_counters()
4729 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); in em_update_stats_counters()
4730 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); in em_update_stats_counters()
4731 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); in em_update_stats_counters()
4732 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); in em_update_stats_counters()
4733 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); in em_update_stats_counters()
4734 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); in em_update_stats_counters()
4735 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); in em_update_stats_counters()
4736 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); in em_update_stats_counters()
4737 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); in em_update_stats_counters()
4738 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); in em_update_stats_counters()
4739 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); in em_update_stats_counters()
4741 /* For the 64-bit byte counters the low dword must be read first. */ in em_update_stats_counters()
4744 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + in em_update_stats_counters()
4745 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); in em_update_stats_counters()
4746 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + in em_update_stats_counters()
4747 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); in em_update_stats_counters()
4749 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); in em_update_stats_counters()
4750 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); in em_update_stats_counters()
4751 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); in em_update_stats_counters()
4752 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); in em_update_stats_counters()
4753 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); in em_update_stats_counters()
4755 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); in em_update_stats_counters()
4756 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); in em_update_stats_counters()
4757 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); in em_update_stats_counters()
4759 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); in em_update_stats_counters()
4760 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); in em_update_stats_counters()
4762 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); in em_update_stats_counters()
4763 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); in em_update_stats_counters()
4764 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); in em_update_stats_counters()
4765 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); in em_update_stats_counters()
4766 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); in em_update_stats_counters()
4767 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); in em_update_stats_counters()
4768 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); in em_update_stats_counters()
4769 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); in em_update_stats_counters()
4770 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); in em_update_stats_counters()
4771 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); in em_update_stats_counters()
4775 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); in em_update_stats_counters()
4776 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); in em_update_stats_counters()
4777 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); in em_update_stats_counters()
4778 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); in em_update_stats_counters()
4779 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); in em_update_stats_counters()
4780 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); in em_update_stats_counters()
4781 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); in em_update_stats_counters()
4782 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); in em_update_stats_counters()
4783 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); in em_update_stats_counters()
4785 if (sc->hw.mac.type >= e1000_82543) { in em_update_stats_counters()
4786 sc->stats.algnerrc += in em_update_stats_counters()
4787 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); in em_update_stats_counters()
4788 sc->stats.rxerrc += in em_update_stats_counters()
4789 E1000_READ_REG(&sc->hw, E1000_RXERRC); in em_update_stats_counters()
4790 sc->stats.tncrs += in em_update_stats_counters()
4791 E1000_READ_REG(&sc->hw, E1000_TNCRS); in em_update_stats_counters()
4792 sc->stats.cexterr += in em_update_stats_counters()
4793 E1000_READ_REG(&sc->hw, E1000_CEXTERR); in em_update_stats_counters()
4794 sc->stats.tsctc += in em_update_stats_counters()
4795 E1000_READ_REG(&sc->hw, E1000_TSCTC); in em_update_stats_counters()
4796 sc->stats.tsctfc += in em_update_stats_counters()
4797 E1000_READ_REG(&sc->hw, E1000_TSCTFC); in em_update_stats_counters()
4809 return (sc->stats.colc); in em_if_get_counter()
4811 return (sc->dropped_pkts + sc->stats.rxerrc + in em_if_get_counter()
4812 sc->stats.crcerrs + sc->stats.algnerrc + in em_if_get_counter()
4813 sc->stats.ruc + sc->stats.roc + in em_if_get_counter()
4814 sc->stats.mpc + sc->stats.cexterr); in em_if_get_counter()
4816 return (sc->stats.ecol + sc->stats.latecol + in em_if_get_counter()
4817 sc->watchdog_events); in em_if_get_counter()
4823 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4841 /* Export a single 32-bit register via a read-only sysctl. */
4848 sc = oidp->oid_arg1; in em_sysctl_reg_handler()
4849 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); in em_sysctl_reg_handler()
4863 bool tx = oidp->oid_arg2; in em_sysctl_interrupt_rate_handler()
4866 tque = oidp->oid_arg1; in em_sysctl_interrupt_rate_handler()
4867 hw = &tque->sc->hw; in em_sysctl_interrupt_rate_handler()
4868 if (hw->mac.type >= igb_mac_min) in em_sysctl_interrupt_rate_handler()
4869 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); in em_sysctl_interrupt_rate_handler()
4870 else if (hw->mac.type == e1000_82574 && tque->msix) in em_sysctl_interrupt_rate_handler()
4871 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); in em_sysctl_interrupt_rate_handler()
4875 rque = oidp->oid_arg1; in em_sysctl_interrupt_rate_handler()
4876 hw = &rque->sc->hw; in em_sysctl_interrupt_rate_handler()
4877 if (hw->mac.type >= igb_mac_min) in em_sysctl_interrupt_rate_handler()
4878 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); in em_sysctl_interrupt_rate_handler()
4879 else if (hw->mac.type == e1000_82574 && rque->msix) in em_sysctl_interrupt_rate_handler()
4881 E1000_EITR_82574(rque->msix)); in em_sysctl_interrupt_rate_handler()
4886 if (hw->mac.type < igb_mac_min) { in em_sysctl_interrupt_rate_handler()
4900 if (error || !req->newptr) in em_sysctl_interrupt_rate_handler()
4911 device_t dev = iflib_get_dev(sc->ctx); in em_add_hw_stats()
4912 struct em_tx_queue *tx_que = sc->tx_queues; in em_add_hw_stats()
4913 struct em_rx_queue *rx_que = sc->rx_queues; in em_add_hw_stats()
4918 struct e1000_hw_stats *stats = &sc->stats; in em_add_hw_stats()
4928 CTLFLAG_RD, &sc->dropped_pkts, in em_add_hw_stats()
4931 CTLFLAG_RD, &sc->link_irq, in em_add_hw_stats()
4932 "Link MSI-X IRQ Handled"); in em_add_hw_stats()
4934 CTLFLAG_RD, &sc->rx_overruns, in em_add_hw_stats()
4937 CTLFLAG_RD, &sc->watchdog_events, in em_add_hw_stats()
4948 CTLFLAG_RD, &sc->hw.fc.high_water, 0, in em_add_hw_stats()
4951 CTLFLAG_RD, &sc->hw.fc.low_water, 0, in em_add_hw_stats()
4952 "Flow Control Low Watermark"); in em_add_hw_stats()
4954 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in em_add_hw_stats()
4955 struct tx_ring *txr = &tx_que->txr; in em_add_hw_stats()
4968 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
4972 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
4975 CTLFLAG_RD, &txr->tx_irq, in em_add_hw_stats()
4976 "Queue MSI-X Transmit Interrupts"); in em_add_hw_stats()
4979 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { in em_add_hw_stats()
4980 struct rx_ring *rxr = &rx_que->rxr; in em_add_hw_stats()
4993 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
4997 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", in em_add_hw_stats()
5000 CTLFLAG_RD, &rxr->rx_irq, in em_add_hw_stats()
5001 "Queue MSI-X Receive Interrupts"); in em_add_hw_stats()
5010 CTLFLAG_RD, &stats->ecol, in em_add_hw_stats()
5013 CTLFLAG_RD, &stats->scc, in em_add_hw_stats()
5016 CTLFLAG_RD, &stats->mcc, in em_add_hw_stats()
5019 CTLFLAG_RD, &stats->latecol, in em_add_hw_stats()
5022 CTLFLAG_RD, &stats->colc, in em_add_hw_stats()
5025 CTLFLAG_RD, &sc->stats.symerrs, in em_add_hw_stats()
5028 CTLFLAG_RD, &sc->stats.sec, in em_add_hw_stats()
5031 CTLFLAG_RD, &sc->stats.dc, in em_add_hw_stats()
5034 CTLFLAG_RD, &sc->stats.mpc, in em_add_hw_stats()
5037 CTLFLAG_RD, &sc->stats.rlec, in em_add_hw_stats()
5040 CTLFLAG_RD, &sc->stats.rnbc, in em_add_hw_stats()
5043 CTLFLAG_RD, &sc->stats.ruc, in em_add_hw_stats()
5046 CTLFLAG_RD, &sc->stats.rfc, in em_add_hw_stats()
5049 CTLFLAG_RD, &sc->stats.roc, in em_add_hw_stats()
5052 CTLFLAG_RD, &sc->stats.rjc, in em_add_hw_stats()
5055 CTLFLAG_RD, &sc->stats.rxerrc, in em_add_hw_stats()
5058 CTLFLAG_RD, &sc->stats.crcerrs, in em_add_hw_stats()
5061 CTLFLAG_RD, &sc->stats.algnerrc, in em_add_hw_stats()
5065 CTLFLAG_RD, &sc->stats.cexterr, in em_add_hw_stats()
5068 CTLFLAG_RD, &sc->stats.xonrxc, in em_add_hw_stats()
5071 CTLFLAG_RD, &sc->stats.xontxc, in em_add_hw_stats()
5074 CTLFLAG_RD, &sc->stats.xoffrxc, in em_add_hw_stats()
5077 CTLFLAG_RD, &sc->stats.xofftxc, in em_add_hw_stats()
5080 CTLFLAG_RD, &sc->stats.fcruc, in em_add_hw_stats()
5083 CTLFLAG_RD, &sc->stats.mgprc, in em_add_hw_stats()
5086 CTLFLAG_RD, &sc->stats.mgpdc, in em_add_hw_stats()
5089 CTLFLAG_RD, &sc->stats.mgptc, in em_add_hw_stats()
5094 CTLFLAG_RD, &sc->stats.tpr, in em_add_hw_stats()
5097 CTLFLAG_RD, &sc->stats.gprc, in em_add_hw_stats()
5100 CTLFLAG_RD, &sc->stats.bprc, in em_add_hw_stats()
5103 CTLFLAG_RD, &sc->stats.mprc, in em_add_hw_stats()
5106 CTLFLAG_RD, &sc->stats.prc64, in em_add_hw_stats()
5109 CTLFLAG_RD, &sc->stats.prc127, in em_add_hw_stats()
5110 "65-127 byte frames received"); in em_add_hw_stats()
5112 CTLFLAG_RD, &sc->stats.prc255, in em_add_hw_stats()
5113 "128-255 byte frames received"); in em_add_hw_stats()
5115 CTLFLAG_RD, &sc->stats.prc511, in em_add_hw_stats()
5116 "256-511 byte frames received"); in em_add_hw_stats()
5118 CTLFLAG_RD, &sc->stats.prc1023, in em_add_hw_stats()
5119 "512-1023 byte frames received"); in em_add_hw_stats()
5121 CTLFLAG_RD, &sc->stats.prc1522, in em_add_hw_stats()
5122 "1023-1522 byte frames received"); in em_add_hw_stats()
5124 CTLFLAG_RD, &sc->stats.gorc, in em_add_hw_stats()
5129 CTLFLAG_RD, &sc->stats.gotc, in em_add_hw_stats()
5132 CTLFLAG_RD, &sc->stats.tpt, in em_add_hw_stats()
5135 CTLFLAG_RD, &sc->stats.gptc, in em_add_hw_stats()
5138 CTLFLAG_RD, &sc->stats.bptc, in em_add_hw_stats()
5141 CTLFLAG_RD, &sc->stats.mptc, in em_add_hw_stats()
5144 CTLFLAG_RD, &sc->stats.ptc64, in em_add_hw_stats()
5147 CTLFLAG_RD, &sc->stats.ptc127, in em_add_hw_stats()
5148 "65-127 byte frames transmitted"); in em_add_hw_stats()
5150 CTLFLAG_RD, &sc->stats.ptc255, in em_add_hw_stats()
5151 "128-255 byte frames transmitted"); in em_add_hw_stats()
5153 CTLFLAG_RD, &sc->stats.ptc511, in em_add_hw_stats()
5154 "256-511 byte frames transmitted"); in em_add_hw_stats()
5156 CTLFLAG_RD, &sc->stats.ptc1023, in em_add_hw_stats()
5157 "512-1023 byte frames transmitted"); in em_add_hw_stats()
5159 CTLFLAG_RD, &sc->stats.ptc1522, in em_add_hw_stats()
5160 "1024-1522 byte frames transmitted"); in em_add_hw_stats()
5162 CTLFLAG_RD, &sc->stats.tsctc, in em_add_hw_stats()
5165 CTLFLAG_RD, &sc->stats.tsctfc, in em_add_hw_stats()
5174 CTLFLAG_RD, &sc->stats.iac, in em_add_hw_stats()
5178 CTLFLAG_RD, &sc->stats.icrxptc, in em_add_hw_stats()
5182 CTLFLAG_RD, &sc->stats.icrxatc, in em_add_hw_stats()
5186 CTLFLAG_RD, &sc->stats.ictxptc, in em_add_hw_stats()
5190 CTLFLAG_RD, &sc->stats.ictxatc, in em_add_hw_stats()
5194 CTLFLAG_RD, &sc->stats.ictxqec, in em_add_hw_stats()
5198 CTLFLAG_RD, &sc->stats.ictxqmtc, in em_add_hw_stats()
5202 CTLFLAG_RD, &sc->stats.icrxdmtc, in em_add_hw_stats()
5206 CTLFLAG_RD, &sc->stats.icrxoc, in em_add_hw_stats()
5214 struct e1000_hw *hw = &sc->hw; in em_fw_version_locked()
5215 struct e1000_fw_version *fw_ver = &sc->fw_ver; in em_fw_version_locked()
5227 if (hw->mac.type >= igb_mac_min) { in em_fw_version_locked()
5242 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; in em_fw_version_locked()
5243 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; in em_fw_version_locked()
5244 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); in em_fw_version_locked()
5253 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { in em_sbuf_fw_version()
5254 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, in em_sbuf_fw_version()
5255 fw_ver->eep_minor, fw_ver->eep_build); in em_sbuf_fw_version()
5259 if (fw_ver->invm_major || fw_ver->invm_minor || in em_sbuf_fw_version()
5260 fw_ver->invm_img_type) { in em_sbuf_fw_version()
5262 space, fw_ver->invm_major, fw_ver->invm_minor, in em_sbuf_fw_version()
5263 fw_ver->invm_img_type); in em_sbuf_fw_version()
5267 if (fw_ver->or_valid) { in em_sbuf_fw_version()
5268 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", in em_sbuf_fw_version()
5269 space, fw_ver->or_major, fw_ver->or_build, in em_sbuf_fw_version()
5270 fw_ver->or_patch); in em_sbuf_fw_version()
5274 if (fw_ver->etrack_id) in em_sbuf_fw_version()
5275 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); in em_sbuf_fw_version()
5281 device_t dev = sc->dev; in em_print_fw_version()
5291 em_sbuf_fw_version(&sc->fw_ver, buf); in em_print_fw_version()
5306 device_t dev = sc->dev; in em_sysctl_print_fw_version()
5316 em_sbuf_fw_version(&sc->fw_ver, buf); in em_sysctl_print_fw_version()
5341 result = -1; in em_sysctl_nvm_info()
5344 if (error || !req->newptr) in em_sysctl_nvm_info()
5349 * first 32 16-bit words of the EEPROM to in em_sysctl_nvm_info()
5361 struct e1000_hw *hw = &sc->hw; in em_print_nvm_info()
5362 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); in em_print_nvm_info()
5394 usecs = info->value; in em_sysctl_int_delay()
5396 if (error != 0 || req->newptr == NULL) in em_sysctl_int_delay()
5400 info->value = usecs; in em_sysctl_int_delay()
5403 sc = info->sc; in em_sysctl_int_delay()
5405 regval = E1000_READ_OFFSET(&sc->hw, info->offset); in em_sysctl_int_delay()
5408 switch (info->offset) { in em_sysctl_int_delay()
5413 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; in em_sysctl_int_delay()
5417 sc->txd_cmd |= E1000_TXD_CMD_IDE; in em_sysctl_int_delay()
5420 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); in em_sysctl_int_delay()
5431 sc = oidp->oid_arg1; in em_sysctl_tso_tcp_flags_mask()
5432 switch (oidp->oid_arg2) { in em_sysctl_tso_tcp_flags_mask()
5449 val = E1000_READ_REG(&sc->hw, reg); in em_sysctl_tso_tcp_flags_mask()
5452 if (error != 0 || req->newptr == NULL) in em_sysctl_tso_tcp_flags_mask()
5457 E1000_WRITE_REG(&sc->hw, reg, val); in em_sysctl_tso_tcp_flags_mask()
5466 info->sc = sc; in em_add_int_delay_sysctl()
5467 info->offset = offset; in em_add_int_delay_sysctl()
5468 info->value = value; in em_add_int_delay_sysctl()
5469 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), in em_add_int_delay_sysctl()
5470 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), in em_add_int_delay_sysctl()
5478 * 0 - off
5479 * 1 - rx pause
5480 * 2 - tx pause
5481 * 3 - full
5492 if ((error) || (req->newptr == NULL)) in em_set_flowcntl()
5495 if (input == sc->fc) /* no change? */ in em_set_flowcntl()
5503 sc->hw.fc.requested_mode = input; in em_set_flowcntl()
5504 sc->fc = input; in em_set_flowcntl()
5511 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; in em_set_flowcntl()
5512 e1000_force_mac_fc(&sc->hw); in em_set_flowcntl()
5519 * 0/1 - off/on
5521 * 250,500,1000-10000 in thousands
5529 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); in igb_sysctl_dmac()
5531 if ((error) || (req->newptr == NULL)) in igb_sysctl_dmac()
5534 switch (sc->dmac) { in igb_sysctl_dmac()
5539 sc->dmac = 1000; in igb_sysctl_dmac()
5553 /* Legal values - allow */ in igb_sysctl_dmac()
5557 sc->dmac = 0; in igb_sysctl_dmac()
5561 em_if_init(sc->ctx); in igb_sysctl_dmac()
5568 * 0/1 - enabled/disabled
5576 if (sc->hw.mac.type < igb_mac_min) in em_sysctl_eee()
5577 value = sc->hw.dev_spec.ich8lan.eee_disable; in em_sysctl_eee()
5579 value = sc->hw.dev_spec._82575.eee_disable; in em_sysctl_eee()
5581 if (error || req->newptr == NULL) in em_sysctl_eee()
5583 if (sc->hw.mac.type < igb_mac_min) in em_sysctl_eee()
5584 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); in em_sysctl_eee()
5586 sc->hw.dev_spec._82575.eee_disable = (value != 0); in em_sysctl_eee()
5587 em_if_init(sc->ctx); in em_sysctl_eee()
5599 result = -1; in em_sysctl_debug_info()
5602 if (error || !req->newptr) in em_sysctl_debug_info()
5623 if (error || !req->newptr || result != 1) in em_get_rs()
5638 * needed for debugging a problem. -jfv
5643 device_t dev = iflib_get_dev(sc->ctx); in em_print_debug_info()
5644 if_t ifp = iflib_get_ifp(sc->ctx); in em_print_debug_info()
5645 struct tx_ring *txr = &sc->tx_queues->txr; in em_print_debug_info()
5646 struct rx_ring *rxr = &sc->rx_queues->rxr; in em_print_debug_info()
5658 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in em_print_debug_info()
5659 device_printf(dev, "TX Queue %d ------\n", i); in em_print_debug_info()
5661 E1000_READ_REG(&sc->hw, E1000_TDH(i)), in em_print_debug_info()
5662 E1000_READ_REG(&sc->hw, E1000_TDT(i))); in em_print_debug_info()
5665 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { in em_print_debug_info()
5666 device_printf(dev, "RX Queue %d ------\n", j); in em_print_debug_info()
5668 E1000_READ_REG(&sc->hw, E1000_RDH(j)), in em_print_debug_info()
5669 E1000_READ_REG(&sc->hw, E1000_RDT(j))); in em_print_debug_info()
5675 * Write a new value to the EEPROM increasing the number of MSI-X
5682 struct e1000_hw *hw = &sc->hw; in em_enable_vectors_82574()
5691 "reported MSI-X vectors from 3 to 5...\n"); in em_enable_vectors_82574()