Lines Matching +full:0 +full:x3500
48 * Last entry must be all 0s
56 PVID(0x8086, E1000_DEV_ID_82540EM,
58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM,
60 PVID(0x8086, E1000_DEV_ID_82540EP,
62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM,
64 PVID(0x8086, E1000_DEV_ID_82540EP_LP,
67 PVID(0x8086, E1000_DEV_ID_82541EI,
69 PVID(0x8086, E1000_DEV_ID_82541ER,
71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM,
73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE,
75 PVID(0x8086, E1000_DEV_ID_82541GI,
77 PVID(0x8086, E1000_DEV_ID_82541GI_LF,
79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE,
82 PVID(0x8086, E1000_DEV_ID_82542,
85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER,
87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER,
90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER,
92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER,
94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER,
96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM,
99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER,
101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER,
103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER,
105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER,
107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES,
110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER,
112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER,
114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER,
116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER,
118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER,
120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES,
122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE,
124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER,
126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
129 PVID(0x8086, E1000_DEV_ID_82547EI,
131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE,
133 PVID(0x8086, E1000_DEV_ID_82547GI,
137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER,
139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER,
141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES,
143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL,
145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD,
147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP,
151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
155 PVID(0x8086, E1000_DEV_ID_82572EI,
157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER,
159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER,
161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES,
163 PVID(0x8086, E1000_DEV_ID_82573E,
165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT,
167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT,
179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"),
183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT,
188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT,
190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"),
198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"),
206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"),
207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"),
208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"),
209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"),
210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM,
215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2,
224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2,
226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3,
228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4,
230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5,
233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6,
236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7,
239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8,
242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9,
245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10,
248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10,
250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11,
252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11,
254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12,
256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12,
258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13,
260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13,
262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14,
264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14,
266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15,
268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15,
270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16,
272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16,
274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17,
276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17,
278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18,
280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18,
282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19,
284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19,
286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20,
288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20,
290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21,
292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21,
294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22,
296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22,
298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23,
300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23,
302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24,
304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24,
306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25,
308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25,
310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26,
312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26,
314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27,
316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27,
325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER,
327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES,
335 PVID(0x8086, E1000_DEV_ID_82576_FIBER,
337 PVID(0x8086, E1000_DEV_ID_82576_SERDES,
339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD,
341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER,
343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2,
345 PVID(0x8086, E1000_DEV_ID_82576_VF,
347 PVID(0x8086, E1000_DEV_ID_82580_COPPER,
349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
350 PVID(0x8086, E1000_DEV_ID_82580_SERDES,
352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL,
355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER,
357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES,
359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII,
361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE,
364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT,
372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS,
375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS,
377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS,
379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS,
385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS,
387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
532 DRIVER_MODULE(em, pci, em_driver, 0, 0);
544 DRIVER_MODULE(igb, pci, igb_driver, 0, 0);
637 #define CSUM_TSO 0
640 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
643 static int em_disable_crc_stripping = 0;
645 &em_disable_crc_stripping, 0, "Disable CRC Stripping");
650 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs");
652 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs");
657 &em_tx_abs_int_delay_dflt, 0,
660 &em_rx_abs_int_delay_dflt, 0,
666 0, "Set to true to leave smart power down enabled on newer adapters");
670 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations");
674 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0,
679 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
689 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)");
696 &em_max_interrupt_rate, 0, "Maximum interrupts per second");
699 static int global_quad_port_a = 0;
777 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); in em_get_regs()
779 rc = sysctl_wire_old_buffer(req, 0); in em_get_regs()
780 MPASS(rc == 0); in em_get_regs()
781 if (rc != 0) { in em_get_regs()
794 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); in em_get_regs()
799 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); in em_get_regs()
800 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); in em_get_regs()
801 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); in em_get_regs()
802 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); in em_get_regs()
803 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); in em_get_regs()
804 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); in em_get_regs()
806 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); in em_get_regs()
807 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); in em_get_regs()
808 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); in em_get_regs()
809 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); in em_get_regs()
810 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); in em_get_regs()
811 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); in em_get_regs()
818 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); in em_get_regs()
854 int ntxd = scctx->isc_ntxd[0]; in em_get_regs()
855 int nrxd = scctx->isc_nrxd[0]; in em_get_regs()
858 for (j = 0; j < nrxd; j++) { in em_get_regs()
866 for (j = 0; j < min(ntxd, 256); j++) { in em_get_regs()
870 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" in em_get_regs()
872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, in em_get_regs()
875 E1000_TXD_STAT_DD : 0); in em_get_regs()
952 * return 0 on success, positive on failure
963 int error = 0; in em_if_attach_pre()
983 CTLTYPE_INT | CTLFLAG_RW, sc, 0, in em_if_attach_pre()
988 CTLFLAG_RW, &sc->enable_aim, 0, in em_if_attach_pre()
992 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, in em_if_attach_pre()
997 CTLTYPE_INT | CTLFLAG_RW, sc, 0, in em_if_attach_pre()
1001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, in em_if_attach_pre()
1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, in em_if_attach_pre()
1009 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, in em_if_attach_pre()
1014 CTLTYPE_INT | CTLFLAG_RW, sc, 0, in em_if_attach_pre()
1021 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", in em_if_attach_pre()
1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in em_if_attach_pre()
1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in em_if_attach_pre()
1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); in em_if_attach_pre()
1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); in em_if_attach_pre()
1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * in em_if_attach_pre()
1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * in em_if_attach_pre()
1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); in em_if_attach_pre()
1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); in em_if_attach_pre()
1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * in em_if_attach_pre()
1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * in em_if_attach_pre()
1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); in em_if_attach_pre()
1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); in em_if_attach_pre()
1158 scctx->isc_msix_bar = 0; in em_if_attach_pre()
1278 sc->tso_automasked = 0; in em_if_attach_pre()
1291 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, in em_if_attach_pre()
1302 if (e1000_validate_nvm_checksum(hw) < 0) { in em_if_attach_pre()
1308 if (e1000_validate_nvm_checksum(hw) < 0) { in em_if_attach_pre()
1317 if (e1000_read_mac_addr(hw) < 0) { in em_if_attach_pre()
1347 if (sc->wol != 0) in em_if_attach_pre()
1352 return (0); in em_if_attach_pre()
1368 int error = 0; in em_if_attach_post()
1372 if (error != 0) { in em_if_attach_post()
1391 return (0); in em_if_attach_post()
1408 * return 0 on success, positive on failure
1425 return (0); in em_if_detach()
1451 return (0); in em_if_suspend()
1464 return(0); in em_if_resume()
1515 return (0); in em_if_mtu_set()
1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); in em_if_init()
1545 * With the 82571 adapter, RAR[0] may be overwritten in em_if_init()
1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; in em_if_init()
1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; in em_if_init()
1632 itr_latency_disabled = 0,
1656 if (txbytes == 0 && rxbytes == 0) in em_newitr()
1659 newitr = 0; in em_newitr()
1672 sc->enable_aim = 0; in em_newitr()
1676 bytes = bytes_per_packet = 0; in em_newitr()
1679 if (txpackets != 0) { in em_newitr()
1685 if (rxpackets != 0) { in em_newitr()
1804 struct em_rx_queue *que = &sc->rx_queues[0]; in em_intr()
1805 struct tx_ring *txr = &sc->tx_queues[0].txr; in em_intr()
1813 if (reg_icr == 0xffffffff) in em_intr()
1817 if (reg_icr == 0x0) in em_intr()
1825 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) in em_intr()
1847 txr->tx_bytes = 0; in em_intr()
1848 txr->tx_packets = 0; in em_intr()
1849 rxr->rx_bytes = 0; in em_intr()
1850 rxr->rx_packets = 0; in em_intr()
1862 return (0); in em_if_rx_queue_intr_enable()
1872 return (0); in em_if_tx_queue_intr_enable()
1882 return (0); in igb_if_rx_queue_intr_enable()
1892 return (0); in igb_if_tx_queue_intr_enable()
1913 txr->tx_bytes = 0; in em_msix_que()
1914 txr->tx_packets = 0; in em_msix_que()
1915 rxr->rx_bytes = 0; in em_msix_que()
1916 rxr->rx_packets = 0; in em_msix_que()
2087 sc->hw.phy.autoneg_advertised = 0; in em_if_media_change()
2095 sc->hw.phy.autoneg_advertised = 0; in em_if_media_change()
2107 return (0); in em_if_media_change()
2116 int mcnt = 0; in em_if_set_promisc()
2146 return (0); in em_if_set_promisc()
2155 return (0); in em_copy_maddr()
2174 u32 reg_rctl = 0; in em_if_multi_set()
2175 int mcnt = 0; in em_if_multi_set()
2232 if (qid != 0) in em_if_timer()
2247 link_check = thstat = ctrl = 0; in em_if_update_admin_status()
2288 if (link_check && (sc->link_active == 0)) { in em_if_update_admin_status()
2296 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); in em_if_update_admin_status()
2298 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); in em_if_update_admin_status()
2306 sc->smartspeed = 0; in em_if_update_admin_status()
2332 sc->link_speed = 0; in em_if_update_admin_status()
2333 sc->link_duplex = 0; in em_if_update_admin_status()
2334 sc->link_active = 0; in em_if_update_admin_status()
2335 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); in em_if_update_admin_status()
2339 /* Reset LAA into RAR[0] on 82571 */ in em_if_update_admin_status()
2341 e1000_rar_set(hw, hw->mac.addr, 0); in em_if_update_admin_status()
2378 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); in em_if_stop()
2416 sc->vf_ifp = 0; in em_identify_hardware()
2426 rid = PCIR_BAR(0); in em_allocate_pci_resources()
2441 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { in em_allocate_pci_resources()
2462 sc->hw.io_base = 0; in em_allocate_pci_resources()
2471 return (0); in em_allocate_pci_resources()
2485 int error, rid, i, vector = 0, rx_vectors; in em_if_msix_intr_assign()
2489 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { in em_if_msix_intr_assign()
2521 vector = 0; in em_if_msix_intr_assign()
2522 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { in em_if_msix_intr_assign()
2551 em_msix_link, sc, 0, "aq"); in em_if_msix_intr_assign()
2561 sc->ivars |= 0x80000000; in em_if_msix_intr_assign()
2566 return (0); in em_if_msix_intr_assign()
2570 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) in em_if_msix_intr_assign()
2581 u32 tmp, ivar = 0, newitr = 0; in igb_configure_queues()
2599 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2604 ivar &= 0xFF00FFFF; in igb_configure_queues()
2608 ivar &= 0xFFFFFF00; in igb_configure_queues()
2614 for (int i = 0; i < sc->tx_num_queues; i++) { in igb_configure_queues()
2619 ivar &= 0x00FFFFFF; in igb_configure_queues()
2623 ivar &= 0xFFFF00FF; in igb_configure_queues()
2638 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2639 u32 index = i & 0x7; /* Each IVAR has two entries */ in igb_configure_queues()
2643 ivar &= 0xFFFFFF00; in igb_configure_queues()
2646 ivar &= 0xFF00FFFF; in igb_configure_queues()
2654 for (int i = 0; i < sc->tx_num_queues; i++) { in igb_configure_queues()
2655 u32 index = i & 0x7; /* Each IVAR has two entries */ in igb_configure_queues()
2659 ivar &= 0xFFFF00FF; in igb_configure_queues()
2663 ivar &= 0x00FFFFFF; in igb_configure_queues()
2687 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2692 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, in igb_configure_queues()
2706 if (em_max_interrupt_rate > 0) { in igb_configure_queues()
2714 for (int i = 0; i < sc->rx_num_queues; i++) { in igb_configure_queues()
2735 for (int i = 0; i < sc->rx_num_queues; i++, que++) { in em_free_pci_resources()
2768 return (0); in em_setup_msix()
2782 sc->hw.mac.autoneg == 0 || in lem_smartspeed()
2783 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) in lem_smartspeed()
2786 if (sc->smartspeed == 0) { in lem_smartspeed()
2828 sc->smartspeed = 0; in lem_smartspeed()
2851 if (sc->dmac == 0) { /* Disabling it */ in igb_init_dmac()
2858 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); in igb_init_dmac()
2900 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); in igb_init_dmac()
2908 ** which is 0x4*2 = 0xA. But delay is still 4 usec in igb_init_dmac()
2914 reg |= 0xA; in igb_init_dmac()
2916 reg |= 0x4; in igb_init_dmac()
2918 reg |= 0x4; in igb_init_dmac()
2936 E1000_WRITE_REG(hw, E1000_DMACR, 0); in igb_init_dmac()
2967 txd->upper.data = 0; in em_flush_tx_ring()
2972 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); in em_flush_tx_ring()
2993 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); in em_flush_rx_ring()
2995 rxdctl &= 0xffffc000; in em_flush_rx_ring()
3001 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); in em_flush_rx_ring()
3002 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); in em_flush_rx_ring()
3035 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); in em_flush_desc_rings()
3071 u16 phy_tmp = 0; in em_reset()
3161 pba &= 0xffff; in em_reset()
3202 rx_buffer_size = (pba & 0xffff) << 10; in em_reset()
3213 hw->fc.pause_time = 0xFFFF; in em_reset()
3224 hw->fc.pause_time = 0xFFFF; /* override */ in em_reset()
3226 hw->fc.high_water = 0x3500; in em_reset()
3227 hw->fc.low_water = 0x1500; in em_reset()
3229 hw->fc.high_water = 0x5000; in em_reset()
3230 hw->fc.low_water = 0x3000; in em_reset()
3232 hw->fc.refresh_time = 0x1000; in em_reset()
3242 hw->fc.high_water = 0x5C20; in em_reset()
3243 hw->fc.low_water = 0x5048; in em_reset()
3244 hw->fc.pause_time = 0x0650; in em_reset()
3245 hw->fc.refresh_time = 0x0400; in em_reset()
3270 hw->fc.high_water = 0x2800; in em_reset()
3277 hw->fc.pause_time = 0xFFFF; in em_reset()
3288 E1000_WRITE_REG(hw, E1000_WUC, 0); in em_reset()
3290 E1000_WRITE_REG(hw, E1000_WUFC, 0); in em_reset()
3299 if (e1000_init_hw(hw) < 0) { in em_reset()
3324 uint32_t reta = 0; in em_initialize_rss_mapping()
3331 arc4rand(rss_key, sizeof(rss_key), 0); in em_initialize_rss_mapping()
3332 for (i = 0; i < RSSKEYLEN; ++i) { in em_initialize_rss_mapping()
3333 uint32_t rssrk = 0; in em_initialize_rss_mapping()
3343 for (i = 0; i < sizeof(reta); ++i) { in em_initialize_rss_mapping()
3350 for (i = 0; i < 32; ++i) in em_initialize_rss_mapping()
3368 u32 rss_key[10], mrqc, shift = 0; in igb_initialize_rss_mapping()
3388 reta = 0; in igb_initialize_rss_mapping()
3389 for (i = 0; i < 128; i++) { in igb_initialize_rss_mapping()
3413 * The low 8 bits are for hash value (n+0); in igb_initialize_rss_mapping()
3420 reta = 0; in igb_initialize_rss_mapping()
3436 arc4rand(&rss_key, sizeof(rss_key), 0); in igb_initialize_rss_mapping()
3438 for (i = 0; i < 10; i++) in igb_initialize_rss_mapping()
3439 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); in igb_initialize_rss_mapping()
3472 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); in em_setup_interface()
3487 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); in em_setup_interface()
3488 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); in em_setup_interface()
3490 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); in em_setup_interface()
3492 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); in em_setup_interface()
3493 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); in em_setup_interface()
3495 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); in em_setup_interface()
3498 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); in em_setup_interface()
3500 IFM_ETHER | IFM_1000_T, 0, NULL); in em_setup_interface()
3503 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); in em_setup_interface()
3505 return (0); in em_setup_interface()
3518 MPASS(sc->tx_num_queues > 0); in em_if_tx_queues_alloc()
3530 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { in em_if_tx_queues_alloc()
3539 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], in em_if_tx_queues_alloc()
3546 for (j = 0; j < scctx->isc_ntxd[0]; j++) in em_if_tx_queues_alloc()
3556 return (0); in em_if_tx_queues_alloc()
3571 MPASS(sc->rx_num_queues > 0); in em_if_rx_queues_alloc()
3584 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { in em_if_rx_queues_alloc()
3601 return (0); in em_if_rx_queues_alloc()
3615 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in em_if_queues_free()
3646 u32 tctl, txdctl = 0, tarc, tipg = 0; in em_initialize_transmit_unit()
3650 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in em_initialize_transmit_unit()
3665 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); in em_initialize_transmit_unit()
3669 E1000_WRITE_REG(hw, E1000_TDT(i), 0); in em_initialize_transmit_unit()
3670 E1000_WRITE_REG(hw, E1000_TDH(i), 0); in em_initialize_transmit_unit()
3676 txdctl = 0; /* clear txdctl */ in em_initialize_transmit_unit()
3677 txdctl |= 0x1f; /* PTHRESH */ in em_initialize_transmit_unit()
3713 if (sc->tx_int_delay.value > 0) in em_initialize_transmit_unit()
3721 tarc = E1000_READ_REG(hw, E1000_TARC(0)); in em_initialize_transmit_unit()
3723 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); in em_initialize_transmit_unit()
3726 tarc = E1000_READ_REG(hw, E1000_TARC(0)); in em_initialize_transmit_unit()
3728 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); in em_initialize_transmit_unit()
3733 tarc = E1000_READ_REG(hw, E1000_TARC(0)); in em_initialize_transmit_unit()
3737 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); in em_initialize_transmit_unit()
3740 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); in em_initialize_transmit_unit()
3762 reg = E1000_READ_REG(hw, E1000_TARC(0)); in em_initialize_transmit_unit()
3765 E1000_WRITE_REG(hw, E1000_TARC(0), reg); in em_initialize_transmit_unit()
3835 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); in em_initialize_receive_unit()
3852 for (int i = 0; i < 4; i++) in em_initialize_receive_unit()
3889 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { in em_initialize_receive_unit()
3893 #if 0 in em_initialize_receive_unit()
3898 scctx->isc_nrxd[0] * in em_initialize_receive_unit()
3903 E1000_WRITE_REG(hw, E1000_RDH(i), 0); in em_initialize_receive_unit()
3904 E1000_WRITE_REG(hw, E1000_RDT(i), 0); in em_initialize_receive_unit()
3910 * RXDCTL(1) is written whenever RXDCTL(0) is written. in em_initialize_receive_unit()
3916 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); in em_initialize_receive_unit()
3917 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); in em_initialize_receive_unit()
3919 for (int i = 0; i < sc->rx_num_queues; i++) { in em_initialize_receive_unit()
3921 rxdctl |= 0x20; /* PTHRESH */ in em_initialize_receive_unit()
3928 u32 psize, srrctl = 0; in em_initialize_receive_unit()
3959 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; in em_initialize_receive_unit()
3973 scctx->isc_nrxd[0] * in em_initialize_receive_unit()
3983 rxdctl &= 0xFFF00000; in em_initialize_receive_unit()
4021 rctl &= ~0x00000C00; in em_initialize_receive_unit()
4035 index = (vtag >> 5) & 0x7F; in em_if_vlan_register()
4036 bit = vtag & 0x1F; in em_if_vlan_register()
4048 index = (vtag >> 5) & 0x7F; in em_if_vlan_unregister()
4049 bit = vtag & 0x1F; in em_if_vlan_unregister()
4075 for (int i = 0; i < EM_VFTA_SIZE; i++) in em_if_vlan_filter_used()
4076 if (sc->shadow_vfta[i] != 0) in em_if_vlan_filter_used()
4117 for (int i = 0; i < EM_VFTA_SIZE; i++) in em_if_vlan_filter_write()
4118 if (sc->shadow_vfta[i] != 0) { in em_if_vlan_filter_write()
4166 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged in em_setup_vlan_hw_support()
4169 em_if_vlan_register(ctx, 0); in em_setup_vlan_hw_support()
4198 E1000_WRITE_REG(hw, EM_EIAC, 0); in em_if_intr_disable()
4199 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in em_if_intr_disable()
4228 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); in igb_if_intr_disable()
4229 E1000_WRITE_REG(hw, E1000_EIAC, 0); in igb_if_intr_disable()
4231 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in igb_if_intr_disable()
4337 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; in em_is_valid_ether_addr()
4339 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { in em_is_valid_ether_addr()
4360 if_setcapenablebit(ifp, 0, IFCAP_TSO); in em_automask_tso()
4367 if_setcapenablebit(ifp, sc->tso_automasked, 0); in em_automask_tso()
4368 sc->tso_automasked = 0; in em_automask_tso()
4387 u16 eeprom_data = 0, device_id, apme_mask; in em_get_wakeup()
4461 sc->wol = 0; in em_get_wakeup()
4469 sc->wol = 0; in em_get_wakeup()
4473 if (global_quad_port_a != 0) in em_get_wakeup()
4474 sc->wol = 0; in em_get_wakeup()
4477 global_quad_port_a = 0; in em_get_wakeup()
4484 sc->wol = 0; in em_get_wakeup()
4490 if (global_quad_port_a != 0) in em_get_wakeup()
4491 sc->wol = 0; in em_get_wakeup()
4494 global_quad_port_a = 0; in em_get_wakeup()
4510 int error = 0; in em_enable_wakeup()
4520 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) in em_enable_wakeup()
4523 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) in em_enable_wakeup()
4526 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) in em_enable_wakeup()
4584 u32 mreg, ret = 0; in em_enable_phy_wakeup()
4591 for (int i = 0; i < hw->mac.mta_reg_count; i++) { in em_enable_phy_wakeup()
4593 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); in em_enable_phy_wakeup()
4595 (u16)((mreg >> 16) & 0xFFFF)); in em_enable_phy_wakeup()
4682 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) in em_disable_aspm()
4686 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) in em_disable_aspm()
4851 return (sysctl_handle_int(oidp, &val, 0, req)); in em_sysctl_reg_handler()
4888 if (reg > 0) in em_sysctl_interrupt_rate_handler()
4891 rate = 0; in em_sysctl_interrupt_rate_handler()
4894 if (usec > 0) in em_sysctl_interrupt_rate_handler()
4897 rate = 0; in em_sysctl_interrupt_rate_handler()
4900 error = sysctl_handle_int(oidp, &rate, 0, req); in em_sysctl_interrupt_rate_handler()
4903 return 0; in em_sysctl_interrupt_rate_handler()
4949 CTLFLAG_RD, &sc->hw.fc.high_water, 0, in em_add_hw_stats()
4952 CTLFLAG_RD, &sc->hw.fc.low_water, 0, in em_add_hw_stats()
4955 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { in em_add_hw_stats()
4980 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { in em_add_hw_stats()
5217 uint16_t eep = 0; in em_fw_version_locked()
5226 *fw_ver = (struct e1000_fw_version){0}; in em_fw_version_locked()
5276 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); in em_sbuf_fw_version()
5284 int error = 0; in em_print_fw_version()
5309 int error = 0; in em_sysctl_print_fw_version()
5325 return (0); in em_sysctl_print_fw_version()
5343 error = sysctl_handle_int(oidp, &result, 0, req); in em_sysctl_nvm_info()
5365 int i, j, row = 0; in em_print_nvm_info()
5374 for (i = 0, j = 0; i < 32; i++, j++) { in em_print_nvm_info()
5376 j = 0; ++row; in em_print_nvm_info()
5396 error = sysctl_handle_int(oidp, &usecs, 0, req); in em_sysctl_int_delay()
5397 if (error != 0 || req->newptr == NULL) in em_sysctl_int_delay()
5399 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) in em_sysctl_int_delay()
5407 regval = (regval & ~0xffff) | (ticks & 0xffff); in em_sysctl_int_delay()
5413 if (ticks == 0) { in em_sysctl_int_delay()
5415 /* Don't write 0 into the TIDV register. */ in em_sysctl_int_delay()
5422 return (0); in em_sysctl_int_delay()
5434 case 0: in em_sysctl_tso_tcp_flags_mask()
5436 shift = 0; in em_sysctl_tso_tcp_flags_mask()
5444 shift = 0; in em_sysctl_tso_tcp_flags_mask()
5451 mask = (val >> shift) & 0xfff; in em_sysctl_tso_tcp_flags_mask()
5452 error = sysctl_handle_int(oidp, &mask, 0, req); in em_sysctl_tso_tcp_flags_mask()
5453 if (error != 0 || req->newptr == NULL) in em_sysctl_tso_tcp_flags_mask()
5455 if (mask < 0 || mask > 0xfff) in em_sysctl_tso_tcp_flags_mask()
5457 val = (val & ~(0xfff << shift)) | (mask << shift); in em_sysctl_tso_tcp_flags_mask()
5459 return (0); in em_sysctl_tso_tcp_flags_mask()
5473 info, 0, em_sysctl_int_delay, "I", description); in em_add_int_delay_sysctl()
5479 * 0 - off
5491 error = sysctl_handle_int(oidp, &input, 0, req); in em_set_flowcntl()
5520 * 0/1 - off/on
5530 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); in igb_sysctl_dmac()
5536 case 0: in igb_sysctl_dmac()
5558 sc->dmac = 0; in igb_sysctl_dmac()
5569 * 0/1 - enabled/disabled
5581 error = sysctl_handle_int(oidp, &value, 0, req); in em_sysctl_eee()
5585 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); in em_sysctl_eee()
5587 sc->hw.dev_spec._82575.eee_disable = (value != 0); in em_sysctl_eee()
5590 return (0); in em_sysctl_eee()
5601 error = sysctl_handle_int(oidp, &result, 0, req); in em_sysctl_debug_info()
5621 result = 0; in em_get_rs()
5622 error = sysctl_handle_int(oidp, &result, 0, req); in em_get_rs()
5659 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { in em_print_debug_info()
5666 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { in em_print_debug_info()