Lines Matching +full:spi +full:- +full:crc
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
46 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
59 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
60 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
61 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
62 #define E1000_FEXT 0x0002C /* Future Extended - RW */
63 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
64 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
65 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
66 #define E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */
67 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
68 #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
69 #define E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */
70 #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */
71 #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
72 #define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */
75 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
76 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
77 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
78 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
79 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
80 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
81 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
82 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
84 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
88 #define E1000_RCTL 0x00100 /* Rx Control - RW */
89 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
90 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
91 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
93 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
95 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
96 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
97 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
98 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
99 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
100 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
101 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
102 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
103 #define E1000_TCTL 0x00400 /* Tx Control - RW */
104 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
105 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
106 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
107 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
108 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
114 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
116 #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
123 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
128 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
129 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
130 #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */
131 #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */
132 #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */
133 #define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */
134 #define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */
135 #define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */
136 #define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */
137 #define E1000_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */
138 #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
139 #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
140 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
141 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
142 #define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */
143 #define E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */
144 #define E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */
145 #define E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */
146 #define E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */
147 #define E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */
148 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
149 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
150 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
151 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
152 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
153 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
154 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
155 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
156 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
157 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
158 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
159 /* Split and Replication Rx Control - RW */
160 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
161 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
162 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
163 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
164 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
165 #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */
166 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
167 #define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */
168 #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */
169 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
170 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
173 /* Shadow Ram Write Register - RW */
219 /* Queues priority masks where _n and _p can be 0-3. */
232 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
284 #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
285 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
286 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
290 (0x054E0 + ((_i - 16) * 8)))
292 (0x054E4 + ((_i - 16) * 8)))
303 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
304 /* Same as TXPBS, renamed for newer Si - RW */
306 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
307 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
308 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
309 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
310 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
311 #define E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */
312 #define E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */
313 #define E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */
314 #define E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */
315 #define E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */
316 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
317 #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
318 #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
319 /* DMA Tx Max Total Allow Size Reqs - RW */
321 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
322 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
323 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
325 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
326 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
327 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
328 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
329 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
330 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
331 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
332 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
333 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
334 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
335 #define E1000_DC 0x04030 /* Defer Count - R/clr */
336 #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
337 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
338 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
339 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
340 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
341 #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
342 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
343 #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
344 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
345 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
346 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
347 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
348 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
349 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
350 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
351 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
352 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
353 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
354 #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
355 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
356 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
357 #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
358 #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
359 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
360 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
361 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
362 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
363 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
364 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
365 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
366 #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
367 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
368 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
369 #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
370 #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
371 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
372 #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
373 #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
374 #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
375 #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
376 #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
377 #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
378 #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
379 #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
380 #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
381 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
382 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
393 #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */
421 #define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */
435 #define E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */
436 #define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */
437 #define E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */
438 #define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */
439 #define E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */
440 #define E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */
441 #define E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */
442 #define E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */
443 #define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */
444 #define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */
445 #define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */
446 /* LinkSec Tx 128-bit Key 0 - WO */
448 /* LinkSec Tx 128-bit Key 1 - WO */
450 #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
451 #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
452 /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
453 * key - RW.
459 #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */
460 #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */
461 /* IPSec Rx IPv4/v6 Address - RW */
463 /* IPSec Rx 128-bit Key - RW */
465 #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */
466 #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */
467 /* IPSec Tx 128-bit Key - RW */
469 #define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */
470 #define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */
471 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
472 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
473 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
488 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
489 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
490 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
491 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */
492 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
495 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
496 #define E1000_RA 0x05400 /* Receive Address - RW Array */
497 #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */
498 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
499 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
500 #define E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */
501 #define E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */
502 #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
503 #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
504 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
505 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
506 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
508 #define E1000_MANC 0x05820 /* Management Control - RW */
509 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
510 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
511 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
512 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
513 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
514 /* MSI-X Table Register Descriptions */
515 #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
516 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
525 #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
526 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
530 #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
535 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
536 #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
537 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
538 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
539 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
540 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
545 /* Driver-only SW semaphore (not used by BOOT agents) */
547 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
548 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
549 #define E1000_UFUSE 0x05B78 /* UFUSE - RO */
555 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
556 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
559 #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
560 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
561 /* Redirection Table - RW Array */
563 /* RSS Random Key - RW Array */
568 #define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */
569 #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
570 #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
571 #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
574 #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
575 #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
576 #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */
577 #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
578 #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
595 /* VLAN Virtual Machine Filter - RW */
600 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
601 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
602 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
603 #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
604 #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
605 #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
606 #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
607 #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
608 #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
609 #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
610 #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
611 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
612 #define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */
613 #define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */
622 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
623 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
629 #define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
630 #define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
647 /* Tx Desc plane TC Rate-scheduler config */
649 /* Tx Packet plane TC Rate-Scheduler Config */
651 /* Rx Packet plane TC Rate-Scheduler Config */
653 /* Tx Desc Plane TC Rate-Scheduler Status */
655 /* Tx Desc Plane TC Rate-Scheduler MMW */
657 /* Tx Packet plane TC Rate-Scheduler Status */
659 /* Tx Packet plane TC Rate-scheduler MMW */
661 /* Rx Packet plane TC Rate-Scheduler Status */
663 /* Rx Packet plane TC Rate-Scheduler MMW */
665 /* Tx Desc plane VM Rate-Scheduler MMW*/
667 /* Tx BCN Rate-Scheduler MMW */
670 #define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */
671 #define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */
672 #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */
673 #define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */
710 #define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */
711 #define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */