Lines Matching +full:0 +full:xe14
132 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
133 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
134 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
135 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
136 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
137 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
138 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
141 #define PHY_REG_MASK 0x1F
144 #define GS40G_PAGE_SELECT 0x16
146 #define GS40G_OFFSET_MASK 0xFFFF
147 #define GS40G_PAGE_2 0x20000
148 #define GS40G_MAC_REG2 0x15
149 #define GS40G_MAC_LB 0x4140
150 #define GS40G_MAC_SPEED_1G 0X0006
151 #define GS40G_COPPER_SPEC 0x0010
156 #define BM_WUC_ADDRESS_OPCODE 0x11
157 #define BM_WUC_DATA_OPCODE 0x12
167 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
170 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
191 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
192 #define I82577_PHY_STATUS2_MDIX 0x0800
193 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
194 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
197 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
198 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
199 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
202 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
206 #define E1000_82580_PHY_POWER_MGMT 0xE14
207 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
208 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
209 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
210 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
212 #define E1000_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */
213 #define E1000_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */
214 #define E1000_MPHY_BUSY 0x00010000 /* busy bit */
215 #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */
216 #define E1000_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */
223 #define BM_CS_STATUS_LINK_UP 0x0400
224 #define BM_CS_STATUS_RESOLVED 0x0800
225 #define BM_CS_STATUS_SPEED_MASK 0xC000
226 #define BM_CS_STATUS_SPEED_1000 0x8000
230 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
231 #define HV_M_STATUS_SPEED_MASK 0x0300
232 #define HV_M_STATUS_SPEED_1000 0x0200
233 #define HV_M_STATUS_SPEED_100 0x0100
234 #define HV_M_STATUS_LINK_UP 0x0040
236 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
237 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
239 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
240 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
242 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
245 #define IGP01E1000_GMII_FLEX_SPD 0x0010
246 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
248 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
249 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
250 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
252 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
254 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
255 #define IGP01E1000_PSSR_MDIX 0x0800
256 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
257 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
260 #define IGP02E1000_PHY_AGC_A 0x11B1
261 #define IGP02E1000_PHY_AGC_B 0x12B1
262 #define IGP02E1000_PHY_AGC_C 0x14B1
263 #define IGP02E1000_PHY_AGC_D 0x18B1
266 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
269 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
271 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
273 #define E1000_KMRNCTRLSTA_REN 0x00200000
274 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
275 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
276 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
277 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
278 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
279 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
280 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
281 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
282 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
283 #define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
284 #define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
291 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
292 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
293 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
294 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
297 #define IFE_PESC_POLARITY_REVERSED 0x0100
300 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
301 #define IFE_PSC_FORCE_POLARITY 0x0020
304 #define IFE_PSCL_PROBE_MODE 0x0020
305 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
306 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
309 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
310 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
311 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
314 #define E1000_SFF_IDENTIFIER_OFFSET 0x00
315 #define E1000_SFF_IDENTIFIER_SFF 0x02
316 #define E1000_SFF_IDENTIFIER_SFP 0x03
318 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06
331 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
332 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600
333 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500
334 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00
335 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100