Lines Matching +full:hw +full:- +full:timeout +full:- +full:ms
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
66 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
121 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
132 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
133 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
170 /* Half-duplex collision counts */
220 /* Strapping Option Register - RO */
231 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
250 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
332 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
334 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
335 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
336 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
337 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
338 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
339 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
340 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
341 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
342 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
343 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
344 s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
345 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
346 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);