Lines Matching +full:0 +full:x0400
38 #define ICH_FLASH_GFPREG 0x0000
39 #define ICH_FLASH_HSFSTS 0x0004
40 #define ICH_FLASH_HSFCTL 0x0006
41 #define ICH_FLASH_FADDR 0x0008
42 #define ICH_FLASH_FDATA0 0x0010
48 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
51 #define ICH_CYCLE_READ 0
55 #define FLASH_GFPREG_BASE_MASK 0x1FFF
63 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
65 #define E1000_ICH_FWSM_FW_VALID 0x00008000
66 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
69 #define E1000_ICH_MNG_IAMT_MODE 0x2
71 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380
73 #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
76 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
77 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
79 #define E1000_H2ME 0x05B50 /* Host to ME */
80 #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
81 #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
88 #define E1000_ICH_NVM_SIG_WORD 0x13
89 #define E1000_ICH_NVM_SIG_MASK 0xC000
90 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
91 #define E1000_ICH_NVM_SIG_VALUE 0x80
96 #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
101 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
102 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
104 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
105 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
106 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
108 #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
109 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
110 #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
112 #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
113 #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
114 #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
115 #define E1000_FEXTNVM8_UNBIND_DPG_FROM_MPHY 0x00000400
116 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
117 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
118 #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200
119 #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
120 #define E1000_FEXTNVM12_DONT_WAK_DPG_CLKREQ 0x00001000
121 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
122 #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
125 #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
126 #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
127 #define E1000_TARC0_CB_MULTIQ_3_REQ 0x30000000
128 #define E1000_TARC0_CB_MULTIQ_2_REQ 0x20000000
132 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
133 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
141 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
142 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
143 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
147 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
157 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
158 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
161 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
162 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
163 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
167 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
168 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
186 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
188 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
189 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
190 #define K1_ENTRY_LATENCY 0
195 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
199 #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
200 #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
201 #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
202 #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
203 #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
204 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
206 #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400
208 #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800
209 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
213 #define HV_SMB_ADDR_MASK 0x007F
214 #define HV_SMB_ADDR_PEC_EN 0x0200
215 #define HV_SMB_ADDR_VALID 0x0080
216 #define HV_SMB_ADDR_FREQ_MASK 0x1100
221 #define E1000_STRAP 0x0000C
222 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
224 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000
229 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
230 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
231 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
235 #define HV_KMRN_MDIO_SLOW 0x0400
239 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
244 #define HV_PM_CTRL_K1_CLK_REQ 0x200
245 #define HV_PM_CTRL_K1_ENABLE 0x4000
248 #define I217_PLL_CLOCK_GATE_MASK 0x07FF
254 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
259 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800
263 #define I82579_LPI_CTRL_100_ENABLE 0x2000
264 #define I82579_LPI_CTRL_1000_ENABLE 0x4000
265 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
269 #define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */
272 #define I82579_EMI_ADDR 0x10
273 #define I82579_EMI_DATA 0x11
274 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
275 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
276 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
277 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
278 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */
279 #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
280 #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
281 #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
282 #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
283 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
287 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
288 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
289 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
290 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
291 #define I217_RX_CONFIG 0xB20C /* Receive configuration */
293 #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
294 #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
298 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
300 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
302 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002
304 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
307 #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
310 #define E1000_LTRV 0x000F8
311 #define E1000_LTRV_VALUE_MASK 0x000003FF
315 #define E1000_LTRV_SCALE_MASK 0x00001C00
321 #define E1000_PCI_LTR_CAP_LPT 0xA8
324 #define E1000_SVCR_OFF_EN 0x00000001
325 #define E1000_SVCR_OFF_MASKINT 0x00001000
326 #define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000
328 #define E1000_SVT_OFF_HWM_MASK 0x0000001F
330 #define E1000_PCI_VENDOR_ID_REGISTER 0x00