Lines Matching +full:timer +full:- +full:cannot +full:- +full:wake +full:- +full:cpu
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
36 * 82562G-2 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
53 * 82567LF-3 Gigabit Network Connection
54 * 82567LM-3 Gigabit Network Connection
55 * 82567LM-4 Gigabit Network Connection
62 * Ethernet Connection I217-LM
63 * Ethernet Connection I217-V
64 * Ethernet Connection I218-V
65 * Ethernet Connection I218-LM
66 * Ethernet Connection (2) I218-LM
67 * Ethernet Connection (2) I218-V
68 * Ethernet Connection (3) I218-LM
69 * Ethernet Connection (3) I218-V
162 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
192 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
224 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
225 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
228 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
229 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
236 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
237 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
241 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
247 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_phy_is_accessible_pchlan()
267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
270 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
296 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
304 E1000_CTRL_EXT_LPCD) && count--); in e1000_toggle_lanphypc_pch_lpt()
311 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
325 * non-managed 82579 and newer adapters. in e1000_init_phy_workarounds_pchlan()
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
337 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
343 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is in e1000_init_phy_workarounds_pchlan()
347 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
378 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
382 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
384 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
390 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
404 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
411 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
415 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
435 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
441 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_init_phy_workarounds_pchlan()
442 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
452 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
455 * Initialize family-specific PHY parameters and function pointers.
459 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
464 phy->addr = 1; in e1000_init_phy_params_pchlan()
465 phy->reset_delay_us = 100; in e1000_init_phy_params_pchlan()
467 phy->ops.acquire = e1000_acquire_swflag_ich8lan; in e1000_init_phy_params_pchlan()
468 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; in e1000_init_phy_params_pchlan()
469 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; in e1000_init_phy_params_pchlan()
470 phy->ops.set_page = e1000_set_page_igp; in e1000_init_phy_params_pchlan()
471 phy->ops.read_reg = e1000_read_phy_reg_hv; in e1000_init_phy_params_pchlan()
472 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
473 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
474 phy->ops.release = e1000_release_swflag_ich8lan; in e1000_init_phy_params_pchlan()
475 phy->ops.reset = e1000_phy_hw_reset_ich8lan; in e1000_init_phy_params_pchlan()
476 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
477 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
478 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
479 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
480 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
481 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_pchlan()
482 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_pchlan()
483 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_pchlan()
485 phy->id = e1000_phy_unknown; in e1000_init_phy_params_pchlan()
491 if (phy->id == e1000_phy_unknown) in e1000_init_phy_params_pchlan()
492 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
497 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) in e1000_init_phy_params_pchlan()
519 phy->type = e1000_get_phy_type_from_id(phy->id); in e1000_init_phy_params_pchlan()
521 switch (phy->type) { in e1000_init_phy_params_pchlan()
525 phy->ops.check_polarity = e1000_check_polarity_82577; in e1000_init_phy_params_pchlan()
526 phy->ops.force_speed_duplex = in e1000_init_phy_params_pchlan()
528 phy->ops.get_cable_length = e1000_get_cable_length_82577; in e1000_init_phy_params_pchlan()
529 phy->ops.get_info = e1000_get_phy_info_82577; in e1000_init_phy_params_pchlan()
530 phy->ops.commit = e1000_phy_sw_reset_generic; in e1000_init_phy_params_pchlan()
533 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_pchlan()
534 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; in e1000_init_phy_params_pchlan()
535 phy->ops.get_cable_length = e1000_get_cable_length_m88; in e1000_init_phy_params_pchlan()
536 phy->ops.get_info = e1000_get_phy_info_m88; in e1000_init_phy_params_pchlan()
539 ret_val = -E1000_ERR_PHY; in e1000_init_phy_params_pchlan()
547 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
550 * Initialize family-specific PHY parameters and function pointers.
554 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
560 phy->addr = 1; in e1000_init_phy_params_ich8lan()
561 phy->reset_delay_us = 100; in e1000_init_phy_params_ich8lan()
563 phy->ops.acquire = e1000_acquire_swflag_ich8lan; in e1000_init_phy_params_ich8lan()
564 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan; in e1000_init_phy_params_ich8lan()
565 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; in e1000_init_phy_params_ich8lan()
566 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan; in e1000_init_phy_params_ich8lan()
567 phy->ops.read_reg = e1000_read_phy_reg_igp; in e1000_init_phy_params_ich8lan()
568 phy->ops.release = e1000_release_swflag_ich8lan; in e1000_init_phy_params_ich8lan()
569 phy->ops.reset = e1000_phy_hw_reset_ich8lan; in e1000_init_phy_params_ich8lan()
570 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan; in e1000_init_phy_params_ich8lan()
571 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan; in e1000_init_phy_params_ich8lan()
572 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_ich8lan()
573 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_ich8lan()
574 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_ich8lan()
576 /* We may need to do this twice - once for IGP and if that fails, in e1000_init_phy_params_ich8lan()
581 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
582 phy->ops.read_reg = e1000_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
585 DEBUGOUT("Cannot determine PHY addr. Erroring out\n"); in e1000_init_phy_params_ich8lan()
590 phy->id = 0; in e1000_init_phy_params_ich8lan()
591 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) && in e1000_init_phy_params_ich8lan()
600 switch (phy->id) { in e1000_init_phy_params_ich8lan()
602 phy->type = e1000_phy_igp_3; in e1000_init_phy_params_ich8lan()
603 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
604 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
605 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
606 phy->ops.get_info = e1000_get_phy_info_igp; in e1000_init_phy_params_ich8lan()
607 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_ich8lan()
608 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; in e1000_init_phy_params_ich8lan()
613 phy->type = e1000_phy_ife; in e1000_init_phy_params_ich8lan()
614 phy->autoneg_mask = E1000_ALL_NOT_GIG; in e1000_init_phy_params_ich8lan()
615 phy->ops.get_info = e1000_get_phy_info_ife; in e1000_init_phy_params_ich8lan()
616 phy->ops.check_polarity = e1000_check_polarity_ife; in e1000_init_phy_params_ich8lan()
617 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; in e1000_init_phy_params_ich8lan()
620 phy->type = e1000_phy_bm; in e1000_init_phy_params_ich8lan()
621 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
622 phy->ops.read_reg = e1000_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
623 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
624 phy->ops.commit = e1000_phy_sw_reset_generic; in e1000_init_phy_params_ich8lan()
625 phy->ops.get_info = e1000_get_phy_info_m88; in e1000_init_phy_params_ich8lan()
626 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_ich8lan()
627 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; in e1000_init_phy_params_ich8lan()
630 return -E1000_ERR_PHY; in e1000_init_phy_params_ich8lan()
638 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
641 * Initialize family-specific NVM parameters and function
646 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
647 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
654 nvm->type = e1000_nvm_flash_sw; in e1000_init_nvm_params_ich8lan()
656 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
663 nvm->flash_base_addr = 0; in e1000_init_nvm_params_ich8lan()
667 nvm->flash_bank_size = nvm_size / 2; in e1000_init_nvm_params_ich8lan()
669 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
671 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
674 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
676 return -E1000_ERR_CONFIG; in e1000_init_nvm_params_ich8lan()
681 /* sector_X_addr is a "sector"-aligned address (4096 bytes) in e1000_init_nvm_params_ich8lan()
688 /* flash_base_addr is byte-aligned */ in e1000_init_nvm_params_ich8lan()
689 nvm->flash_base_addr = sector_base_addr in e1000_init_nvm_params_ich8lan()
695 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) in e1000_init_nvm_params_ich8lan()
697 nvm->flash_bank_size /= 2; in e1000_init_nvm_params_ich8lan()
699 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
702 nvm->word_size = E1000_SHADOW_RAM_WORDS; in e1000_init_nvm_params_ich8lan()
705 for (i = 0; i < nvm->word_size; i++) { in e1000_init_nvm_params_ich8lan()
706 dev_spec->shadow_ram[i].modified = false; in e1000_init_nvm_params_ich8lan()
707 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_init_nvm_params_ich8lan()
711 nvm->ops.acquire = e1000_acquire_nvm_ich8lan; in e1000_init_nvm_params_ich8lan()
712 nvm->ops.release = e1000_release_nvm_ich8lan; in e1000_init_nvm_params_ich8lan()
713 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
714 nvm->ops.read = e1000_read_nvm_spt; in e1000_init_nvm_params_ich8lan()
715 nvm->ops.update = e1000_update_nvm_checksum_spt; in e1000_init_nvm_params_ich8lan()
717 nvm->ops.read = e1000_read_nvm_ich8lan; in e1000_init_nvm_params_ich8lan()
718 nvm->ops.update = e1000_update_nvm_checksum_ich8lan; in e1000_init_nvm_params_ich8lan()
720 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan; in e1000_init_nvm_params_ich8lan()
721 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan; in e1000_init_nvm_params_ich8lan()
722 nvm->ops.write = e1000_write_nvm_ich8lan; in e1000_init_nvm_params_ich8lan()
728 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
731 * Initialize family-specific MAC parameters and function
736 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan()
741 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
744 mac->mta_reg_count = 32; in e1000_init_mac_params_ich8lan()
746 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
747 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
748 mac->rar_entry_count--; in e1000_init_mac_params_ich8lan()
750 mac->asf_firmware_present = true; in e1000_init_mac_params_ich8lan()
752 mac->has_fwsm = true; in e1000_init_mac_params_ich8lan()
754 mac->arc_subsystem_valid = false; in e1000_init_mac_params_ich8lan()
756 mac->adaptive_ifs = true; in e1000_init_mac_params_ich8lan()
761 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan; in e1000_init_mac_params_ich8lan()
763 mac->ops.set_lan_id = e1000_set_lan_id_single_port; in e1000_init_mac_params_ich8lan()
765 mac->ops.reset_hw = e1000_reset_hw_ich8lan; in e1000_init_mac_params_ich8lan()
767 mac->ops.init_hw = e1000_init_hw_ich8lan; in e1000_init_mac_params_ich8lan()
769 mac->ops.setup_link = e1000_setup_link_ich8lan; in e1000_init_mac_params_ich8lan()
771 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan; in e1000_init_mac_params_ich8lan()
773 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan; in e1000_init_mac_params_ich8lan()
775 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan; in e1000_init_mac_params_ich8lan()
777 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; in e1000_init_mac_params_ich8lan()
779 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan; in e1000_init_mac_params_ich8lan()
782 switch (mac->type) { in e1000_init_mac_params_ich8lan()
787 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; in e1000_init_mac_params_ich8lan()
789 mac->ops.id_led_init = e1000_id_led_init_generic; in e1000_init_mac_params_ich8lan()
791 mac->ops.blink_led = e1000_blink_led_generic; in e1000_init_mac_params_ich8lan()
793 mac->ops.setup_led = e1000_setup_led_generic; in e1000_init_mac_params_ich8lan()
795 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; in e1000_init_mac_params_ich8lan()
797 mac->ops.led_on = e1000_led_on_ich8lan; in e1000_init_mac_params_ich8lan()
798 mac->ops.led_off = e1000_led_off_ich8lan; in e1000_init_mac_params_ich8lan()
801 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
802 mac->ops.rar_set = e1000_rar_set_pch2lan; in e1000_init_mac_params_ich8lan()
812 mac->ops.update_mc_addr_list = in e1000_init_mac_params_ich8lan()
817 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; in e1000_init_mac_params_ich8lan()
819 mac->ops.id_led_init = e1000_id_led_init_pchlan; in e1000_init_mac_params_ich8lan()
821 mac->ops.setup_led = e1000_setup_led_pchlan; in e1000_init_mac_params_ich8lan()
823 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; in e1000_init_mac_params_ich8lan()
825 mac->ops.led_on = e1000_led_on_pchlan; in e1000_init_mac_params_ich8lan()
826 mac->ops.led_off = e1000_led_off_pchlan; in e1000_init_mac_params_ich8lan()
832 if (mac->type >= e1000_pch_lpt) { in e1000_init_mac_params_ich8lan()
833 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
834 mac->ops.rar_set = e1000_rar_set_pch_lpt; in e1000_init_mac_params_ich8lan()
835 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt; in e1000_init_mac_params_ich8lan()
836 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt; in e1000_init_mac_params_ich8lan()
839 /* Enable PCS Lock-loss workaround for ICH8 */ in e1000_init_mac_params_ich8lan()
840 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
847 * __e1000_access_emi_reg_locked - Read/write EMI register
862 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); in __e1000_access_emi_reg_locked()
867 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, in __e1000_access_emi_reg_locked()
870 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, in __e1000_access_emi_reg_locked()
877 * e1000_read_emi_reg_locked - Read Extended Management Interface register
892 * e1000_write_emi_reg_locked - Write Extended Management Interface register
907 * e1000_set_eee_pchlan - Enable/disable EEE support
917 * enabled immediately upon link up since they have a timer in hardware which
922 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
928 switch (hw->phy.type) { in e1000_set_eee_pchlan()
943 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
947 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); in e1000_set_eee_pchlan()
955 if (!dev_spec->eee_disable) { in e1000_set_eee_pchlan()
958 &dev_spec->eee_lp_ability); in e1000_set_eee_pchlan()
970 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) in e1000_set_eee_pchlan()
973 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { in e1000_set_eee_pchlan()
974 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); in e1000_set_eee_pchlan()
979 * partner's EEE in 100 ability if full-duplex in e1000_set_eee_pchlan()
982 dev_spec->eee_lp_ability &= in e1000_set_eee_pchlan()
987 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
998 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ in e1000_set_eee_pchlan()
1003 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); in e1000_set_eee_pchlan()
1005 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
1011 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
1017 * the de-assertion of the clock request when in 1Gpbs mode.
1018 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1029 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
1057 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1062 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
1067 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); in e1000_k1_workaround_lpt_lp()
1089 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); in e1000_k1_workaround_lpt_lp()
1112 * e1000_platform_pm_pch_lpt - Set platform power management values
1116 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1120 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1123 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1124 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1128 * high-water mark.
1147 if (!hw->mac.max_frame_size) { in e1000_platform_pm_pch_lpt()
1149 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1152 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1155 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1164 * a 3-bit encoded scale (only 0-5 are valid) multiplied by in e1000_platform_pm_pch_lpt()
1165 * a 10-bit value (0-1023) to provide a range from 1 ns to in e1000_platform_pm_pch_lpt()
1166 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, in e1000_platform_pm_pch_lpt()
1169 lat_ns = ((s64)rxa * 1024 - in e1000_platform_pm_pch_lpt()
1170 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; in e1000_platform_pm_pch_lpt()
1183 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1201 obff_hwm = (s32)(rxa - lat_ns); in e1000_platform_pm_pch_lpt()
1205 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1209 /* Set Snoop and No-Snoop latencies the same */ in e1000_platform_pm_pch_lpt()
1221 /* Always unblock interrupts to the CPU even when the system is in e1000_platform_pm_pch_lpt()
1222 * in OBFF mode. This ensures that small round-robin traffic in e1000_platform_pm_pch_lpt()
1232 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1241 s32 timer; in e1000_set_obff_timer_pch_lpt() local
1245 /* Convert ITR value into microseconds for OBFF timer */ in e1000_set_obff_timer_pch_lpt()
1246 timer = itr & E1000_ITR_MASK; in e1000_set_obff_timer_pch_lpt()
1247 timer = (timer * E1000_ITR_MULT) / 1000; in e1000_set_obff_timer_pch_lpt()
1249 if ((timer < 0) || (timer > E1000_ITR_MASK)) { in e1000_set_obff_timer_pch_lpt()
1250 DEBUGOUT1("Invalid OBFF timer %d\n", timer); in e1000_set_obff_timer_pch_lpt()
1251 return -E1000_ERR_CONFIG; in e1000_set_obff_timer_pch_lpt()
1256 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT; in e1000_set_obff_timer_pch_lpt()
1263 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1279 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1280 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1281 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1282 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1283 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1284 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1301 /* Bail if link is re-acquired */ in e1000_enable_ulp_lpt_lp()
1303 return -E1000_ERR_PHY; in e1000_enable_ulp_lpt_lp()
1318 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1337 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1385 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1394 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1399 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1405 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1409 * Un-configure ULP mode when link is up, the system is transitioned from
1411 * system, poll for an indication from ME that ULP has been un-configured.
1412 * If not on an ME enabled system, un-configure the ULP mode by software.
1416 * the driver or during Sx->S0 transitions, this is called with force=true
1427 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1428 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1429 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1430 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1431 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1432 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1437 /* Request ME un-configure ULP mode in the PHY */ in e1000_disable_ulp_lpt_lp()
1444 if (hw->mac.type == e1000_pch_cnp) in e1000_disable_ulp_lpt_lp()
1450 ret_val = -E1000_ERR_PHY; in e1000_disable_ulp_lpt_lp()
1472 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1506 * hardware. Re-Enable K1 in the PHY when exiting ULP. in e1000_disable_ulp_lpt_lp()
1538 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1540 hw->phy.ops.reset(hw); in e1000_disable_ulp_lpt_lp()
1547 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1553 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1562 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan()
1570 /* We only want to go out to the PHY registers to see if Auto-Neg in e1000_check_for_copper_link_ich8lan()
1575 if (!mac->get_link_status) in e1000_check_for_copper_link_ich8lan()
1586 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1592 /* When connected at 10Mbps half-duplex, some parts are excessively in e1000_check_for_copper_link_ich8lan()
1596 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1607 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1619 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1623 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1630 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1631 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, in e1000_check_for_copper_link_ich8lan()
1638 hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1643 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1648 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1652 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1657 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1662 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1666 ret_val = hw->phy.ops.read_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1670 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1679 hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1682 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1686 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1690 ret_val = hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1693 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1706 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1715 /* Work-around I218 hang issue */ in e1000_check_for_copper_link_ich8lan()
1716 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1717 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1718 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1719 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1724 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1734 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1736 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1739 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1740 /* FEXTNVM6 K1-off workaround - for SPT only */ in e1000_check_for_copper_link_ich8lan()
1749 if (hw->dev_spec.ich8lan.disable_k1_off == true) in e1000_check_for_copper_link_ich8lan()
1761 mac->get_link_status = false; in e1000_check_for_copper_link_ich8lan()
1763 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1770 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1776 /* Workaround for PCHx parts in half-duplex: in e1000_check_for_copper_link_ich8lan()
1781 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); in e1000_check_for_copper_link_ich8lan()
1788 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); in e1000_check_for_copper_link_ich8lan()
1795 * immediately after link-up in e1000_check_for_copper_link_ich8lan()
1800 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1809 if (!mac->autoneg) in e1000_check_for_copper_link_ich8lan()
1810 return -E1000_ERR_CONFIG; in e1000_check_for_copper_link_ich8lan()
1812 /* Auto-Neg is enabled. Auto Speed Detection takes care in e1000_check_for_copper_link_ich8lan()
1816 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1818 /* Configure Flow Control now that Auto-Neg has completed. in e1000_check_for_copper_link_ich8lan()
1820 * settings because we may have had to re-autoneg with a in e1000_check_for_copper_link_ich8lan()
1831 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1834 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1840 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1841 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1842 switch (hw->mac.type) { in e1000_init_function_pointers_ich8lan()
1846 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1857 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; in e1000_init_function_pointers_ich8lan()
1865 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1880 * e1000_release_nvm_ich8lan - Release NVM mutex
1893 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1914 timeout--; in e1000_acquire_swflag_ich8lan()
1919 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1934 timeout--; in e1000_acquire_swflag_ich8lan()
1942 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1951 * e1000_release_swflag_ich8lan - Release software control flag
1974 * e1000_check_mng_mode_ich8lan - Checks management mode
1995 * e1000_check_mng_mode_pchlan - Checks management mode
2015 * e1000_rar_set_pch2lan - Set receive address register
2022 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
2023 * Use SHRA[0-3] in place of those reserved for ME.
2052 /* RAR[1-6] are owned by manageability. Skip those and program the in e1000_rar_set_pch2lan()
2055 if (index < (u32) (hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
2062 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
2064 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
2070 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
2071 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
2074 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", in e1000_rar_set_pch2lan()
2075 (index - 1), E1000_READ_REG(hw, E1000_FWSM)); in e1000_rar_set_pch2lan()
2080 return -E1000_ERR_CONFIG; in e1000_rar_set_pch2lan()
2084 * e1000_rar_set_pch_lpt - Set receive address registers
2091 * contain the MAC address. SHRA[0-10] are the shared receive address
2122 * it is using - those registers are unavailable for use. in e1000_rar_set_pch_lpt()
2124 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
2141 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), in e1000_rar_set_pch_lpt()
2144 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), in e1000_rar_set_pch_lpt()
2151 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2152 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2159 return -E1000_ERR_CONFIG; in e1000_rar_set_pch_lpt()
2163 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2183 ret_val = hw->phy.ops.acquire(hw); in e1000_update_mc_addr_list_pch2lan()
2191 for (i = 0; i < hw->mac.mta_reg_count; i++) { in e1000_update_mc_addr_list_pch2lan()
2192 hw->phy.ops.write_reg_page(hw, BM_MTA(i), in e1000_update_mc_addr_list_pch2lan()
2193 (u16)(hw->mac.mta_shadow[i] & in e1000_update_mc_addr_list_pch2lan()
2195 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), in e1000_update_mc_addr_list_pch2lan()
2196 (u16)((hw->mac.mta_shadow[i] >> 16) & in e1000_update_mc_addr_list_pch2lan()
2203 hw->phy.ops.release(hw); in e1000_update_mc_addr_list_pch2lan()
2207 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2235 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2259 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2261 if (freq--) { in e1000_write_smbus_addr()
2266 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); in e1000_write_smbus_addr()
2276 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2284 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2297 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2299 if (phy->type != e1000_phy_igp_3) in e1000_sw_lcd_config_ich8lan()
2302 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2303 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2323 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2335 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2348 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2350 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2373 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, in e1000_sw_lcd_config_ich8lan()
2378 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), in e1000_sw_lcd_config_ich8lan()
2392 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, in e1000_sw_lcd_config_ich8lan()
2399 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2404 * e1000_k1_gig_workaround_hv - K1 Si workaround
2417 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2421 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2425 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2431 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2432 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, in e1000_k1_gig_workaround_hv()
2447 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2448 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, in e1000_k1_gig_workaround_hv()
2464 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), in e1000_k1_gig_workaround_hv()
2471 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), in e1000_k1_gig_workaround_hv()
2480 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2486 * e1000_configure_k1_ich8lan - Configure K1 power state
2493 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2540 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2556 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2559 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2563 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2575 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); in e1000_oem_bits_config_ich8lan()
2597 /* Set Restart auto-neg to activate the bits */ in e1000_oem_bits_config_ich8lan()
2598 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2599 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2602 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); in e1000_oem_bits_config_ich8lan()
2605 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2612 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2622 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); in e1000_set_mdio_slow_mode_hv()
2628 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); in e1000_set_mdio_slow_mode_hv()
2634 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2645 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2649 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2655 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2656 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2657 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2659 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2664 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, in e1000_hv_phy_workarounds_ich8lan()
2670 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2674 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2676 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, in e1000_hv_phy_workarounds_ich8lan()
2684 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2688 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2690 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2702 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2705 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); in e1000_hv_phy_workarounds_ich8lan()
2708 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, in e1000_hv_phy_workarounds_ich8lan()
2716 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2722 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2733 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2741 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2743 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2745 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2749 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2751 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2759 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2772 for (j = 8; j > 0; j--) { in e1000_calc_rx_da_crc()
2773 mask = (crc & 1) * (-1); in e1000_calc_rx_da_crc()
2781 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2795 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2799 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2800 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), in e1000_lv_jumbo_workaround_ich8lan()
2809 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2865 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2868 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2871 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2873 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2876 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2879 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2882 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); in e1000_lv_jumbo_workaround_ich8lan()
2885 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2886 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | in e1000_lv_jumbo_workaround_ich8lan()
2924 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2926 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2929 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2931 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2934 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2937 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2940 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); in e1000_lv_jumbo_workaround_ich8lan()
2943 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2944 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & in e1000_lv_jumbo_workaround_ich8lan()
2950 /* re-enable Rx path after enabling/disabling workaround */ in e1000_lv_jumbo_workaround_ich8lan()
2951 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & in e1000_lv_jumbo_workaround_ich8lan()
2956 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2966 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2974 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2984 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
2990 * e1000_k1_gig_workaround_lv - K1 Si workaround
3003 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
3007 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); in e1000_k1_workaround_lv()
3018 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, in e1000_k1_workaround_lv()
3023 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, in e1000_k1_workaround_lv()
3040 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
3053 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
3067 * e1000_lan_init_done_ich8lan - Check for PHY config completion
3084 } while ((!data) && --loop); in e1000_lan_init_done_ich8lan()
3100 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3110 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
3116 /* Perform any necessary post-reset workarounds */ in e1000_post_phy_reset_ich8lan()
3117 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
3133 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
3134 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); in e1000_post_phy_reset_ich8lan()
3136 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); in e1000_post_phy_reset_ich8lan()
3147 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
3148 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_post_phy_reset_ich8lan()
3155 /* Set EEE LPI Update Timer to 200usec */ in e1000_post_phy_reset_ich8lan()
3156 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
3162 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
3169 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3182 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ in e1000_phy_hw_reset_ich8lan()
3183 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
3195 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3202 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3211 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); in e1000_set_lplu_state_pchlan()
3220 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
3223 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); in e1000_set_lplu_state_pchlan()
3227 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3241 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
3248 if (phy->type == e1000_phy_ife) in e1000_set_d0_lplu_state_ich8lan()
3257 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3263 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3267 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3273 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3282 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3290 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state_ich8lan()
3291 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3298 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3303 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state_ich8lan()
3304 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3311 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3323 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3337 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3350 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3358 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state_ich8lan()
3359 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3366 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3371 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state_ich8lan()
3372 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3379 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3385 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in e1000_set_d3_lplu_state_ich8lan()
3386 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in e1000_set_d3_lplu_state_ich8lan()
3387 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in e1000_set_d3_lplu_state_ich8lan()
3391 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3397 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3401 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3408 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3417 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3427 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3428 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); in e1000_valid_nvm_bank_detect_ich8lan()
3436 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3443 bank1_offset = nvm->flash_bank_size; in e1000_valid_nvm_bank_detect_ich8lan()
3475 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3488 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); in e1000_valid_nvm_bank_detect_ich8lan()
3518 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3523 * e1000_read_nvm_spt - NVM access for SPT
3534 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3535 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3545 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_spt()
3548 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_spt()
3552 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3560 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_spt()
3566 if (words - i == 1) { in e1000_read_nvm_spt()
3567 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_spt()
3569 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3571 offset_to_read = act_offset + i - in e1000_read_nvm_spt()
3586 if (!(dev_spec->shadow_ram[offset + i].modified) || in e1000_read_nvm_spt()
3587 !(dev_spec->shadow_ram[offset + i + 1].modified)) { in e1000_read_nvm_spt()
3595 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3597 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3600 if (dev_spec->shadow_ram[offset + i + 1].modified) in e1000_read_nvm_spt()
3602 dev_spec->shadow_ram[offset + i + 1].value; in e1000_read_nvm_spt()
3608 nvm->ops.release(hw); in e1000_read_nvm_spt()
3618 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3629 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3630 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3638 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_ich8lan()
3641 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_ich8lan()
3645 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3653 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_ich8lan()
3658 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_ich8lan()
3659 data[i] = dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_ich8lan()
3670 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3680 * e1000_flash_cycle_init_ich8lan - Initialize flash
3689 s32 ret_val = -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3698 return -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3704 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3724 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3751 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3758 DEBUGOUT("Flash controller busy, cannot get access\n"); in e1000_flash_cycle_init_ich8lan()
3766 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3781 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3787 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3804 return -E1000_ERR_NVM; in e1000_flash_cycle_ich8lan()
3808 * e1000_read_flash_dword_ich8lan - Read dword from flash
3822 return -E1000_ERR_NVM; in e1000_read_flash_dword_ich8lan()
3831 * e1000_read_flash_word_ich8lan - Read word from flash
3845 return -E1000_ERR_NVM; in e1000_read_flash_word_ich8lan()
3854 * e1000_read_flash_byte_ich8lan - Read byte from flash
3870 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3871 return -E1000_ERR_NVM; in e1000_read_flash_byte_ich8lan()
3884 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3899 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3905 return -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3907 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3918 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_read_flash_data_ich8lan()
3950 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data_ich8lan()
3960 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3973 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3979 hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3980 return -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3982 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
3996 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_read_flash_data32_ich8lan()
4028 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data32_ich8lan()
4038 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
4049 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
4050 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
4055 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_write_nvm_ich8lan()
4058 return -E1000_ERR_NVM; in e1000_write_nvm_ich8lan()
4061 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
4064 dev_spec->shadow_ram[offset + i].modified = true; in e1000_write_nvm_ich8lan()
4065 dev_spec->shadow_ram[offset + i].value = data[i]; in e1000_write_nvm_ich8lan()
4068 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
4074 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
4086 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
4087 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
4098 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_spt()
4101 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
4114 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
4120 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
4135 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_spt()
4137 dword |= (dev_spec->shadow_ram[i].value & 0xffff); in e1000_update_nvm_checksum_spt()
4139 if (dev_spec->shadow_ram[i + 1].modified) { in e1000_update_nvm_checksum_spt()
4141 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) in e1000_update_nvm_checksum_spt()
4154 if (i == E1000_ICH_NVM_SIG_WORD - 1) in e1000_update_nvm_checksum_spt()
4186 --act_offset; in e1000_update_nvm_checksum_spt()
4199 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; in e1000_update_nvm_checksum_spt()
4213 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_spt()
4214 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_spt()
4218 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
4224 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
4236 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4248 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
4249 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
4260 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_ich8lan()
4263 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
4276 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4282 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4289 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_ich8lan()
4290 data = dev_spec->shadow_ram[i].value; in e1000_update_nvm_checksum_ich8lan()
4366 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_ich8lan()
4367 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_ich8lan()
4371 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4377 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4389 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4410 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4427 ret_val = hw->nvm.ops.read(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4433 ret_val = hw->nvm.ops.write(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4436 ret_val = hw->nvm.ops.update(hw); in e1000_validate_nvm_checksum_ich8lan()
4445 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4465 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4467 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4470 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4474 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4485 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4493 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_write_flash_data_ich8lan()
4499 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4534 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data_ich8lan()
4543 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4561 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4563 return -E1000_ERR_NVM; in e1000_write_flash_data32_ich8lan()
4566 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4577 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4585 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_write_flash_data32_ich8lan()
4592 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4623 DEBUGOUT("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data32_ich8lan()
4632 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4650 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4681 return -E1000_ERR_NVM; in e1000_retry_write_flash_dword_ich8lan()
4687 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4715 return -E1000_ERR_NVM; in e1000_retry_write_flash_byte_ich8lan()
4721 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4730 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4734 /* bank size is in 16bit words - adjust to bytes */ in e1000_erase_flash_bank_ich8lan()
4735 u32 flash_bank_size = nvm->flash_bank_size * 2; in e1000_erase_flash_bank_ich8lan()
4775 return -E1000_ERR_NVM; in e1000_erase_flash_bank_ich8lan()
4779 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4794 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4804 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4841 * e1000_valid_led_default_ich8lan - Set the default LED settings
4855 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_ich8lan()
4868 * e1000_id_led_init_pchlan - store LED configurations
4882 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan()
4891 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4895 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); in e1000_id_led_init_pchlan()
4896 mac->ledctl_mode1 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4897 mac->ledctl_mode2 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4906 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4907 mac->ledctl_mode1 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4912 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4913 mac->ledctl_mode1 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4923 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4924 mac->ledctl_mode2 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4929 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4930 mac->ledctl_mode2 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4942 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4950 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4957 /* ICH devices are "PCI Express"-ish. They have in e1000_get_bus_info_ich8lan()
4962 if (bus->width == e1000_bus_width_unknown) in e1000_get_bus_info_ich8lan()
4963 bus->width = e1000_bus_width_pcie_x1; in e1000_get_bus_info_ich8lan()
4969 * e1000_reset_hw_ich8lan - Reset the hardware
4977 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
4985 /* Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_ich8lan()
4990 DEBUGOUT("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_ich8lan()
5006 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
5013 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
5020 dev_spec->nvm_k1_enabled = true; in e1000_reset_hw_ich8lan()
5022 dev_spec->nvm_k1_enabled = false; in e1000_reset_hw_ich8lan()
5027 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
5028 /* Full-chip reset requires MAC and PHY reset at the same in e1000_reset_hw_ich8lan()
5035 * non-managed 82579 in e1000_reset_hw_ich8lan()
5037 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
5053 /* cannot issue a flush here because it hangs the hardware */ in e1000_reset_hw_ich8lan()
5065 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
5074 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
5087 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
5101 * e1000_init_hw_ich8lan - Initialize the hardware
5105 * - initialize hardware bits
5106 * - initialize LED identification
5107 * - setup receive address registers
5108 * - setup flow control
5109 * - setup transmit descriptors
5110 * - clear statistics
5114 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan()
5124 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
5130 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
5134 for (i = 0; i < mac->mta_reg_count; i++) in e1000_init_hw_ich8lan()
5141 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
5142 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); in e1000_init_hw_ich8lan()
5144 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); in e1000_init_hw_ich8lan()
5151 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
5153 /* Set the transmit descriptor write-back policy for both queues */ in e1000_init_hw_ich8lan()
5170 if (mac->type == e1000_ich8lan) in e1000_init_hw_ich8lan()
5177 if (mac->type >= e1000_pch_tgp) { in e1000_init_hw_ich8lan()
5198 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5213 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ in e1000_initialize_hw_bits_ich8lan()
5214 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
5230 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5245 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
5251 /* work-around descriptor data corruption issue during nfs v2 udp in e1000_initialize_hw_bits_ich8lan()
5260 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5265 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
5279 * e1000_setup_link_ich8lan - Setup flow control and link settings
5283 * control. Calls the appropriate media-specific link configuration
5298 if (hw->fc.requested_mode == e1000_fc_default) in e1000_setup_link_ich8lan()
5299 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
5304 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
5306 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", in e1000_setup_link_ich8lan()
5307 hw->fc.current_mode); in e1000_setup_link_ich8lan()
5309 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_setup_link_ich8lan()
5311 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
5316 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
5317 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
5318 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
5319 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
5320 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
5321 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
5323 ret_val = hw->phy.ops.write_reg(hw, in e1000_setup_link_ich8lan()
5325 hw->fc.pause_time); in e1000_setup_link_ich8lan()
5334 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5374 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5393 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, in e1000_setup_copper_link_ich8lan()
5400 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5412 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, in e1000_setup_copper_link_ich8lan()
5425 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5452 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5472 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5473 (hw->phy.type == e1000_phy_igp_3) && in e1000_get_link_up_info_ich8lan()
5482 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5485 * Work-around for 82566 Kumeran PCS lock loss:
5487 * speed is gigabit-
5498 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5506 if (!dev_spec->kmrn_lock_loss_workaround_enabled) in e1000_kmrn_lock_loss_workaround_ich8lan()
5519 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5523 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5532 hw->phy.ops.reset(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5547 return -E1000_ERR_PHY; in e1000_kmrn_lock_loss_workaround_ich8lan()
5551 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5555 * If ICH8, set the current Kumeran workaround state (enabled - true
5556 * /disabled - false).
5561 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5565 if (hw->mac.type != e1000_ich8lan) { in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5570 dev_spec->kmrn_lock_loss_workaround_enabled = state; in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5576 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5579 * Workaround for 82566 power-down on D3 entry:
5581 * 2) write VR power-down enable
5593 if (hw->phy.type != e1000_phy_igp_3) in e1000_igp3_phy_powerdown_workaround_ich8lan()
5607 if (hw->mac.type == e1000_ich8lan) in e1000_igp3_phy_powerdown_workaround_ich8lan()
5610 /* Write VR power-down enable */ in e1000_igp3_phy_powerdown_workaround_ich8lan()
5611 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5613 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, in e1000_igp3_phy_powerdown_workaround_ich8lan()
5617 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5630 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5635 * 1) Set Kumeran Near-end loopback
5636 * 2) Clear Kumeran Near-end loopback
5646 if ((hw->mac.type != e1000_ich8lan) || in e1000_gig_downshift_workaround_ich8lan()
5647 (hw->phy.type == e1000_phy_ife)) in e1000_gig_downshift_workaround_ich8lan()
5666 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5681 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5690 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5691 u16 phy_reg, device_id = hw->device_id; in e1000_suspend_workarounds_ich8lan()
5697 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5704 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5708 if (!dev_spec->eee_disable) { in e1000_suspend_workarounds_ich8lan()
5724 (dev_spec->eee_lp_ability & in e1000_suspend_workarounds_ich8lan()
5726 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5731 hw->phy.ops.read_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5735 hw->phy.ops.write_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5751 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, in e1000_suspend_workarounds_ich8lan()
5754 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, in e1000_suspend_workarounds_ich8lan()
5760 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5762 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); in e1000_suspend_workarounds_ich8lan()
5765 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5767 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); in e1000_suspend_workarounds_ich8lan()
5773 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5775 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); in e1000_suspend_workarounds_ich8lan()
5778 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5783 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5786 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5790 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5793 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5797 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5804 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5807 * During Sx to S0 transitions on non-managed devices or managed devices
5808 * on which PHY resets are not blocked, if the PHY registers cannot be
5818 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5832 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5835 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5842 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); in e1000_resume_workarounds_pchlan()
5844 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); in e1000_resume_workarounds_pchlan()
5851 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, in e1000_resume_workarounds_pchlan()
5856 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); in e1000_resume_workarounds_pchlan()
5859 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); in e1000_resume_workarounds_pchlan()
5862 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, in e1000_resume_workarounds_pchlan()
5867 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); in e1000_resume_workarounds_pchlan()
5871 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5878 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5887 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5888 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_cleanup_led_ich8lan()
5891 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5896 * e1000_led_on_ich8lan - Turn LEDs on
5905 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5906 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_on_ich8lan()
5909 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5914 * e1000_led_off_ich8lan - Turn LEDs off
5923 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5924 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_off_ich8lan()
5927 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5932 * e1000_setup_led_pchlan - Configures SW controllable LED
5941 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, in e1000_setup_led_pchlan()
5942 (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5946 * e1000_cleanup_led_pchlan - Restore the default LED operation
5955 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, in e1000_cleanup_led_pchlan()
5956 (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5960 * e1000_led_on_pchlan - Turn LEDs on
5967 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5988 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); in e1000_led_on_pchlan()
5992 * e1000_led_off_pchlan - Turn LEDs off
5999 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
6020 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); in e1000_led_off_pchlan()
6024 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
6028 * and configure the PHY through s/w for EEPROM-less parts.
6030 * NOTE: some silicon which is EEPROM-less will fail trying to read the
6032 * to return with error, EEPROM-less silicon would not be able to be reset
6046 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
6065 DEBUGOUT("PHY Reset Asserted not set - needs delay\n"); in e1000_get_cfg_done_ich8lan()
6068 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
6070 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
6077 ret_val = -E1000_ERR_CONFIG; in e1000_get_cfg_done_ich8lan()
6085 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6089 * driver unload, or wake on lan is not enabled, remove the link.
6094 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
6095 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
6102 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6132 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
6133 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
6134 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
6135 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
6136 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
6139 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
6143 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6144 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6145 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6146 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6147 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6148 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6149 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6150 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6151 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6152 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6153 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6154 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6155 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6156 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6158 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()
6163 * e1000_configure_k0s_lpt - Configure K0s power state
6165 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6167 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6174 * -E1000_ERR_PHY (-2) in case of access error
6175 * -E1000_ERR_PARAM (-4) in case of parameters error
6185 return -E1000_ERR_PARAM; in e1000_configure_k0s_lpt()