Lines Matching full:hw
74 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
75 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
76 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
77 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
78 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
80 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
81 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
82 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
83 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
84 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
87 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
90 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
92 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
94 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
98 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
100 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
102 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
103 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
105 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
106 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
111 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
112 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
114 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
118 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
121 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
122 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
123 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
124 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
128 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
130 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
132 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
134 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
136 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
138 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
140 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
142 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
143 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
145 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
146 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
147 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
148 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
193 * @hw: pointer to the HW structure
199 * Assumes the sw/fw/hw semaphore is already acquired.
201 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) in e1000_phy_is_accessible_pchlan() argument
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
224 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
225 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
228 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
229 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
236 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
237 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
238 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_phy_is_accessible_pchlan()
240 ret_val = e1000_get_phy_id(hw); in e1000_phy_is_accessible_pchlan()
241 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
247 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
249 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_phy_is_accessible_pchlan()
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_phy_is_accessible_pchlan()
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_phy_is_accessible_pchlan()
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_phy_is_accessible_pchlan()
268 * @hw: pointer to the HW structure
273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) in e1000_toggle_lanphypc_pch_lpt() argument
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3); in e1000_toggle_lanphypc_pch_lpt()
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_toggle_lanphypc_pch_lpt()
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
290 E1000_WRITE_FLUSH(hw); in e1000_toggle_lanphypc_pch_lpt()
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
294 E1000_WRITE_FLUSH(hw); in e1000_toggle_lanphypc_pch_lpt()
296 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) & in e1000_toggle_lanphypc_pch_lpt()
312 * @hw: pointer to the HW structure
317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) in e1000_init_phy_workarounds_pchlan() argument
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_init_phy_workarounds_pchlan()
327 e1000_gate_hw_phy_config_ich8lan(hw, true); in e1000_init_phy_workarounds_pchlan()
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
333 ret_val = e1000_disable_ulp_lpt_lp(hw, true); in e1000_init_phy_workarounds_pchlan()
337 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
347 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
355 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
361 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_phy_workarounds_pchlan()
363 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
373 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
378 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
382 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
389 e1000_toggle_lanphypc_pch_lpt(hw); in e1000_init_phy_workarounds_pchlan()
390 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
391 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
397 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_phy_workarounds_pchlan()
399 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_init_phy_workarounds_pchlan()
401 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
411 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
415 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
425 ret_val = e1000_phy_hw_reset_generic(hw); in e1000_init_phy_workarounds_pchlan()
435 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
442 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
445 e1000_gate_hw_phy_config_ich8lan(hw, false); in e1000_init_phy_workarounds_pchlan()
453 * @hw: pointer to the HW structure
457 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) in e1000_init_phy_params_pchlan() argument
459 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
487 ret_val = e1000_init_phy_workarounds_pchlan(hw); in e1000_init_phy_params_pchlan()
492 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
494 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_pchlan()
511 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_init_phy_params_pchlan()
514 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_pchlan()
548 * @hw: pointer to the HW structure
552 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) in e1000_init_phy_params_ich8lan() argument
554 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
579 ret_val = e1000_determine_phy_address(hw); in e1000_init_phy_params_ich8lan()
583 ret_val = e1000_determine_phy_address(hw); in e1000_init_phy_params_ich8lan()
594 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_ich8lan()
639 * @hw: pointer to the HW structure
644 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) in e1000_init_nvm_params_ich8lan() argument
646 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
647 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
656 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
665 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1) in e1000_init_nvm_params_ich8lan()
671 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
674 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
679 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG); in e1000_init_nvm_params_ich8lan()
713 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
729 * @hw: pointer to the HW structure
734 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) in e1000_init_mac_params_ich8lan() argument
736 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan()
741 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
766 /* hw initialization */ in e1000_init_mac_params_ich8lan()
841 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true); in e1000_init_mac_params_ich8lan()
848 * @hw: pointer to the HW structure
853 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
855 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, in __e1000_access_emi_reg_locked() argument
862 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address); in __e1000_access_emi_reg_locked()
867 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA, in __e1000_access_emi_reg_locked()
870 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, in __e1000_access_emi_reg_locked()
878 * @hw: pointer to the HW structure
882 * Assumes the SW/FW/HW Semaphore is already acquired.
884 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) in e1000_read_emi_reg_locked() argument
888 return __e1000_access_emi_reg_locked(hw, addr, data, true); in e1000_read_emi_reg_locked()
893 * @hw: pointer to the HW structure
897 * Assumes the SW/FW/HW Semaphore is already acquired.
899 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) in e1000_write_emi_reg_locked() argument
903 return __e1000_access_emi_reg_locked(hw, addr, &data, false); in e1000_write_emi_reg_locked()
908 * @hw: pointer to the HW structure
920 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) in e1000_set_eee_pchlan() argument
922 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
928 switch (hw->phy.type) { in e1000_set_eee_pchlan()
943 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
947 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); in e1000_set_eee_pchlan()
957 ret_val = e1000_read_emi_reg_locked(hw, lpa, in e1000_set_eee_pchlan()
963 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); in e1000_set_eee_pchlan()
974 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data); in e1000_set_eee_pchlan()
987 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
988 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, in e1000_set_eee_pchlan()
994 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, in e1000_set_eee_pchlan()
999 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); in e1000_set_eee_pchlan()
1003 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl); in e1000_set_eee_pchlan()
1005 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
1012 * @hw: pointer to the HW structure
1021 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) in e1000_k1_workaround_lpt_lp() argument
1023 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); in e1000_k1_workaround_lpt_lp()
1024 u32 status = E1000_READ_REG(hw, E1000_STATUS); in e1000_k1_workaround_lpt_lp()
1029 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
1034 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_k1_workaround_lpt_lp()
1040 e1000_write_kmrn_reg_locked(hw, in e1000_k1_workaround_lpt_lp()
1049 E1000_WRITE_REG(hw, E1000_FEXTNVM6, in e1000_k1_workaround_lpt_lp()
1053 e1000_write_kmrn_reg_locked(hw, in e1000_k1_workaround_lpt_lp()
1057 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1062 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
1067 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®); in e1000_k1_workaround_lpt_lp()
1089 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); in e1000_k1_workaround_lpt_lp()
1094 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); in e1000_k1_workaround_lpt_lp()
1113 * @hw: pointer to the HW structure
1130 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) in e1000_platform_pm_pch_lpt() argument
1147 if (!hw->mac.max_frame_size) { in e1000_platform_pm_pch_lpt()
1152 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1159 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK; in e1000_platform_pm_pch_lpt()
1170 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000; in e1000_platform_pm_pch_lpt()
1188 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop); in e1000_platform_pm_pch_lpt()
1189 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); in e1000_platform_pm_pch_lpt()
1211 E1000_WRITE_REG(hw, E1000_LTRV, reg); in e1000_platform_pm_pch_lpt()
1214 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK; in e1000_platform_pm_pch_lpt()
1216 E1000_WRITE_REG(hw, E1000_SVT, reg); in e1000_platform_pm_pch_lpt()
1219 reg = E1000_READ_REG(hw, E1000_SVCR); in e1000_platform_pm_pch_lpt()
1226 E1000_WRITE_REG(hw, E1000_SVCR, reg); in e1000_platform_pm_pch_lpt()
1233 * @hw: pointer to the HW structure
1238 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr) in e1000_set_obff_timer_pch_lpt() argument
1254 svcr = E1000_READ_REG(hw, E1000_SVCR); in e1000_set_obff_timer_pch_lpt()
1257 E1000_WRITE_REG(hw, E1000_SVCR, svcr); in e1000_set_obff_timer_pch_lpt()
1264 * @hw: pointer to the HW structure
1272 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) in e1000_enable_ulp_lpt_lp() argument
1279 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1280 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1281 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1282 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1283 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1284 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1287 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { in e1000_enable_ulp_lpt_lp()
1289 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_enable_ulp_lpt_lp()
1291 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_enable_ulp_lpt_lp()
1299 while (!(E1000_READ_REG(hw, E1000_FEXT) & in e1000_enable_ulp_lpt_lp()
1302 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) in e1000_enable_ulp_lpt_lp()
1310 (E1000_READ_REG(hw, E1000_FEXT) & in e1000_enable_ulp_lpt_lp()
1313 if (!(E1000_READ_REG(hw, E1000_FEXT) & in e1000_enable_ulp_lpt_lp()
1318 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_enable_ulp_lpt_lp()
1327 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_enable_ulp_lpt_lp()
1330 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_enable_ulp_lpt_lp()
1332 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_enable_ulp_lpt_lp()
1337 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1338 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1346 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1356 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); in e1000_enable_ulp_lpt_lp()
1362 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC) in e1000_enable_ulp_lpt_lp()
1374 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_enable_ulp_lpt_lp()
1377 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); in e1000_enable_ulp_lpt_lp()
1379 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); in e1000_enable_ulp_lpt_lp()
1383 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_enable_ulp_lpt_lp()
1385 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1386 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { in e1000_enable_ulp_lpt_lp()
1387 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1394 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1399 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1406 * @hw: pointer to the HW structure
1419 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) in e1000_disable_ulp_lpt_lp() argument
1427 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1428 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1429 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1430 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1431 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1432 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1435 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) { in e1000_disable_ulp_lpt_lp()
1438 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_disable_ulp_lpt_lp()
1441 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_disable_ulp_lpt_lp()
1444 if (hw->mac.type == e1000_pch_cnp) in e1000_disable_ulp_lpt_lp()
1447 while (E1000_READ_REG(hw, E1000_FWSM) & in e1000_disable_ulp_lpt_lp()
1459 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_disable_ulp_lpt_lp()
1461 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_disable_ulp_lpt_lp()
1464 mac_reg = E1000_READ_REG(hw, E1000_H2ME); in e1000_disable_ulp_lpt_lp()
1466 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); in e1000_disable_ulp_lpt_lp()
1472 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1478 e1000_toggle_lanphypc_pch_lpt(hw); in e1000_disable_ulp_lpt_lp()
1481 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_disable_ulp_lpt_lp()
1486 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_disable_ulp_lpt_lp()
1488 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_disable_ulp_lpt_lp()
1492 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, in e1000_disable_ulp_lpt_lp()
1498 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_disable_ulp_lpt_lp()
1501 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_disable_ulp_lpt_lp()
1503 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg); in e1000_disable_ulp_lpt_lp()
1508 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); in e1000_disable_ulp_lpt_lp()
1512 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); in e1000_disable_ulp_lpt_lp()
1515 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); in e1000_disable_ulp_lpt_lp()
1526 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_disable_ulp_lpt_lp()
1530 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_disable_ulp_lpt_lp()
1533 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7); in e1000_disable_ulp_lpt_lp()
1535 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg); in e1000_disable_ulp_lpt_lp()
1538 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1540 hw->phy.ops.reset(hw); in e1000_disable_ulp_lpt_lp()
1547 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1554 * @hw: pointer to the HW structure
1560 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) in e1000_check_for_copper_link_ich8lan() argument
1562 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan()
1582 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); in e1000_check_for_copper_link_ich8lan()
1586 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1587 ret_val = e1000_k1_gig_workaround_hv(hw, link); in e1000_check_for_copper_link_ich8lan()
1596 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1599 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex); in e1000_check_for_copper_link_ich8lan()
1600 tipg_reg = E1000_READ_REG(hw, E1000_TIPG); in e1000_check_for_copper_link_ich8lan()
1607 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1617 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg); in e1000_check_for_copper_link_ich8lan()
1619 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1623 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1627 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); in e1000_check_for_copper_link_ich8lan()
1630 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1631 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG, in e1000_check_for_copper_link_ich8lan()
1638 hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1643 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1648 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1652 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1657 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1662 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1666 ret_val = hw->phy.ops.read_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1670 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1679 hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1682 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1686 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1690 ret_val = hw->phy.ops.write_reg_locked(hw, in e1000_check_for_copper_link_ich8lan()
1693 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1706 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1709 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); in e1000_check_for_copper_link_ich8lan()
1712 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); in e1000_check_for_copper_link_ich8lan()
1716 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1717 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1718 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1719 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1720 ret_val = e1000_k1_workaround_lpt_lp(hw, link); in e1000_check_for_copper_link_ich8lan()
1724 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1729 ret_val = e1000_platform_pm_pch_lpt(hw, link); in e1000_check_for_copper_link_ich8lan()
1734 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1736 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1737 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); in e1000_check_for_copper_link_ich8lan()
1739 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1741 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG); in e1000_check_for_copper_link_ich8lan()
1749 if (hw->dev_spec.ich8lan.disable_k1_off == true) in e1000_check_for_copper_link_ich8lan()
1752 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6); in e1000_check_for_copper_link_ich8lan()
1755 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME); in e1000_check_for_copper_link_ich8lan()
1763 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1765 ret_val = e1000_k1_workaround_lv(hw); in e1000_check_for_copper_link_ich8lan()
1770 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1771 ret_val = e1000_link_stall_workaround_hv(hw); in e1000_check_for_copper_link_ich8lan()
1781 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); in e1000_check_for_copper_link_ich8lan()
1784 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) != in e1000_check_for_copper_link_ich8lan()
1788 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); in e1000_check_for_copper_link_ich8lan()
1797 e1000_check_downshift_generic(hw); in e1000_check_for_copper_link_ich8lan()
1800 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1801 ret_val = e1000_set_eee_pchlan(hw); in e1000_check_for_copper_link_ich8lan()
1816 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1823 ret_val = e1000_config_fc_after_link_up_generic(hw); in e1000_check_for_copper_link_ich8lan()
1832 * @hw: pointer to the HW structure
1836 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw) in e1000_init_function_pointers_ich8lan() argument
1840 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1841 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1842 switch (hw->mac.type) { in e1000_init_function_pointers_ich8lan()
1846 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan; in e1000_init_function_pointers_ich8lan()
1857 hw->phy.ops.init_params = e1000_init_phy_params_pchlan; in e1000_init_function_pointers_ich8lan()
1866 * @hw: pointer to the HW structure
1870 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) in e1000_acquire_nvm_ich8lan() argument
1874 ASSERT_CTX_LOCK_HELD(hw); in e1000_acquire_nvm_ich8lan()
1881 * @hw: pointer to the HW structure
1885 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) in e1000_release_nvm_ich8lan() argument
1889 ASSERT_CTX_LOCK_HELD(hw); in e1000_release_nvm_ich8lan()
1894 * @hw: pointer to the HW structure
1899 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) in e1000_acquire_swflag_ich8lan() argument
1906 ASSERT_CTX_LOCK_HELD(hw); in e1000_acquire_swflag_ich8lan()
1909 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_acquire_swflag_ich8lan()
1926 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_acquire_swflag_ich8lan()
1929 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_acquire_swflag_ich8lan()
1938 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", in e1000_acquire_swflag_ich8lan()
1939 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl); in e1000_acquire_swflag_ich8lan()
1941 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_acquire_swflag_ich8lan()
1952 * @hw: pointer to the HW structure
1957 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) in e1000_release_swflag_ich8lan() argument
1963 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_release_swflag_ich8lan()
1967 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_release_swflag_ich8lan()
1969 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); in e1000_release_swflag_ich8lan()
1975 * @hw: pointer to the HW structure
1981 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) in e1000_check_mng_mode_ich8lan() argument
1987 fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_check_mng_mode_ich8lan()
1996 * @hw: pointer to the HW structure
2002 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) in e1000_check_mng_mode_pchlan() argument
2008 fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_check_mng_mode_pchlan()
2016 * @hw: pointer to the HW structure
2025 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) in e1000_rar_set_pch2lan() argument
2031 /* HW expects these in little endian so we reverse the byte order in e1000_rar_set_pch2lan()
2045 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); in e1000_rar_set_pch2lan()
2046 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2047 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); in e1000_rar_set_pch2lan()
2048 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2055 if (index < (u32) (hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
2058 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_rar_set_pch2lan()
2062 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
2063 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2064 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
2065 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch2lan()
2067 e1000_release_swflag_ich8lan(hw); in e1000_rar_set_pch2lan()
2070 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
2071 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
2075 (index - 1), E1000_READ_REG(hw, E1000_FWSM)); in e1000_rar_set_pch2lan()
2085 * @hw: pointer to the HW structure
2094 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) in e1000_rar_set_pch_lpt() argument
2101 /* HW expects these in little endian so we reverse the byte order in e1000_rar_set_pch_lpt()
2114 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); in e1000_rar_set_pch_lpt()
2115 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2116 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); in e1000_rar_set_pch_lpt()
2117 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2124 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
2125 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) & in e1000_rar_set_pch_lpt()
2136 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_rar_set_pch_lpt()
2141 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1), in e1000_rar_set_pch_lpt()
2143 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2144 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1), in e1000_rar_set_pch_lpt()
2146 E1000_WRITE_FLUSH(hw); in e1000_rar_set_pch_lpt()
2148 e1000_release_swflag_ich8lan(hw); in e1000_rar_set_pch_lpt()
2151 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2152 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2164 * @hw: pointer to the HW structure
2171 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, in e1000_update_mc_addr_list_pch2lan() argument
2181 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); in e1000_update_mc_addr_list_pch2lan()
2183 ret_val = hw->phy.ops.acquire(hw); in e1000_update_mc_addr_list_pch2lan()
2187 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_update_mc_addr_list_pch2lan()
2191 for (i = 0; i < hw->mac.mta_reg_count; i++) { in e1000_update_mc_addr_list_pch2lan()
2192 hw->phy.ops.write_reg_page(hw, BM_MTA(i), in e1000_update_mc_addr_list_pch2lan()
2193 (u16)(hw->mac.mta_shadow[i] & in e1000_update_mc_addr_list_pch2lan()
2195 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1), in e1000_update_mc_addr_list_pch2lan()
2196 (u16)((hw->mac.mta_shadow[i] >> 16) & in e1000_update_mc_addr_list_pch2lan()
2200 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_update_mc_addr_list_pch2lan()
2203 hw->phy.ops.release(hw); in e1000_update_mc_addr_list_pch2lan()
2208 * @hw: pointer to the HW structure
2214 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) in e1000_check_reset_block_ich8lan() argument
2223 fwsm = E1000_READ_REG(hw, E1000_FWSM); in e1000_check_reset_block_ich8lan()
2236 * @hw: pointer to the HW structure
2241 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) in e1000_write_smbus_addr() argument
2244 u32 strap = E1000_READ_REG(hw, E1000_STRAP); in e1000_write_smbus_addr()
2251 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); in e1000_write_smbus_addr()
2259 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2272 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); in e1000_write_smbus_addr()
2277 * @hw: pointer to the HW structure
2282 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) in e1000_sw_lcd_config_ich8lan() argument
2284 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2297 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2302 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2303 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2323 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2327 data = E1000_READ_REG(hw, E1000_FEXTNVM); in e1000_sw_lcd_config_ich8lan()
2331 /* Make sure HW does not configure LCD from PHY in e1000_sw_lcd_config_ich8lan()
2334 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_sw_lcd_config_ich8lan()
2335 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2339 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE); in e1000_sw_lcd_config_ich8lan()
2348 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2350 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2351 /* HW configures the SMBus address and LEDs when the in e1000_sw_lcd_config_ich8lan()
2356 ret_val = e1000_write_smbus_addr(hw); in e1000_sw_lcd_config_ich8lan()
2360 data = E1000_READ_REG(hw, E1000_LEDCTL); in e1000_sw_lcd_config_ich8lan()
2361 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, in e1000_sw_lcd_config_ich8lan()
2373 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1, in e1000_sw_lcd_config_ich8lan()
2378 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1), in e1000_sw_lcd_config_ich8lan()
2392 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, in e1000_sw_lcd_config_ich8lan()
2399 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2405 * @hw: pointer to the HW structure
2413 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) in e1000_k1_gig_workaround_hv() argument
2417 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2421 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2425 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2431 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2432 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, in e1000_k1_gig_workaround_hv()
2447 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2448 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, in e1000_k1_gig_workaround_hv()
2464 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), in e1000_k1_gig_workaround_hv()
2471 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), in e1000_k1_gig_workaround_hv()
2477 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); in e1000_k1_gig_workaround_hv()
2480 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2487 * @hw: pointer to the HW structure
2495 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) in e1000_configure_k1_ich8lan() argument
2505 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_configure_k1_ich8lan()
2515 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_configure_k1_ich8lan()
2521 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_configure_k1_ich8lan()
2522 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_configure_k1_ich8lan()
2526 E1000_WRITE_REG(hw, E1000_CTRL, reg); in e1000_configure_k1_ich8lan()
2528 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); in e1000_configure_k1_ich8lan()
2529 E1000_WRITE_FLUSH(hw); in e1000_configure_k1_ich8lan()
2531 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); in e1000_configure_k1_ich8lan()
2532 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_configure_k1_ich8lan()
2533 E1000_WRITE_FLUSH(hw); in e1000_configure_k1_ich8lan()
2541 * @hw: pointer to the HW structure
2546 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2548 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) in e1000_oem_bits_config_ich8lan() argument
2556 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2559 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2563 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2564 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_oem_bits_config_ich8lan()
2569 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM); in e1000_oem_bits_config_ich8lan()
2573 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_oem_bits_config_ich8lan()
2575 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); in e1000_oem_bits_config_ich8lan()
2598 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2599 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2602 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); in e1000_oem_bits_config_ich8lan()
2605 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2613 * @hw: pointer to the HW structure
2615 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) in e1000_set_mdio_slow_mode_hv() argument
2622 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data); in e1000_set_mdio_slow_mode_hv()
2628 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); in e1000_set_mdio_slow_mode_hv()
2636 * @hw: pointer to the HW structure
2638 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) in e1000_hv_phy_workarounds_ich8lan() argument
2645 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2649 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2650 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_hv_phy_workarounds_ich8lan()
2655 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2656 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2657 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2659 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2664 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, in e1000_hv_phy_workarounds_ich8lan()
2670 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2674 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2675 e1000_phy_sw_reset_generic(hw); in e1000_hv_phy_workarounds_ich8lan()
2676 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, in e1000_hv_phy_workarounds_ich8lan()
2684 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2688 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2689 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); in e1000_hv_phy_workarounds_ich8lan()
2690 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2697 ret_val = e1000_k1_gig_workaround_hv(hw, true); in e1000_hv_phy_workarounds_ich8lan()
2702 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2705 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); in e1000_hv_phy_workarounds_ich8lan()
2708 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, in e1000_hv_phy_workarounds_ich8lan()
2714 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); in e1000_hv_phy_workarounds_ich8lan()
2716 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2723 * @hw: pointer to the HW structure
2725 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) in e1000_copy_rx_addrs_to_phy_ich8lan() argument
2733 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2736 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_copy_rx_addrs_to_phy_ich8lan()
2741 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2742 mac_reg = E1000_READ_REG(hw, E1000_RAL(i)); in e1000_copy_rx_addrs_to_phy_ich8lan()
2743 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2745 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2748 mac_reg = E1000_READ_REG(hw, E1000_RAH(i)); in e1000_copy_rx_addrs_to_phy_ich8lan()
2749 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2751 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2756 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_copy_rx_addrs_to_phy_ich8lan()
2759 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2783 * @hw: pointer to the HW structure
2786 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) in e1000_lv_jumbo_workaround_ich8lan() argument
2795 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2799 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2800 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), in e1000_lv_jumbo_workaround_ich8lan()
2809 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2813 addr_high = E1000_READ_REG(hw, E1000_RAH(i)); in e1000_lv_jumbo_workaround_ich8lan()
2816 addr_low = E1000_READ_REG(hw, E1000_RAL(i)); in e1000_lv_jumbo_workaround_ich8lan()
2824 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), in e1000_lv_jumbo_workaround_ich8lan()
2829 e1000_copy_rx_addrs_to_phy_ich8lan(hw); in e1000_lv_jumbo_workaround_ich8lan()
2832 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); in e1000_lv_jumbo_workaround_ich8lan()
2835 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2837 mac_reg = E1000_READ_REG(hw, E1000_RCTL); in e1000_lv_jumbo_workaround_ich8lan()
2839 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2841 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2846 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2851 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2858 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2865 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2868 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2871 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2873 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2876 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2879 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2882 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100); in e1000_lv_jumbo_workaround_ich8lan()
2885 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2886 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | in e1000_lv_jumbo_workaround_ich8lan()
2892 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG); in e1000_lv_jumbo_workaround_ich8lan()
2894 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2896 mac_reg = E1000_READ_REG(hw, E1000_RCTL); in e1000_lv_jumbo_workaround_ich8lan()
2898 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg); in e1000_lv_jumbo_workaround_ich8lan()
2900 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2905 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2910 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2917 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_lv_jumbo_workaround_ich8lan()
2924 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2926 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2929 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2931 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2934 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2937 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2940 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00); in e1000_lv_jumbo_workaround_ich8lan()
2943 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2944 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & in e1000_lv_jumbo_workaround_ich8lan()
2951 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & in e1000_lv_jumbo_workaround_ich8lan()
2958 * @hw: pointer to the HW structure
2960 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) in e1000_lv_phy_workarounds_ich8lan() argument
2966 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2970 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_lv_phy_workarounds_ich8lan()
2974 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2978 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); in e1000_lv_phy_workarounds_ich8lan()
2982 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); in e1000_lv_phy_workarounds_ich8lan()
2984 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
2991 * @hw: pointer to the HW structure
2996 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) in e1000_k1_workaround_lv() argument
3003 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
3007 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg); in e1000_k1_workaround_lv()
3018 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL, in e1000_k1_workaround_lv()
3023 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, in e1000_k1_workaround_lv()
3029 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4); in e1000_k1_workaround_lv()
3032 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg); in e1000_k1_workaround_lv()
3041 * @hw: pointer to the HW structure
3047 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) in e1000_gate_hw_phy_config_ich8lan() argument
3053 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
3056 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); in e1000_gate_hw_phy_config_ich8lan()
3063 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); in e1000_gate_hw_phy_config_ich8lan()
3068 * @hw: pointer to the HW structure
3073 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) in e1000_lan_init_done_ich8lan() argument
3081 data = E1000_READ_REG(hw, E1000_STATUS); in e1000_lan_init_done_ich8lan()
3094 data = E1000_READ_REG(hw, E1000_STATUS); in e1000_lan_init_done_ich8lan()
3096 E1000_WRITE_REG(hw, E1000_STATUS, data); in e1000_lan_init_done_ich8lan()
3101 * @hw: pointer to the HW structure
3103 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) in e1000_post_phy_reset_ich8lan() argument
3110 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
3117 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
3119 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3124 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3133 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
3134 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®); in e1000_post_phy_reset_ich8lan()
3136 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg); in e1000_post_phy_reset_ich8lan()
3140 ret_val = e1000_sw_lcd_config_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3145 ret_val = e1000_oem_bits_config_ich8lan(hw, true); in e1000_post_phy_reset_ich8lan()
3147 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
3149 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_post_phy_reset_ich8lan()
3152 e1000_gate_hw_phy_config_ich8lan(hw, false); in e1000_post_phy_reset_ich8lan()
3156 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
3159 ret_val = e1000_write_emi_reg_locked(hw, in e1000_post_phy_reset_ich8lan()
3162 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
3170 * @hw: pointer to the HW structure
3176 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) in e1000_phy_hw_reset_ich8lan() argument
3183 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
3184 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) in e1000_phy_hw_reset_ich8lan()
3185 e1000_gate_hw_phy_config_ich8lan(hw, true); in e1000_phy_hw_reset_ich8lan()
3187 ret_val = e1000_phy_hw_reset_generic(hw); in e1000_phy_hw_reset_ich8lan()
3191 return e1000_post_phy_reset_ich8lan(hw); in e1000_phy_hw_reset_ich8lan()
3196 * @hw: pointer to the HW structure
3202 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3205 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) in e1000_set_lplu_state_pchlan() argument
3211 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg); in e1000_set_lplu_state_pchlan()
3220 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
3223 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg); in e1000_set_lplu_state_pchlan()
3228 * @hw: pointer to the HW structure
3239 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) in e1000_set_d0_lplu_state_ich8lan() argument
3241 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
3251 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
3255 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3263 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3264 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_set_d0_lplu_state_ich8lan()
3267 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3273 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3280 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3291 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3298 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3304 ret_val = phy->ops.read_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3311 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_ich8lan()
3324 * @hw: pointer to the HW structure
3335 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) in e1000_set_d3_lplu_state_ich8lan() argument
3337 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3344 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3348 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3359 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3366 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3372 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3379 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3389 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3397 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3398 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_set_d3_lplu_state_ich8lan()
3401 ret_val = phy->ops.read_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3408 ret_val = phy->ops.write_reg(hw, in e1000_set_d3_lplu_state_ich8lan()
3418 * @hw: pointer to the HW structure
3424 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) in e1000_valid_nvm_bank_detect_ich8lan() argument
3427 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3436 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3450 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, in e1000_valid_nvm_bank_detect_ich8lan()
3462 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + in e1000_valid_nvm_bank_detect_ich8lan()
3478 eecd = E1000_READ_REG(hw, E1000_EECD); in e1000_valid_nvm_bank_detect_ich8lan()
3495 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, in e1000_valid_nvm_bank_detect_ich8lan()
3506 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + in e1000_valid_nvm_bank_detect_ich8lan()
3524 * @hw: pointer to the HW structure
3531 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_spt() argument
3534 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3535 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3552 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3554 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_read_nvm_spt()
3574 e1000_read_flash_dword_ich8lan(hw, in e1000_read_nvm_spt()
3589 e1000_read_flash_dword_ich8lan(hw, in e1000_read_nvm_spt()
3608 nvm->ops.release(hw); in e1000_read_nvm_spt()
3619 * @hw: pointer to the HW structure
3626 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_ich8lan() argument
3629 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3630 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3645 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3647 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_read_nvm_ich8lan()
3661 ret_val = e1000_read_flash_word_ich8lan(hw, in e1000_read_nvm_ich8lan()
3670 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3681 * @hw: pointer to the HW structure
3686 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) in e1000_flash_cycle_init_ich8lan() argument
3693 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_flash_cycle_init_ich8lan()
3701 /* Clear FCERR and DAEL in hw status by writing 1 */ in e1000_flash_cycle_init_ich8lan()
3704 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3705 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3708 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3724 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3725 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3728 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3738 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_flash_cycle_init_ich8lan()
3751 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3752 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3755 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_init_ich8lan()
3767 * @hw: pointer to the HW structure
3772 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) in e1000_flash_cycle_ich8lan() argument
3780 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ in e1000_flash_cycle_ich8lan()
3781 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3782 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; in e1000_flash_cycle_ich8lan()
3784 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_flash_cycle_ich8lan()
3787 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3788 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_flash_cycle_ich8lan()
3791 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); in e1000_flash_cycle_ich8lan()
3795 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_flash_cycle_ich8lan()
3809 * @hw: pointer to the HW structure
3816 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_dword_ich8lan() argument
3827 return e1000_read_flash_data32_ich8lan(hw, offset, data); in e1000_read_flash_dword_ich8lan()
3832 * @hw: pointer to the HW structure
3839 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_word_ich8lan() argument
3850 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); in e1000_read_flash_word_ich8lan()
3855 * @hw: pointer to the HW structure
3861 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_byte_ich8lan() argument
3870 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3873 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); in e1000_read_flash_byte_ich8lan()
3885 * @hw: pointer to the HW structure
3892 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_data_ich8lan() argument
3907 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3912 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_read_flash_data_ich8lan()
3915 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_read_flash_data_ich8lan()
3920 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); in e1000_read_flash_data_ich8lan()
3921 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_read_flash_data_ich8lan()
3923 ret_val = e1000_flash_cycle_ich8lan(hw, in e1000_read_flash_data_ich8lan()
3932 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); in e1000_read_flash_data_ich8lan()
3944 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_read_flash_data_ich8lan()
3961 * @hw: pointer to the HW structure
3967 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_data32_ich8lan() argument
3979 hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3982 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
3987 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_read_flash_data32_ich8lan()
3993 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; in e1000_read_flash_data32_ich8lan()
4001 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_read_flash_data32_ich8lan()
4003 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_read_flash_data32_ich8lan()
4005 ret_val = e1000_flash_cycle_ich8lan(hw, in e1000_read_flash_data32_ich8lan()
4014 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0); in e1000_read_flash_data32_ich8lan()
4022 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_read_flash_data32_ich8lan()
4039 * @hw: pointer to the HW structure
4046 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, in e1000_write_nvm_ich8lan() argument
4049 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
4050 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
4061 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
4068 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
4075 * @hw: pointer to the HW structure
4084 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) in e1000_update_nvm_checksum_spt() argument
4086 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
4087 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
4094 ret_val = e1000_update_nvm_checksum_generic(hw); in e1000_update_nvm_checksum_spt()
4101 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
4107 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_update_nvm_checksum_spt()
4116 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); in e1000_update_nvm_checksum_spt()
4122 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); in e1000_update_nvm_checksum_spt()
4131 ret_val = e1000_read_flash_dword_ich8lan(hw, in e1000_update_nvm_checksum_spt()
4164 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, in e1000_update_nvm_checksum_spt()
4187 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); in e1000_update_nvm_checksum_spt()
4193 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); in e1000_update_nvm_checksum_spt()
4200 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); in e1000_update_nvm_checksum_spt()
4206 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); in e1000_update_nvm_checksum_spt()
4218 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
4224 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
4237 * @hw: pointer to the HW structure
4246 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) in e1000_update_nvm_checksum_ich8lan() argument
4248 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
4249 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
4256 ret_val = e1000_update_nvm_checksum_generic(hw); in e1000_update_nvm_checksum_ich8lan()
4263 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
4269 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_update_nvm_checksum_ich8lan()
4278 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); in e1000_update_nvm_checksum_ich8lan()
4284 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); in e1000_update_nvm_checksum_ich8lan()
4292 ret_val = e1000_read_flash_word_ich8lan(hw, i + in e1000_update_nvm_checksum_ich8lan()
4314 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4321 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4342 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); in e1000_update_nvm_checksum_ich8lan()
4347 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1, in e1000_update_nvm_checksum_ich8lan()
4359 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); in e1000_update_nvm_checksum_ich8lan()
4371 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4377 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4390 * @hw: pointer to the HW structure
4396 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) in e1000_validate_nvm_checksum_ich8lan() argument
4410 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4427 ret_val = hw->nvm.ops.read(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4433 ret_val = hw->nvm.ops.write(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4436 ret_val = hw->nvm.ops.update(hw); in e1000_validate_nvm_checksum_ich8lan()
4441 return e1000_validate_nvm_checksum_generic(hw); in e1000_validate_nvm_checksum_ich8lan()
4446 * @hw: pointer to the HW structure
4453 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_data_ich8lan() argument
4465 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4474 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4479 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_write_flash_data_ich8lan()
4485 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4487 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16; in e1000_write_flash_data_ich8lan()
4490 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_write_flash_data_ich8lan()
4499 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4500 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_write_flash_data_ich8lan()
4503 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, in e1000_write_flash_data_ich8lan()
4506 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_write_flash_data_ich8lan()
4513 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); in e1000_write_flash_data_ich8lan()
4519 e1000_flash_cycle_ich8lan(hw, in e1000_write_flash_data_ich8lan()
4529 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_write_flash_data_ich8lan()
4544 * @hw: pointer to the HW structure
4550 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_data32_ich8lan() argument
4561 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4566 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4570 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_write_flash_data32_ich8lan()
4577 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4578 hsflctl.regval = E1000_READ_FLASH_REG(hw, in e1000_write_flash_data32_ich8lan()
4582 hsflctl.regval = E1000_READ_FLASH_REG16(hw, in e1000_write_flash_data32_ich8lan()
4592 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4593 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_write_flash_data32_ich8lan()
4596 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, in e1000_write_flash_data32_ich8lan()
4599 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr); in e1000_write_flash_data32_ich8lan()
4601 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data); in e1000_write_flash_data32_ich8lan()
4606 ret_val = e1000_flash_cycle_ich8lan(hw, in e1000_write_flash_data32_ich8lan()
4617 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_write_flash_data32_ich8lan()
4633 * @hw: pointer to the HW structure
4639 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_byte_ich8lan() argument
4646 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); in e1000_write_flash_byte_ich8lan()
4651 * @hw: pointer to the HW structure
4658 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, in e1000_retry_write_flash_dword_ich8lan() argument
4669 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); in e1000_retry_write_flash_dword_ich8lan()
4676 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); in e1000_retry_write_flash_dword_ich8lan()
4688 * @hw: pointer to the HW structure
4695 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, in e1000_retry_write_flash_byte_ich8lan() argument
4703 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); in e1000_retry_write_flash_byte_ich8lan()
4710 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); in e1000_retry_write_flash_byte_ich8lan()
4722 * @hw: pointer to the HW structure
4728 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) in e1000_erase_flash_bank_ich8lan() argument
4730 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4742 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_erase_flash_bank_ich8lan()
4744 /* Determine HW Sector size: Read BERASE bits of hw flash status in e1000_erase_flash_bank_ich8lan()
4746 * 00: The Hw sector is 256 bytes, hence we need to erase 16 in e1000_erase_flash_bank_ich8lan()
4747 * consecutive sectors. The start index for the nth Hw sector in e1000_erase_flash_bank_ich8lan()
4749 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. in e1000_erase_flash_bank_ich8lan()
4750 * The start index for the nth Hw sector can be calculated in e1000_erase_flash_bank_ich8lan()
4752 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 in e1000_erase_flash_bank_ich8lan()
4754 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 in e1000_erase_flash_bank_ich8lan()
4758 /* Hw sector size 256 */ in e1000_erase_flash_bank_ich8lan()
4779 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4787 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_erase_flash_bank_ich8lan()
4792 * Cycle field in hw flash control in e1000_erase_flash_bank_ich8lan()
4794 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4796 E1000_READ_FLASH_REG(hw, in e1000_erase_flash_bank_ich8lan()
4800 E1000_READ_FLASH_REG16(hw, in e1000_erase_flash_bank_ich8lan()
4804 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4805 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS, in e1000_erase_flash_bank_ich8lan()
4808 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, in e1000_erase_flash_bank_ich8lan()
4816 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, in e1000_erase_flash_bank_ich8lan()
4819 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); in e1000_erase_flash_bank_ich8lan()
4827 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_erase_flash_bank_ich8lan()
4842 * @hw: pointer to the HW structure
4849 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) in e1000_valid_led_default_ich8lan() argument
4855 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_ich8lan()
4869 * @hw: pointer to the HW structure
4880 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) in e1000_id_led_init_pchlan() argument
4882 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan()
4891 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4895 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); in e1000_id_led_init_pchlan()
4943 * @hw: pointer to the HW structure
4948 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) in e1000_get_bus_info_ich8lan() argument
4950 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4955 ret_val = e1000_get_bus_info_pcie_generic(hw); in e1000_get_bus_info_ich8lan()
4970 * @hw: pointer to the HW structure
4975 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) in e1000_reset_hw_ich8lan() argument
4977 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
4988 ret_val = e1000_disable_pcie_master_generic(hw); in e1000_reset_hw_ich8lan()
4993 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_ich8lan()
4999 E1000_WRITE_REG(hw, E1000_RCTL, 0); in e1000_reset_hw_ich8lan()
5000 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); in e1000_reset_hw_ich8lan()
5001 E1000_WRITE_FLUSH(hw); in e1000_reset_hw_ich8lan()
5006 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
5008 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K); in e1000_reset_hw_ich8lan()
5010 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K); in e1000_reset_hw_ich8lan()
5013 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
5015 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); in e1000_reset_hw_ich8lan()
5025 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_reset_hw_ich8lan()
5027 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
5037 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
5038 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) in e1000_reset_hw_ich8lan()
5039 e1000_gate_hw_phy_config_ich8lan(hw, true); in e1000_reset_hw_ich8lan()
5041 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_reset_hw_ich8lan()
5049 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg); in e1000_reset_hw_ich8lan()
5050 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg); in e1000_reset_hw_ich8lan()
5052 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw_ich8lan()
5056 /* Configuration space access improve HW level time sync mechanism. in e1000_reset_hw_ich8lan()
5061 e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg); in e1000_reset_hw_ich8lan()
5062 E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg); in e1000_reset_hw_ich8lan()
5065 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
5066 reg = E1000_READ_REG(hw, E1000_FEXTNVM3); in e1000_reset_hw_ich8lan()
5069 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg); in e1000_reset_hw_ich8lan()
5074 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
5078 ret_val = e1000_post_phy_reset_ich8lan(hw); in e1000_reset_hw_ich8lan()
5087 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
5088 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); in e1000_reset_hw_ich8lan()
5090 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_ich8lan()
5091 E1000_READ_REG(hw, E1000_ICR); in e1000_reset_hw_ich8lan()
5093 reg = E1000_READ_REG(hw, E1000_KABGTXD); in e1000_reset_hw_ich8lan()
5095 E1000_WRITE_REG(hw, E1000_KABGTXD, reg); in e1000_reset_hw_ich8lan()
5102 * @hw: pointer to the HW structure
5112 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) in e1000_init_hw_ich8lan() argument
5114 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan()
5121 e1000_initialize_hw_bits_ich8lan(hw); in e1000_init_hw_ich8lan()
5124 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
5130 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
5135 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); in e1000_init_hw_ich8lan()
5141 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
5142 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i); in e1000_init_hw_ich8lan()
5144 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i); in e1000_init_hw_ich8lan()
5145 ret_val = e1000_phy_hw_reset_ich8lan(hw); in e1000_init_hw_ich8lan()
5151 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
5154 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_ich8lan()
5159 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); in e1000_init_hw_ich8lan()
5160 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_init_hw_ich8lan()
5165 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); in e1000_init_hw_ich8lan()
5174 e1000_set_pcie_no_snoop_generic(hw, snoop); in e1000_init_hw_ich8lan()
5178 uint32_t fflt_dbg = E1000_READ_REG(hw, E1000_FFLT_DBG); in e1000_init_hw_ich8lan()
5180 E1000_WRITE_REG(hw, E1000_FFLT_DBG, fflt_dbg); in e1000_init_hw_ich8lan()
5183 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_init_hw_ich8lan()
5185 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); in e1000_init_hw_ich8lan()
5192 e1000_clear_hw_cntrs_ich8lan(hw); in e1000_init_hw_ich8lan()
5199 * @hw: pointer to the HW structure
5204 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) in e1000_initialize_hw_bits_ich8lan() argument
5211 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_initialize_hw_bits_ich8lan()
5214 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
5216 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); in e1000_initialize_hw_bits_ich8lan()
5219 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_initialize_hw_bits_ich8lan()
5221 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); in e1000_initialize_hw_bits_ich8lan()
5224 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_initialize_hw_bits_ich8lan()
5226 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); in e1000_initialize_hw_bits_ich8lan()
5229 reg = E1000_READ_REG(hw, E1000_TARC(0)); in e1000_initialize_hw_bits_ich8lan()
5230 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5233 E1000_WRITE_REG(hw, E1000_TARC(0), reg); in e1000_initialize_hw_bits_ich8lan()
5236 reg = E1000_READ_REG(hw, E1000_TARC(1)); in e1000_initialize_hw_bits_ich8lan()
5237 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) in e1000_initialize_hw_bits_ich8lan()
5242 E1000_WRITE_REG(hw, E1000_TARC(1), reg); in e1000_initialize_hw_bits_ich8lan()
5245 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
5246 reg = E1000_READ_REG(hw, E1000_STATUS); in e1000_initialize_hw_bits_ich8lan()
5248 E1000_WRITE_REG(hw, E1000_STATUS, reg); in e1000_initialize_hw_bits_ich8lan()
5254 reg = E1000_READ_REG(hw, E1000_RFCTL); in e1000_initialize_hw_bits_ich8lan()
5260 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5262 E1000_WRITE_REG(hw, E1000_RFCTL, reg); in e1000_initialize_hw_bits_ich8lan()
5265 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
5266 reg = E1000_READ_REG(hw, E1000_PBECCSTS); in e1000_initialize_hw_bits_ich8lan()
5268 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg); in e1000_initialize_hw_bits_ich8lan()
5270 reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_initialize_hw_bits_ich8lan()
5272 E1000_WRITE_REG(hw, E1000_CTRL, reg); in e1000_initialize_hw_bits_ich8lan()
5280 * @hw: pointer to the HW structure
5288 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) in e1000_setup_link_ich8lan() argument
5298 if (hw->fc.requested_mode == e1000_fc_default) in e1000_setup_link_ich8lan()
5299 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
5304 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
5307 hw->fc.current_mode); in e1000_setup_link_ich8lan()
5309 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_setup_link_ich8lan()
5311 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
5316 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
5317 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
5318 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
5319 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
5320 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
5321 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
5323 ret_val = hw->phy.ops.write_reg(hw, in e1000_setup_link_ich8lan()
5325 hw->fc.pause_time); in e1000_setup_link_ich8lan()
5330 return e1000_set_fc_watermarks_generic(hw); in e1000_setup_link_ich8lan()
5335 * @hw: pointer to the HW structure
5341 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) in e1000_setup_copper_link_ich8lan() argument
5349 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_copper_link_ich8lan()
5352 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_setup_copper_link_ich8lan()
5358 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS, in e1000_setup_copper_link_ich8lan()
5362 ret_val = e1000_read_kmrn_reg_generic(hw, in e1000_setup_copper_link_ich8lan()
5368 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_setup_copper_link_ich8lan()
5374 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5376 ret_val = e1000_copper_link_setup_igp(hw); in e1000_setup_copper_link_ich8lan()
5382 ret_val = e1000_copper_link_setup_m88(hw); in e1000_setup_copper_link_ich8lan()
5388 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_ich8lan()
5393 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, in e1000_setup_copper_link_ich8lan()
5400 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5412 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, in e1000_setup_copper_link_ich8lan()
5421 return e1000_setup_copper_link_generic(hw); in e1000_setup_copper_link_ich8lan()
5426 * @hw: pointer to the HW structure
5432 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) in e1000_setup_copper_link_pch_lpt() argument
5439 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_copper_link_pch_lpt()
5442 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_setup_copper_link_pch_lpt()
5444 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_pch_lpt()
5448 return e1000_setup_copper_link_generic(hw); in e1000_setup_copper_link_pch_lpt()
5453 * @hw: pointer to the HW structure
5461 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, in e1000_get_link_up_info_ich8lan() argument
5468 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); in e1000_get_link_up_info_ich8lan()
5472 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5473 (hw->phy.type == e1000_phy_igp_3) && in e1000_get_link_up_info_ich8lan()
5475 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); in e1000_get_link_up_info_ich8lan()
5483 * @hw: pointer to the HW structure
5496 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) in e1000_kmrn_lock_loss_workaround_ich8lan() argument
5498 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5513 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); in e1000_kmrn_lock_loss_workaround_ich8lan()
5519 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5523 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5532 hw->phy.ops.reset(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5536 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_kmrn_lock_loss_workaround_ich8lan()
5539 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5544 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5552 * @hw: pointer to the HW structure
5558 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, in e1000_set_kmrn_lock_loss_workaround_ich8lan() argument
5561 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5565 if (hw->mac.type != e1000_ich8lan) { in e1000_set_kmrn_lock_loss_workaround_ich8lan()
5577 * @hw: pointer to the HW structure
5585 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) in e1000_igp3_phy_powerdown_workaround_ich8lan() argument
5593 if (hw->phy.type != e1000_phy_igp_3) in e1000_igp3_phy_powerdown_workaround_ich8lan()
5599 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5602 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5607 if (hw->mac.type == e1000_ich8lan) in e1000_igp3_phy_powerdown_workaround_ich8lan()
5608 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5611 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5613 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL, in e1000_igp3_phy_powerdown_workaround_ich8lan()
5617 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5623 reg = E1000_READ_REG(hw, E1000_CTRL); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5624 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST); in e1000_igp3_phy_powerdown_workaround_ich8lan()
5631 * @hw: pointer to the HW structure
5639 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) in e1000_gig_downshift_workaround_ich8lan() argument
5646 if ((hw->mac.type != e1000_ich8lan) || in e1000_gig_downshift_workaround_ich8lan()
5647 (hw->phy.type == e1000_phy_ife)) in e1000_gig_downshift_workaround_ich8lan()
5650 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, in e1000_gig_downshift_workaround_ich8lan()
5655 ret_val = e1000_write_kmrn_reg_generic(hw, in e1000_gig_downshift_workaround_ich8lan()
5661 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, in e1000_gig_downshift_workaround_ich8lan()
5667 * @hw: pointer to the HW structure
5679 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) in e1000_suspend_workarounds_ich8lan() argument
5681 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5687 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_suspend_workarounds_ich8lan()
5690 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5691 u16 phy_reg, device_id = hw->device_id; in e1000_suspend_workarounds_ich8lan()
5697 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5698 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6); in e1000_suspend_workarounds_ich8lan()
5700 E1000_WRITE_REG(hw, E1000_FEXTNVM6, in e1000_suspend_workarounds_ich8lan()
5704 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5712 e1000_read_emi_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5726 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5731 hw->phy.ops.read_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5735 hw->phy.ops.write_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5748 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_suspend_workarounds_ich8lan()
5751 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL, in e1000_suspend_workarounds_ich8lan()
5754 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, in e1000_suspend_workarounds_ich8lan()
5760 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5762 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg); in e1000_suspend_workarounds_ich8lan()
5765 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5767 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); in e1000_suspend_workarounds_ich8lan()
5773 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5775 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); in e1000_suspend_workarounds_ich8lan()
5778 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5781 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_suspend_workarounds_ich8lan()
5783 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5784 e1000_gig_downshift_workaround_ich8lan(hw); in e1000_suspend_workarounds_ich8lan()
5786 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5787 e1000_oem_bits_config_ich8lan(hw, false); in e1000_suspend_workarounds_ich8lan()
5790 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5791 e1000_phy_hw_reset_generic(hw); in e1000_suspend_workarounds_ich8lan()
5793 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5796 e1000_write_smbus_addr(hw); in e1000_suspend_workarounds_ich8lan()
5797 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5805 * @hw: pointer to the HW structure
5813 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw) in e1000_resume_workarounds_pchlan() argument
5818 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5821 ret_val = e1000_init_phy_workarounds_pchlan(hw); in e1000_resume_workarounds_pchlan()
5832 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5835 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5842 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); in e1000_resume_workarounds_pchlan()
5844 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); in e1000_resume_workarounds_pchlan()
5846 if (!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_resume_workarounds_pchlan()
5851 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, in e1000_resume_workarounds_pchlan()
5856 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg); in e1000_resume_workarounds_pchlan()
5859 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0); in e1000_resume_workarounds_pchlan()
5862 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG, in e1000_resume_workarounds_pchlan()
5867 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg); in e1000_resume_workarounds_pchlan()
5871 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5879 * @hw: pointer to the HW structure
5883 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) in e1000_cleanup_led_ich8lan() argument
5887 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5888 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_cleanup_led_ich8lan()
5891 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5897 * @hw: pointer to the HW structure
5901 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) in e1000_led_on_ich8lan() argument
5905 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5906 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_on_ich8lan()
5909 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5915 * @hw: pointer to the HW structure
5919 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) in e1000_led_off_ich8lan() argument
5923 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5924 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_off_ich8lan()
5927 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5933 * @hw: pointer to the HW structure
5937 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) in e1000_setup_led_pchlan() argument
5941 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, in e1000_setup_led_pchlan()
5942 (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5947 * @hw: pointer to the HW structure
5951 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) in e1000_cleanup_led_pchlan() argument
5955 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, in e1000_cleanup_led_pchlan()
5956 (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5961 * @hw: pointer to the HW structure
5965 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) in e1000_led_on_pchlan() argument
5967 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5975 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { in e1000_led_on_pchlan()
5988 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); in e1000_led_on_pchlan()
5993 * @hw: pointer to the HW structure
5997 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) in e1000_led_off_pchlan() argument
5999 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
6007 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { in e1000_led_off_pchlan()
6020 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data); in e1000_led_off_pchlan()
6025 * @hw: pointer to the HW structure
6035 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) in e1000_get_cfg_done_ich8lan() argument
6043 e1000_get_cfg_done_generic(hw); in e1000_get_cfg_done_ich8lan()
6046 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
6047 e1000_lan_init_done_ich8lan(hw); in e1000_get_cfg_done_ich8lan()
6049 ret_val = e1000_get_auto_rd_done_generic(hw); in e1000_get_cfg_done_ich8lan()
6061 status = E1000_READ_REG(hw, E1000_STATUS); in e1000_get_cfg_done_ich8lan()
6063 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA); in e1000_get_cfg_done_ich8lan()
6068 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
6069 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && in e1000_get_cfg_done_ich8lan()
6070 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
6071 e1000_phy_init_script_igp3(hw); in e1000_get_cfg_done_ich8lan()
6074 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { in e1000_get_cfg_done_ich8lan()
6086 * @hw: pointer to the HW structure
6091 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) in e1000_power_down_phy_copper_ich8lan() argument
6094 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
6095 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
6096 e1000_power_down_phy_copper(hw); in e1000_power_down_phy_copper_ich8lan()
6103 * @hw: pointer to the HW structure
6108 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) in e1000_clear_hw_cntrs_ich8lan() argument
6115 e1000_clear_hw_cntrs_base_generic(hw); in e1000_clear_hw_cntrs_ich8lan()
6117 E1000_READ_REG(hw, E1000_ALGNERRC); in e1000_clear_hw_cntrs_ich8lan()
6118 E1000_READ_REG(hw, E1000_RXERRC); in e1000_clear_hw_cntrs_ich8lan()
6119 E1000_READ_REG(hw, E1000_TNCRS); in e1000_clear_hw_cntrs_ich8lan()
6120 E1000_READ_REG(hw, E1000_CEXTERR); in e1000_clear_hw_cntrs_ich8lan()
6121 E1000_READ_REG(hw, E1000_TSCTC); in e1000_clear_hw_cntrs_ich8lan()
6122 E1000_READ_REG(hw, E1000_TSCTFC); in e1000_clear_hw_cntrs_ich8lan()
6124 E1000_READ_REG(hw, E1000_MGTPRC); in e1000_clear_hw_cntrs_ich8lan()
6125 E1000_READ_REG(hw, E1000_MGTPDC); in e1000_clear_hw_cntrs_ich8lan()
6126 E1000_READ_REG(hw, E1000_MGTPTC); in e1000_clear_hw_cntrs_ich8lan()
6128 E1000_READ_REG(hw, E1000_IAC); in e1000_clear_hw_cntrs_ich8lan()
6129 E1000_READ_REG(hw, E1000_ICRXOC); in e1000_clear_hw_cntrs_ich8lan()
6132 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
6133 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
6134 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
6135 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
6136 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
6139 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
6143 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6144 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6145 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6146 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6147 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6148 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6149 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6150 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6151 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6152 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6153 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6154 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6155 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6156 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
6158 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()
6164 * @hw: pointer to the HW structure
6177 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time) in e1000_configure_k0s_lpt() argument
6187 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL, in e1000_configure_k0s_lpt()
6196 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL, in e1000_configure_k0s_lpt()