Lines Matching +full:sync +full:- +full:update +full:- +full:mask
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
145 /* mask to determine if packets should be dropped due to frame errors */
153 /* Same mask, but for extended and packet split descriptors */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
265 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
326 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
560 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
564 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
579 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
602 /* This defines the bits that are set in the Interrupt Mask
617 /* Interrupt Mask Set */
628 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
630 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
640 /* Extended Interrupt Mask Set */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
743 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
744 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
751 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
755 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
763 /* HH Time Sync */
765 #define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
766 #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
767 #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
770 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
822 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
824 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
833 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
834 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
835 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
838 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
987 /* 1000BASE-T Control Register */
1003 /* 1000BASE-T Status Register */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1052 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1053 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
1056 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
1057 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
1154 /* Mask bits for fields in Word 0x24 of the NVM */
1163 /* Mask bits for fields in Word 0x0f of the NVM */
1169 /* Mask bits for fields in Word 0x1a of the NVM */
1172 /* Mask bits for fields in Word 0x03 of the EEPROM */
1193 /* NVM Commands - Microwire */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1517 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */