Lines Matching +full:smbus +full:- +full:timeout +full:- +full:disable
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
76 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
82 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
733 /* Number of 100 microseconds we wait for PCI Express master disable */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
822 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
987 /* 1000BASE-T Control Register */
1003 /* 1000BASE-T Status Register */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1043 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1193 /* NVM Commands - Microwire */
1198 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */