Lines Matching +full:rx +full:- +full:queue +full:- +full:3
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
17 3. Neither the name of the Intel Corporation nor the names of its
71 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
198 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
205 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
206 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
207 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
208 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
210 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
211 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
212 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
258 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
281 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
424 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
474 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */
544 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
546 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
547 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
548 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
549 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
551 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
555 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
564 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
565 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
566 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
567 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
585 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
586 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
587 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
588 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
589 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
590 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
591 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
592 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
618 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
621 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
622 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
623 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
624 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
630 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
631 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
632 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
633 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
640 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
641 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
642 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
643 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
644 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
645 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
646 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
647 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
653 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
654 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
657 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
658 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
659 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
660 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
661 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
662 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
663 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
664 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
710 #define E1000_ERR_CONFIG 3
727 /* Loop limit on how long we wait for auto-negotiation to complete */
742 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
743 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
768 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
769 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
775 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
813 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
822 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
831 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
832 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
865 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
869 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
880 #define E1000_PCS_STATUS_DEV_I354 3
976 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
986 /* 1000BASE-T Control Register */
1002 /* 1000BASE-T Status Register */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1460 /* DMA Coalescing Rx Threshold */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1475 /* Rx Traffic Rate Threshold */
1477 /* Rx packet rate in current window */
1480 /* DMA Coal Rx Traffic Current Count */
1483 /* Flow ctrl Rx Threshold High val */
1489 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1490 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */