Lines Matching +full:rate +full:- +full:lp +full:- +full:ms
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
727 /* Loop limit on how long we wait for auto-negotiation to complete */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
871 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
889 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
890 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
967 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
968 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
969 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
970 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
971 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
972 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
973 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
974 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
975 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
976 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
980 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
981 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
982 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
983 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
984 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
986 /* 1000BASE-T Control Register */
1002 /* 1000BASE-T Status Register */
1004 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
1005 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1006 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1200 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1475 /* Rx Traffic Rate Threshold */
1477 /* Rx packet rate in current window */